Lines Matching +full:per +full:- +full:device
10 * vxge-config.h: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
12 * Copyright(c) 2002-2010 Exar Corp.
27 (((size) - (((u64)adrs) & ((size)-1))) & ((size)-1))
46 * @test: C-condition to check
145 VXGE_HW_EOF_TRACE_BUF = -1
149 * enum enum vxge_hw_device_link_state - Link state enumeration.
162 * enum enum vxge_hw_fw_upgrade_code - FW upgrade return codes.
177 * enum enum vxge_hw_fw_upgrade_err_code - FW upgrade error codes.
203 * struct vxge_hw_device_date - Date Format
228 * struct vxge_hw_fifo_config - Configuration of fifo.
231 * blocks per queue.
232 * @max_frags: Max number of Tx buffers per TxDL (that is, per single
237 * by-page allocation of descriptors. 128K bytes is the
239 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data
243 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
288 * struct vxge_hw_ring_config - Ring configurations.
297 * @greedy_return: If Set it forces the device to return absolutely all RxD
299 * triggers. If Clear, then if the device has already returned
301 * previous timer interrupt triggered, then the device is not
340 * struct vxge_hw_vp_config - Configuration of virtual path
350 * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to
353 * 0 - Do not strip the VLAN tag.
354 * 1 - Strip the VLAN tag. Regardless of this setting, VLAN tags are
389 * struct vxge_hw_device_config - Device configuration.
392 * @intr_mode: Line, or MSI-X interrupt.
402 * Contains per-device configuration parameters, including:
403 * - stats sampling interval, etc.
407 * - fifos and rings;
408 * - MAC (done at firmware level).
462 * function vxge_uld_link_up_f - Link-Up callback provided by driver.
463 * @devh: HW device handle.
464 * Link-up notification callback provided by the driver.
465 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
472 * function vxge_uld_link_down_f - Link-Down callback provided by
474 * @devh: HW device handle.
476 * Link-Down notification callback provided by the driver.
477 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
484 * function vxge_uld_crit_err_f - Critical Error notification callback.
485 * @devh: HW device handle.
486 * (typically - at HW device iinitialization time).
491 * Link-Down notification callback provided by the driver.
492 * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}.
499 * struct vxge_hw_uld_cbs - driver "slow-path" callbacks.
504 * Driver slow-path (per-driver) callbacks.
520 * struct __vxge_hw_blockpool_entry - Block private data structure
541 * struct __vxge_hw_blockpool - Block Pool
542 * @hldev: HW device
563 * enum enum __vxge_hw_channel_type - Enumerated channel types.
567 * @VXGE_HW_CHANNEL_TYPE_MAX: Maximum number of HW-supported
570 * Enumerated channel types. Currently there are only two link-layer
571 * channels - Titan fifo and Titan ring. In the future the list will grow.
584 * @devh: Device handle. HW device object that contains _this_ channel.
599 * 1) posted but not yet consumed by Titan device;
604 * position in the channel, which'll contain next to-be-posted
608 * to-be-completed descriptor.
613 * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize
614 * to store per-operation control information.
616 * @userdata: Per-channel opaque (void*) user-defined context, which may be
650 * struct __vxge_hw_virtualpath - Virtual Path
654 * @hldev: Hal device
707 * struct __vxge_hw_vpath_handle - List item to store callback information
721 * HW device object.
724 * struct __vxge_hw_device - Hal device object
727 * @pdev: Physical device handle
731 * HW device object. Represents Titan adapter
782 * struct vxge_hw_device_hw_info - Device information
833 * struct vxge_hw_device_attr - Device memory spaces.
835 * @pdev: PCI device object.
837 * Device memory spaces. Includes configuration, BAR0 etc. per device
838 * mapped memories. Also, includes a pointer to OS-specific PCI device object.
846 #define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls) (hldev->link_state = ls)
881 * struct __vxge_hw_ring - Ring channel.
886 * @config: Ring configuration, part of device configuration
890 * as per Titan User Guide.
891 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Titan spec,
892 * 1-buffer mode descriptor is 32 byte long, etc.
893 * @rxd_priv_size: Per RxD size reserved (by HW) for driver to keep
894 * per-descriptor data (e.g., DMA handle for Solaris)
895 * @per_rxd_space: Per rxd space requested by driver
896 * @rxds_per_block: Number of descriptors per hardware-defined RxD
897 * block. Depends on the (1-, 3-, 5-) buffer mode.
904 * @rxd_init: Channel's descriptor-initialize callback.
908 * @rxd_term: Channel's descriptor-terminate callback. If not NULL,
958 * enum enum vxge_hw_txdl_state - Descriptor (TXDL) state.
962 * device.
964 * filling-in and posting later.
976 * struct __vxge_hw_fifo - Fifo.
980 * @config: Fifo configuration, part of device configuration
984 * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
987 * per-TxDL HW private space (struct __vxge_hw_fifo_txdl_priv).
988 * @priv_size: Per-Tx descriptor space reserved for driver
990 * @per_txdl_space: Per txdl private space for the driver
994 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
1038 * struct __vxge_hw_fifo_txdl_priv - Transmit descriptor HW-private data.
1040 * @dma_handle: DMA handle used to map the descriptor onto device.
1043 * Each memblock is a contiguous block of DMA-able memory.
1047 * @align_vaddr: Virtual address of the per-TxDL area in memory used for
1048 * alignement. Used to place one or more mis-aligned fragments
1070 * Per-transmit decsriptor HW-private data. HW uses the space to keep DMA
1072 * to allocate additional per-descriptor space for its own (driver-specific)
1097 * struct __vxge_hw_non_offload_db_wrapper - Non-offload Doorbell Wrapper
1098 * @control_0: Bits 0 to 7 - Doorbell type.
1099 * Bits 8 to 31 - Reserved.
1100 * Bits 32 to 39 - The highest TxD in this TxDL.
1101 * Bits 40 to 47 - Reserved.
1102 * Bits 48 to 55 - Reserved.
1103 * Bits 56 to 63 - No snoop flags.
1107 * FIFO. All non-offload doorbell wrapper fields must be written by the host as
1133 * struct vxge_hw_fifo_txd - Transmit Descriptor
1134 * @control_0: Bits 0 to 6 - Reserved.
1135 * Bit 7 - List Ownership. This field should be initialized
1139 * the list. Note - This field is only valid in TxD0. Additionally,
1140 * for multi-list sequences, the driver should not release any
1141 * buffers until the ownership of the last list in the multi-list
1143 * Bits 8 to 11 - Reserved
1144 * Bits 12 to 15 - Transfer_Code. This field is only valid in
1148 * Bits 16 to 17 - Host steering. This field allows the host to
1158 * Bits 18 to 21 - Reserved
1159 * Bits 22 to 23 - Gather_Code. This field is set by the host and
1162 * 00: Middle of a multi-descriptor frame.
1166 * For multi-descriptor frames, the only valid gather code sequence
1169 * Bits 24 to 27 - Reserved
1170 * Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation
1173 * 00 - classic mode (best guess)
1174 * 01 - LLC
1175 * 10 - SNAP
1176 * 11 - DIX
1182 * 0x8870 Jumbo-SNAP encoding.
1186 * Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag.
1189 * Bits 31 to 33 - Reserved.
1190 * Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size
1191 * This field is meaningful only when LSO_Control is non-zero.
1203 * Bits 48 to 63 - Buffer_Size. Number of valid bytes in the
1206 * Bits 32 to 63 - This value is written by the adapter upon
1209 * returned for any non-LSO operation.
1210 * @control_1: Bits 0 to 4 - Reserved.
1211 * Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum
1213 * Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload.
1217 * Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload.
1221 * Bits 8 to 14 - Reserved.
1222 * Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to
1226 * Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag
1230 * Bits 32 to 33 - Reserved.
1231 * Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt
1234 * Bits 40 to 42 - Reserved.
1235 * Bit 43 - Set to 1 to exclude the frame from bandwidth metering
1238 * Bits 44 to 45 - Reserved.
1239 * Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to
1241 * have been transmitted. In order to have per-frame interrupts,
1242 * the driver should place a maximum of one frame per list. This
1244 * Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter
1248 * Bits 48 to 63 - Reserved.
1298 * struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring
1301 * @control_0:Bits 0 to 6 - RTH_Bucket get
1302 * Bit 7 - Own Descriptor ownership bit. This bit is set to 1
1304 * 0 - Host owns RxD and buffer.
1305 * 1 - The adapter owns RxD and buffer.
1306 * Bit 8 - Fast_Path_Eligible When set, indicates that the
1318 * Bit 9 - L3 Checksum Correct
1319 * Bit 10 - L4 Checksum Correct
1320 * Bit 11 - Reserved
1321 * Bit 12 to 15 - This field is written by the adapter. It is
1323 * 0x0 - Transfer OK
1324 * 0x4 - RDA Failure During Transfer
1325 * 0x5 - Unparseable Packet, such as unknown IPv6 header.
1326 * 0x6 - Frame integrity error (FCS or ECC).
1327 * 0x7 - Buffer Size Error. The provided buffer(s) were not
1329 * 0x8 - Internal ECC Error. RxD corrupted.
1330 * 0x9 - IPv4 Checksum error
1331 * 0xA - TCP/UDP Checksum error
1332 * 0xF - Unknown Error or Multiple Error. Indicates an
1334 * Bit 16 - SYN The adapter sets this field to indicate that
1338 * Bit 17 - Is ICMP
1339 * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the
1342 * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the
1345 * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash
1347 * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN
1349 * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation
1351 * 0x0 - Ethernet DIX
1352 * 0x1 - LLC
1353 * 0x2 - SNAP (includes Jumbo-SNAP)
1354 * 0x3 - IPX
1355 * Bit 27 - IS_IPV4 Set to '1' if the frame contains an IPv4 packet.
1356 * Bit 28 - IS_IPV6 Set to '1' if the frame contains an IPv6 packet.
1357 * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a fragmented
1359 * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment.
1360 * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message.
1361 * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that
1365 * Bit 48 to 63 - L4_Checksum[0:15] The TCP/UDP checksum value that
1369 * @control_1:Bits 0 to 1 - Reserved
1370 * Bits 2 to 15 - Buffer0_Size.This field is set by the host and
1376 * Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid if
1378 * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable portion
1380 * populated even if VLAN-tag stripping is enabled.
1443 * struct vxge_hw_rth_hash_types - RTH hash types.
1476 * vxge_hw_ring_rxd_size_get - Get the size of ring descriptor.
1487 * vxge_hw_ring_rxds_per_block_get - Get the number of rxds per block.
1494 return (u32)((VXGE_HW_BLOCK_SIZE-16) / in vxge_hw_ring_rxds_per_block_get()
1499 * vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor.
1503 * the receive buffer should be already mapped to the device
1506 * Prepare 1-buffer-mode Rx descriptor for posting
1509 * This inline helper-function does not return any parameters and always
1520 rxdp->buffer0_ptr = dma_pointer; in vxge_hw_ring_rxd_1b_set()
1521 rxdp->control_1 &= ~VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK; in vxge_hw_ring_rxd_1b_set()
1522 rxdp->control_1 |= VXGE_HW_RING_RXD_1_BUFFER0_SIZE(size); in vxge_hw_ring_rxd_1b_set()
1526 * vxge_hw_ring_rxd_1b_get - Get data from the completed 1-buf
1534 * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor.
1535 * This inline helper-function uses completed descriptor to populate receive
1548 (u32)VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1); in vxge_hw_ring_rxd_1b_get()
1552 * vxge_hw_ring_rxd_1b_info_get - Get extended information associated with
1569 rxd_info->syn_flag = in vxge_hw_ring_rxd_1b_info_get()
1570 (u32)VXGE_HW_RING_RXD_SYN_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1571 rxd_info->is_icmp = in vxge_hw_ring_rxd_1b_info_get()
1572 (u32)VXGE_HW_RING_RXD_IS_ICMP_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1573 rxd_info->fast_path_eligible = in vxge_hw_ring_rxd_1b_info_get()
1574 (u32)VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1575 rxd_info->l3_cksum_valid = in vxge_hw_ring_rxd_1b_info_get()
1576 (u32)VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1577 rxd_info->l3_cksum = in vxge_hw_ring_rxd_1b_info_get()
1578 (u32)VXGE_HW_RING_RXD_L3_CKSUM_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1579 rxd_info->l4_cksum_valid = in vxge_hw_ring_rxd_1b_info_get()
1580 (u32)VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1581 rxd_info->l4_cksum = in vxge_hw_ring_rxd_1b_info_get()
1582 (u32)VXGE_HW_RING_RXD_L4_CKSUM_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1583 rxd_info->frame = in vxge_hw_ring_rxd_1b_info_get()
1584 (u32)VXGE_HW_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1585 rxd_info->proto = in vxge_hw_ring_rxd_1b_info_get()
1586 (u32)VXGE_HW_RING_RXD_FRAME_PROTO_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1587 rxd_info->is_vlan = in vxge_hw_ring_rxd_1b_info_get()
1588 (u32)VXGE_HW_RING_RXD_IS_VLAN_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1589 rxd_info->vlan = in vxge_hw_ring_rxd_1b_info_get()
1590 (u32)VXGE_HW_RING_RXD_VLAN_TAG_GET(rxdp->control_1); in vxge_hw_ring_rxd_1b_info_get()
1591 rxd_info->rth_bucket = in vxge_hw_ring_rxd_1b_info_get()
1592 (u32)VXGE_HW_RING_RXD_RTH_BUCKET_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1593 rxd_info->rth_it_hit = in vxge_hw_ring_rxd_1b_info_get()
1594 (u32)VXGE_HW_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1595 rxd_info->rth_spdm_hit = in vxge_hw_ring_rxd_1b_info_get()
1596 (u32)VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1597 rxd_info->rth_hash_type = in vxge_hw_ring_rxd_1b_info_get()
1598 (u32)VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0); in vxge_hw_ring_rxd_1b_info_get()
1599 rxd_info->rth_value = in vxge_hw_ring_rxd_1b_info_get()
1600 (u32)VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1); in vxge_hw_ring_rxd_1b_info_get()
1604 * vxge_hw_ring_rxd_private_get - Get driver private per-descriptor data
1609 * driver requests per-descriptor space via vxge_hw_ring_attr.
1615 return (void *)(size_t)rxdp->host_control; in vxge_hw_ring_rxd_private_get()
1619 * vxge_hw_fifo_txdl_cksum_set_bits - Offload checksum.
1637 txdp->control_1 |= cksum_bits; in vxge_hw_fifo_txdl_cksum_set_bits()
1641 * vxge_hw_fifo_txdl_mss_set - Set MSS.
1658 txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_EN; in vxge_hw_fifo_txdl_mss_set()
1659 txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_MSS(mss); in vxge_hw_fifo_txdl_mss_set()
1663 * vxge_hw_fifo_txdl_vlan_set - Set VLAN tag.
1674 txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_ENABLE; in vxge_hw_fifo_txdl_vlan_set()
1675 txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_TAG(vlan_tag); in vxge_hw_fifo_txdl_vlan_set()
1679 * vxge_hw_fifo_txdl_private_get - Retrieve per-descriptor private data.
1682 * Retrieve per-descriptor private data.
1683 * Note that driver requests per-descriptor space via
1693 return (void *)(size_t)txdp->host_control; in vxge_hw_fifo_txdl_private_get()
1697 * struct vxge_hw_ring_attr - Ring open "template".
1701 * @rxd_init: Ring's descriptor-initialize callback.
1705 * @rxd_term: Ring's descriptor-terminate callback. If not NULL,
1708 * @userdata: User-defined "context" of _that_ ring. Passed back to the
1711 * reserved by HW per each receive descriptor.
1740 * function vxge_hw_fifo_callback_f - FIFO callback.
1744 * @txdl_priv: Pointer to per txdl space allocated
1745 * @t_code: Transfer code, as per Titan User Guide.
1751 * @userdata: Opaque per-fifo data specified at fifo open
1754 * Fifo completion callback (type declaration). A single per-fifo
1762 * - vxge_hw_fifo_txdl_next_completed()
1767 * Non-zero @t_code means failure to process transmit descriptor.
1778 * function vxge_hw_fifo_txdl_term_f - Terminate descriptor callback.
1780 * @txdl_priv: Pointer to per txdl space allocated
1782 * @userdata: Per-fifo user data (a.k.a. context) specified at
1788 * de-allocating the ring and associated data structures
1798 * struct vxge_hw_fifo_attr - Fifo open "template".
1802 * @txdl_term: Fifo's descriptor-terminate callback. If not NULL,
1805 * @userdata: User-defined "context" of _that_ fifo. Passed back to the
1808 * reserved by HW per each transmit descriptor. Can be used to
1835 * struct vxge_hw_vpath_attr - Attributes of virtual path
1837 * @ring_attr: Attributes of ring for non-offload receive
1838 * @fifo_attr: Attributes of fifo for non-offload transmit
1857 * vxge_hw_device_link_state_get - Get link state.
1858 * @devh: HW device handle.
1867 return devh->link_state; in vxge_hw_device_link_state_get()
1936 tmp -= misaligned; in vxge_os_dma_free()
1941 * __vxge_hw_mempool_item_priv - will return pointer on per item private space
1951 void *memblock = mempool->memblocks_arr[memblock_idx]; in __vxge_hw_mempool_item_priv()
1954 offset = (u32)((u8 *)item - (u8 *)memblock); in __vxge_hw_mempool_item_priv()
1955 vxge_assert(offset >= 0 && (u32)offset < mempool->memblock_size); in __vxge_hw_mempool_item_priv()
1957 (*memblock_item_idx) = (u32) offset / mempool->item_size; in __vxge_hw_mempool_item_priv()
1958 vxge_assert((*memblock_item_idx) < mempool->items_per_memblock); in __vxge_hw_mempool_item_priv()
1960 return (u8 *)mempool->memblocks_priv_arr[memblock_idx] + in __vxge_hw_mempool_item_priv()
1961 (*memblock_item_idx) * mempool->items_priv_size; in __vxge_hw_mempool_item_priv()
1965 * __vxge_hw_fifo_txdl_priv - Return the max fragments allocated
1976 (((char *)((ulong)txdp->host_control)) + in __vxge_hw_fifo_txdl_priv()
1977 fifo->per_txdl_space); in __vxge_hw_fifo_txdl_priv()
2032 * Provides logging facilities. Can be customized on per-module