Lines Matching +full:0 +full:x2000
32 #define KS_DMA_TX_CTRL 0x0000
33 #define DMA_TX_ENABLE 0x00000001
34 #define DMA_TX_CRC_ENABLE 0x00000002
35 #define DMA_TX_PAD_ENABLE 0x00000004
36 #define DMA_TX_LOOPBACK 0x00000100
37 #define DMA_TX_FLOW_ENABLE 0x00000200
38 #define DMA_TX_CSUM_IP 0x00010000
39 #define DMA_TX_CSUM_TCP 0x00020000
40 #define DMA_TX_CSUM_UDP 0x00040000
41 #define DMA_TX_BURST_SIZE 0x3F000000
43 #define KS_DMA_RX_CTRL 0x0004
44 #define DMA_RX_ENABLE 0x00000001
45 #define KS884X_DMA_RX_MULTICAST 0x00000002
46 #define DMA_RX_PROMISCUOUS 0x00000004
47 #define DMA_RX_ERROR 0x00000008
48 #define DMA_RX_UNICAST 0x00000010
49 #define DMA_RX_ALL_MULTICAST 0x00000020
50 #define DMA_RX_BROADCAST 0x00000040
51 #define DMA_RX_FLOW_ENABLE 0x00000200
52 #define DMA_RX_CSUM_IP 0x00010000
53 #define DMA_RX_CSUM_TCP 0x00020000
54 #define DMA_RX_CSUM_UDP 0x00040000
55 #define DMA_RX_BURST_SIZE 0x3F000000
60 #define KS_DMA_TX_START 0x0008
61 #define KS_DMA_RX_START 0x000C
62 #define DMA_START 0x00000001
64 #define KS_DMA_TX_ADDR 0x0010
65 #define KS_DMA_RX_ADDR 0x0014
67 #define DMA_ADDR_LIST_MASK 0xFFFFFFFC
71 #define KS884X_MULTICAST_0_OFFSET 0x0020
72 #define KS884X_MULTICAST_1_OFFSET 0x0021
73 #define KS884X_MULTICAST_2_OFFSET 0x0022
74 #define KS884x_MULTICAST_3_OFFSET 0x0023
76 #define KS884X_MULTICAST_4_OFFSET 0x0024
77 #define KS884X_MULTICAST_5_OFFSET 0x0025
78 #define KS884X_MULTICAST_6_OFFSET 0x0026
79 #define KS884X_MULTICAST_7_OFFSET 0x0027
84 #define KS884X_INTERRUPTS_ENABLE 0x0028
86 #define KS884X_INTERRUPTS_STATUS 0x002C
88 #define KS884X_INT_RX_STOPPED 0x02000000
89 #define KS884X_INT_TX_STOPPED 0x04000000
90 #define KS884X_INT_RX_OVERRUN 0x08000000
91 #define KS884X_INT_TX_EMPTY 0x10000000
92 #define KS884X_INT_RX 0x20000000
93 #define KS884X_INT_TX 0x40000000
94 #define KS884X_INT_PHY 0x80000000
105 #define KS_ADD_ADDR_0_LO 0x0080
107 #define KS_ADD_ADDR_0_HI 0x0084
109 #define KS_ADD_ADDR_1_LO 0x0088
111 #define KS_ADD_ADDR_1_HI 0x008C
113 #define KS_ADD_ADDR_2_LO 0x0090
115 #define KS_ADD_ADDR_2_HI 0x0094
117 #define KS_ADD_ADDR_3_LO 0x0098
119 #define KS_ADD_ADDR_3_HI 0x009C
121 #define KS_ADD_ADDR_4_LO 0x00A0
123 #define KS_ADD_ADDR_4_HI 0x00A4
125 #define KS_ADD_ADDR_5_LO 0x00A8
127 #define KS_ADD_ADDR_5_HI 0x00AC
129 #define KS_ADD_ADDR_6_LO 0x00B0
131 #define KS_ADD_ADDR_6_HI 0x00B4
133 #define KS_ADD_ADDR_7_LO 0x00B8
135 #define KS_ADD_ADDR_7_HI 0x00BC
137 #define KS_ADD_ADDR_8_LO 0x00C0
139 #define KS_ADD_ADDR_8_HI 0x00C4
141 #define KS_ADD_ADDR_9_LO 0x00C8
143 #define KS_ADD_ADDR_9_HI 0x00CC
145 #define KS_ADD_ADDR_A_LO 0x00D0
147 #define KS_ADD_ADDR_A_HI 0x00D4
149 #define KS_ADD_ADDR_B_LO 0x00D8
151 #define KS_ADD_ADDR_B_HI 0x00DC
153 #define KS_ADD_ADDR_C_LO 0x00E0
155 #define KS_ADD_ADDR_C_HI 0x00E4
157 #define KS_ADD_ADDR_D_LO 0x00E8
159 #define KS_ADD_ADDR_D_HI 0x00EC
161 #define KS_ADD_ADDR_E_LO 0x00F0
163 #define KS_ADD_ADDR_E_HI 0x00F4
165 #define KS_ADD_ADDR_F_LO 0x00F8
167 #define KS_ADD_ADDR_F_HI 0x00FC
169 #define ADD_ADDR_HI_MASK 0x0000FFFF
170 #define ADD_ADDR_ENABLE 0x80000000
176 #define KS884X_ADDR_0_OFFSET 0x0200
177 #define KS884X_ADDR_1_OFFSET 0x0201
179 #define KS884X_ADDR_2_OFFSET 0x0202
180 #define KS884X_ADDR_3_OFFSET 0x0203
182 #define KS884X_ADDR_4_OFFSET 0x0204
183 #define KS884X_ADDR_5_OFFSET 0x0205
186 #define KS884X_BUS_CTRL_OFFSET 0x0210
188 #define BUS_SPEED_125_MHZ 0x0000
189 #define BUS_SPEED_62_5_MHZ 0x0001
190 #define BUS_SPEED_41_66_MHZ 0x0002
191 #define BUS_SPEED_25_MHZ 0x0003
194 #define KS884X_EEPROM_CTRL_OFFSET 0x0212
196 #define EEPROM_CHIP_SELECT 0x0001
197 #define EEPROM_SERIAL_CLOCK 0x0002
198 #define EEPROM_DATA_OUT 0x0004
199 #define EEPROM_DATA_IN 0x0008
200 #define EEPROM_ACCESS_ENABLE 0x0010
203 #define KS884X_MEM_INFO_OFFSET 0x0214
205 #define RX_MEM_TEST_FAILED 0x0008
206 #define RX_MEM_TEST_FINISHED 0x0010
207 #define TX_MEM_TEST_FAILED 0x0800
208 #define TX_MEM_TEST_FINISHED 0x1000
211 #define KS884X_GLOBAL_CTRL_OFFSET 0x0216
212 #define GLOBAL_SOFTWARE_RESET 0x0001
214 #define KS8841_POWER_MANAGE_OFFSET 0x0218
217 #define KS8841_WOL_CTRL_OFFSET 0x021A
218 #define KS8841_WOL_MAGIC_ENABLE 0x0080
219 #define KS8841_WOL_FRAME3_ENABLE 0x0008
220 #define KS8841_WOL_FRAME2_ENABLE 0x0004
221 #define KS8841_WOL_FRAME1_ENABLE 0x0002
222 #define KS8841_WOL_FRAME0_ENABLE 0x0001
225 #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
226 #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
227 #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
230 #define KS884X_IACR_P 0x04A0
234 #define KS884X_IADR1_P 0x04A2
235 #define KS884X_IADR2_P 0x04A4
236 #define KS884X_IADR3_P 0x04A6
237 #define KS884X_IADR4_P 0x04A8
238 #define KS884X_IADR5_P 0x04AA
254 #define KS884X_P1MBCR_P 0x04D0
255 #define KS884X_P1MBSR_P 0x04D2
256 #define KS884X_PHY1ILR_P 0x04D4
257 #define KS884X_PHY1IHR_P 0x04D6
258 #define KS884X_P1ANAR_P 0x04D8
259 #define KS884X_P1ANLPR_P 0x04DA
262 #define KS884X_P2MBCR_P 0x04E0
263 #define KS884X_P2MBSR_P 0x04E2
264 #define KS884X_PHY2ILR_P 0x04E4
265 #define KS884X_PHY2IHR_P 0x04E6
266 #define KS884X_P2ANAR_P 0x04E8
267 #define KS884X_P2ANLPR_P 0x04EA
272 #define KS884X_PHY_CTRL_OFFSET 0x00
275 #define PHY_REG_CTRL 0
277 #define PHY_RESET 0x8000
278 #define PHY_LOOPBACK 0x4000
279 #define PHY_SPEED_100MBIT 0x2000
280 #define PHY_AUTO_NEG_ENABLE 0x1000
281 #define PHY_POWER_DOWN 0x0800
282 #define PHY_MII_DISABLE 0x0400
283 #define PHY_AUTO_NEG_RESTART 0x0200
284 #define PHY_FULL_DUPLEX 0x0100
285 #define PHY_COLLISION_TEST 0x0080
286 #define PHY_HP_MDIX 0x0020
287 #define PHY_FORCE_MDIX 0x0010
288 #define PHY_AUTO_MDIX_DISABLE 0x0008
289 #define PHY_REMOTE_FAULT_DISABLE 0x0004
290 #define PHY_TRANSMIT_DISABLE 0x0002
291 #define PHY_LED_DISABLE 0x0001
293 #define KS884X_PHY_STATUS_OFFSET 0x02
298 #define PHY_100BT4_CAPABLE 0x8000
299 #define PHY_100BTX_FD_CAPABLE 0x4000
300 #define PHY_100BTX_CAPABLE 0x2000
301 #define PHY_10BT_FD_CAPABLE 0x1000
302 #define PHY_10BT_CAPABLE 0x0800
303 #define PHY_MII_SUPPRESS_CAPABLE 0x0040
304 #define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
305 #define PHY_REMOTE_FAULT 0x0010
306 #define PHY_AUTO_NEG_CAPABLE 0x0008
307 #define PHY_LINK_STATUS 0x0004
308 #define PHY_JABBER_DETECT 0x0002
309 #define PHY_EXTENDED_CAPABILITY 0x0001
311 #define KS884X_PHY_ID_1_OFFSET 0x04
312 #define KS884X_PHY_ID_2_OFFSET 0x06
318 #define KS884X_PHY_AUTO_NEG_OFFSET 0x08
323 #define PHY_AUTO_NEG_NEXT_PAGE 0x8000
324 #define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
326 #define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
327 #define PHY_AUTO_NEG_SYM_PAUSE 0x0400
328 #define PHY_AUTO_NEG_100BT4 0x0200
329 #define PHY_AUTO_NEG_100BTX_FD 0x0100
330 #define PHY_AUTO_NEG_100BTX 0x0080
331 #define PHY_AUTO_NEG_10BT_FD 0x0040
332 #define PHY_AUTO_NEG_10BT 0x0020
333 #define PHY_AUTO_NEG_SELECTOR 0x001F
334 #define PHY_AUTO_NEG_802_3 0x0001
338 #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
343 #define PHY_REMOTE_NEXT_PAGE 0x8000
344 #define PHY_REMOTE_ACKNOWLEDGE 0x4000
345 #define PHY_REMOTE_REMOTE_FAULT 0x2000
346 #define PHY_REMOTE_SYM_PAUSE 0x0400
347 #define PHY_REMOTE_100BTX_FD 0x0100
348 #define PHY_REMOTE_100BTX 0x0080
349 #define PHY_REMOTE_10BT_FD 0x0040
350 #define PHY_REMOTE_10BT 0x0020
353 #define KS884X_P1VCT_P 0x04F0
354 #define KS884X_P1PHYCTRL_P 0x04F2
357 #define KS884X_P2VCT_P 0x04F4
358 #define KS884X_P2PHYCTRL_P 0x04F6
363 #define KS884X_PHY_LINK_MD_OFFSET 0x00
365 #define PHY_START_CABLE_DIAG 0x8000
366 #define PHY_CABLE_DIAG_RESULT 0x6000
367 #define PHY_CABLE_STAT_NORMAL 0x0000
368 #define PHY_CABLE_STAT_OPEN 0x2000
369 #define PHY_CABLE_STAT_SHORT 0x4000
370 #define PHY_CABLE_STAT_FAILED 0x6000
371 #define PHY_CABLE_10M_SHORT 0x1000
372 #define PHY_CABLE_FAULT_COUNTER 0x01FF
374 #define KS884X_PHY_PHY_CTRL_OFFSET 0x02
376 #define PHY_STAT_REVERSED_POLARITY 0x0020
377 #define PHY_STAT_MDIX 0x0010
378 #define PHY_FORCE_LINK 0x0008
379 #define PHY_POWER_SAVING_DISABLE 0x0004
380 #define PHY_REMOTE_LOOPBACK 0x0002
383 #define KS884X_SIDER_P 0x0400
387 #define REG_FAMILY_ID 0x88
389 #define REG_CHIP_ID_41 0x8810
390 #define REG_CHIP_ID_42 0x8800
392 #define KS884X_CHIP_ID_MASK_41 0xFF10
393 #define KS884X_CHIP_ID_MASK 0xFFF0
395 #define KS884X_REVISION_MASK 0x000E
397 #define KS8842_START 0x0001
399 #define CHIP_IP_41_M 0x8810
400 #define CHIP_IP_42_M 0x8800
401 #define CHIP_IP_61_M 0x8890
402 #define CHIP_IP_62_M 0x8880
404 #define CHIP_IP_41_P 0x8850
405 #define CHIP_IP_42_P 0x8840
406 #define CHIP_IP_61_P 0x88D0
407 #define CHIP_IP_62_P 0x88C0
410 #define KS8842_SGCR1_P 0x0402
413 #define SWITCH_PASS_ALL 0x8000
414 #define SWITCH_TX_FLOW_CTRL 0x2000
415 #define SWITCH_RX_FLOW_CTRL 0x1000
416 #define SWITCH_CHECK_LENGTH 0x0800
417 #define SWITCH_AGING_ENABLE 0x0400
418 #define SWITCH_FAST_AGING 0x0200
419 #define SWITCH_AGGR_BACKOFF 0x0100
420 #define SWITCH_PASS_PAUSE 0x0008
421 #define SWITCH_LINK_AUTO_AGING 0x0001
424 #define KS8842_SGCR2_P 0x0404
427 #define SWITCH_VLAN_ENABLE 0x8000
428 #define SWITCH_IGMP_SNOOP 0x4000
429 #define IPV6_MLD_SNOOP_ENABLE 0x2000
430 #define IPV6_MLD_SNOOP_OPTION 0x1000
431 #define PRIORITY_SCHEME_SELECT 0x0800
432 #define SWITCH_MIRROR_RX_TX 0x0100
433 #define UNICAST_VLAN_BOUNDARY 0x0080
434 #define MULTICAST_STORM_DISABLE 0x0040
435 #define SWITCH_BACK_PRESSURE 0x0020
436 #define FAIR_FLOW_CTRL 0x0010
437 #define NO_EXC_COLLISION_DROP 0x0008
438 #define SWITCH_HUGE_PACKET 0x0004
439 #define SWITCH_LEGAL_PACKET 0x0002
440 #define SWITCH_BUF_RESERVE 0x0001
443 #define KS8842_SGCR3_P 0x0406
446 #define BROADCAST_STORM_RATE_LO 0xFF00
447 #define SWITCH_REPEATER 0x0080
448 #define SWITCH_HALF_DUPLEX 0x0040
449 #define SWITCH_FLOW_CTRL 0x0020
450 #define SWITCH_10_MBIT 0x0010
451 #define SWITCH_REPLACE_NULL_VID 0x0008
452 #define BROADCAST_STORM_RATE_HI 0x0007
454 #define BROADCAST_STORM_RATE 0x07FF
457 #define KS8842_SGCR4_P 0x0408
460 #define KS8842_SGCR5_P 0x040A
463 #define LED_MODE 0x8200
464 #define LED_SPEED_DUPLEX_ACT 0x0000
465 #define LED_SPEED_DUPLEX_LINK_ACT 0x8000
466 #define LED_DUPLEX_10_100 0x0200
469 #define KS8842_SGCR6_P 0x0410
476 #define KS8842_SGCR7_P 0x0412
479 #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
480 #define SWITCH_UNK_DEF_PORT_3 0x0004
481 #define SWITCH_UNK_DEF_PORT_2 0x0002
482 #define SWITCH_UNK_DEF_PORT_1 0x0001
485 #define KS8842_MACAR1_P 0x0470
486 #define KS8842_MACAR2_P 0x0472
487 #define KS8842_MACAR3_P 0x0474
496 #define KS8842_TOSR1_P 0x0480
497 #define KS8842_TOSR2_P 0x0482
498 #define KS8842_TOSR3_P 0x0484
499 #define KS8842_TOSR4_P 0x0486
500 #define KS8842_TOSR5_P 0x0488
501 #define KS8842_TOSR6_P 0x048A
502 #define KS8842_TOSR7_P 0x0490
503 #define KS8842_TOSR8_P 0x0492
515 #define KS8842_P1CR1_P 0x0500
516 #define KS8842_P1CR2_P 0x0502
517 #define KS8842_P1VIDR_P 0x0504
518 #define KS8842_P1CR3_P 0x0506
519 #define KS8842_P1IRCR_P 0x0508
520 #define KS8842_P1ERCR_P 0x050A
521 #define KS884X_P1SCSLMD_P 0x0510
522 #define KS884X_P1CR4_P 0x0512
523 #define KS884X_P1SR_P 0x0514
526 #define KS8842_P2CR1_P 0x0520
527 #define KS8842_P2CR2_P 0x0522
528 #define KS8842_P2VIDR_P 0x0524
529 #define KS8842_P2CR3_P 0x0526
530 #define KS8842_P2IRCR_P 0x0528
531 #define KS8842_P2ERCR_P 0x052A
532 #define KS884X_P2SCSLMD_P 0x0530
533 #define KS884X_P2CR4_P 0x0532
534 #define KS884X_P2SR_P 0x0534
537 #define KS8842_P3CR1_P 0x0540
538 #define KS8842_P3CR2_P 0x0542
539 #define KS8842_P3VIDR_P 0x0544
540 #define KS8842_P3CR3_P 0x0546
541 #define KS8842_P3IRCR_P 0x0548
542 #define KS8842_P3ERCR_P 0x054A
552 #define KS8842_PORT_CTRL_1_OFFSET 0x00
554 #define PORT_BROADCAST_STORM 0x0080
555 #define PORT_DIFFSERV_ENABLE 0x0040
556 #define PORT_802_1P_ENABLE 0x0020
557 #define PORT_BASED_PRIORITY_MASK 0x0018
558 #define PORT_BASED_PRIORITY_BASE 0x0003
560 #define PORT_BASED_PRIORITY_0 0x0000
561 #define PORT_BASED_PRIORITY_1 0x0008
562 #define PORT_BASED_PRIORITY_2 0x0010
563 #define PORT_BASED_PRIORITY_3 0x0018
564 #define PORT_INSERT_TAG 0x0004
565 #define PORT_REMOVE_TAG 0x0002
566 #define PORT_PRIO_QUEUE_ENABLE 0x0001
568 #define KS8842_PORT_CTRL_2_OFFSET 0x02
570 #define PORT_INGRESS_VLAN_FILTER 0x4000
571 #define PORT_DISCARD_NON_VID 0x2000
572 #define PORT_FORCE_FLOW_CTRL 0x1000
573 #define PORT_BACK_PRESSURE 0x0800
574 #define PORT_TX_ENABLE 0x0400
575 #define PORT_RX_ENABLE 0x0200
576 #define PORT_LEARN_DISABLE 0x0100
577 #define PORT_MIRROR_SNIFFER 0x0080
578 #define PORT_MIRROR_RX 0x0040
579 #define PORT_MIRROR_TX 0x0020
580 #define PORT_USER_PRIORITY_CEILING 0x0008
581 #define PORT_VLAN_MEMBERSHIP 0x0007
583 #define KS8842_PORT_CTRL_VID_OFFSET 0x04
585 #define PORT_DEFAULT_VID 0x0001
587 #define KS8842_PORT_CTRL_3_OFFSET 0x06
589 #define PORT_INGRESS_LIMIT_MODE 0x000C
590 #define PORT_INGRESS_ALL 0x0000
591 #define PORT_INGRESS_UNICAST 0x0004
592 #define PORT_INGRESS_MULTICAST 0x0008
593 #define PORT_INGRESS_BROADCAST 0x000C
594 #define PORT_COUNT_IFG 0x0002
595 #define PORT_COUNT_PREAMBLE 0x0001
597 #define KS8842_PORT_IN_RATE_OFFSET 0x08
598 #define KS8842_PORT_OUT_RATE_OFFSET 0x0A
600 #define PORT_PRIORITY_RATE 0x0F
603 #define KS884X_PORT_LINK_MD 0x10
605 #define PORT_CABLE_10M_SHORT 0x8000
606 #define PORT_CABLE_DIAG_RESULT 0x6000
607 #define PORT_CABLE_STAT_NORMAL 0x0000
608 #define PORT_CABLE_STAT_OPEN 0x2000
609 #define PORT_CABLE_STAT_SHORT 0x4000
610 #define PORT_CABLE_STAT_FAILED 0x6000
611 #define PORT_START_CABLE_DIAG 0x1000
612 #define PORT_FORCE_LINK 0x0800
613 #define PORT_POWER_SAVING_DISABLE 0x0400
614 #define PORT_PHY_REMOTE_LOOPBACK 0x0200
615 #define PORT_CABLE_FAULT_COUNTER 0x01FF
617 #define KS884X_PORT_CTRL_4_OFFSET 0x12
619 #define PORT_LED_OFF 0x8000
620 #define PORT_TX_DISABLE 0x4000
621 #define PORT_AUTO_NEG_RESTART 0x2000
622 #define PORT_REMOTE_FAULT_DISABLE 0x1000
623 #define PORT_POWER_DOWN 0x0800
624 #define PORT_AUTO_MDIX_DISABLE 0x0400
625 #define PORT_FORCE_MDIX 0x0200
626 #define PORT_LOOPBACK 0x0100
627 #define PORT_AUTO_NEG_ENABLE 0x0080
628 #define PORT_FORCE_100_MBIT 0x0040
629 #define PORT_FORCE_FULL_DUPLEX 0x0020
630 #define PORT_AUTO_NEG_SYM_PAUSE 0x0010
631 #define PORT_AUTO_NEG_100BTX_FD 0x0008
632 #define PORT_AUTO_NEG_100BTX 0x0004
633 #define PORT_AUTO_NEG_10BT_FD 0x0002
634 #define PORT_AUTO_NEG_10BT 0x0001
636 #define KS884X_PORT_STATUS_OFFSET 0x14
638 #define PORT_HP_MDIX 0x8000
639 #define PORT_REVERSED_POLARITY 0x2000
640 #define PORT_RX_FLOW_CTRL 0x0800
641 #define PORT_TX_FLOW_CTRL 0x1000
642 #define PORT_STATUS_SPEED_100MBIT 0x0400
643 #define PORT_STATUS_FULL_DUPLEX 0x0200
644 #define PORT_REMOTE_FAULT 0x0100
645 #define PORT_MDIX_STATUS 0x0080
646 #define PORT_AUTO_NEG_COMPLETE 0x0040
647 #define PORT_STATUS_LINK_GOOD 0x0020
648 #define PORT_REMOTE_SYM_PAUSE 0x0010
649 #define PORT_REMOTE_100BTX_FD 0x0008
650 #define PORT_REMOTE_100BTX 0x0004
651 #define PORT_REMOTE_10BT_FD 0x0002
652 #define PORT_REMOTE_10BT 0x0001
663 #define STATIC_MAC_TABLE_ADDR 0x0000FFFF
664 #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
665 #define STATIC_MAC_TABLE_VALID 0x00080000
666 #define STATIC_MAC_TABLE_OVERRIDE 0x00100000
667 #define STATIC_MAC_TABLE_USE_FID 0x00200000
668 #define STATIC_MAC_TABLE_FID 0x03C00000
680 #define VLAN_TABLE_VID 0x00000FFF
681 #define VLAN_TABLE_FID 0x0000F000
682 #define VLAN_TABLE_MEMBERSHIP 0x00070000
683 #define VLAN_TABLE_VALID 0x00080000
699 #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
700 #define DYNAMIC_MAC_TABLE_FID 0x000F0000
701 #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
702 #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
703 #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
705 #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
706 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
707 #define DYNAMIC_MAC_TABLE_RESERVED 0x78
708 #define DYNAMIC_MAC_TABLE_NOT_READY 0x80
722 #define MIB_COUNTER_VALUE 0x3FFFFFFF
723 #define MIB_COUNTER_VALID 0x40000000
724 #define MIB_COUNTER_OVERFLOW 0x80000000
726 #define MIB_PACKET_DROPPED 0x0000FFFF
728 #define KS_MIB_PACKET_DROPPED_TX_0 0x100
729 #define KS_MIB_PACKET_DROPPED_TX_1 0x101
730 #define KS_MIB_PACKET_DROPPED_TX 0x102
731 #define KS_MIB_PACKET_DROPPED_RX_0 0x103
732 #define KS_MIB_PACKET_DROPPED_RX_1 0x104
733 #define KS_MIB_PACKET_DROPPED_RX 0x105
785 #define KS_DESC_RX_FRAME_LEN 0x000007FF
786 #define KS_DESC_RX_FRAME_TYPE 0x00008000
787 #define KS_DESC_RX_ERROR_CRC 0x00010000
788 #define KS_DESC_RX_ERROR_RUNT 0x00020000
789 #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
790 #define KS_DESC_RX_ERROR_PHY 0x00080000
791 #define KS884X_DESC_RX_PORT_MASK 0x00300000
792 #define KS_DESC_RX_MULTICAST 0x01000000
793 #define KS_DESC_RX_ERROR 0x02000000
794 #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
795 #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
796 #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
797 #define KS_DESC_RX_LAST 0x20000000
798 #define KS_DESC_RX_FIRST 0x40000000
805 #define KS_DESC_HW_OWNED 0x80000000
807 #define KS_DESC_BUF_SIZE 0x000007FF
808 #define KS884X_DESC_TX_PORT_MASK 0x00300000
809 #define KS_DESC_END_OF_RING 0x02000000
810 #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
811 #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
812 #define KS_DESC_TX_CSUM_GEN_IP 0x10000000
813 #define KS_DESC_TX_LAST 0x20000000
814 #define KS_DESC_TX_FIRST 0x40000000
815 #define KS_DESC_TX_INTERRUPT 0x80000000
1017 TABLE_STATIC_MAC = 0,
1069 #define MAIN_PORT 0
1073 #define PORT_COUNTER_NUM 0x20
1076 #define MIB_COUNTER_RX_LO_PRIORITY 0x00
1077 #define MIB_COUNTER_RX_HI_PRIORITY 0x01
1078 #define MIB_COUNTER_RX_UNDERSIZE 0x02
1079 #define MIB_COUNTER_RX_FRAGMENT 0x03
1080 #define MIB_COUNTER_RX_OVERSIZE 0x04
1081 #define MIB_COUNTER_RX_JABBER 0x05
1082 #define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1083 #define MIB_COUNTER_RX_CRC_ERR 0x07
1084 #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1085 #define MIB_COUNTER_RX_CTRL_8808 0x09
1086 #define MIB_COUNTER_RX_PAUSE 0x0A
1087 #define MIB_COUNTER_RX_BROADCAST 0x0B
1088 #define MIB_COUNTER_RX_MULTICAST 0x0C
1089 #define MIB_COUNTER_RX_UNICAST 0x0D
1090 #define MIB_COUNTER_RX_OCTET_64 0x0E
1091 #define MIB_COUNTER_RX_OCTET_65_127 0x0F
1092 #define MIB_COUNTER_RX_OCTET_128_255 0x10
1093 #define MIB_COUNTER_RX_OCTET_256_511 0x11
1094 #define MIB_COUNTER_RX_OCTET_512_1023 0x12
1095 #define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1096 #define MIB_COUNTER_TX_LO_PRIORITY 0x14
1097 #define MIB_COUNTER_TX_HI_PRIORITY 0x15
1098 #define MIB_COUNTER_TX_LATE_COLLISION 0x16
1099 #define MIB_COUNTER_TX_PAUSE 0x17
1100 #define MIB_COUNTER_TX_BROADCAST 0x18
1101 #define MIB_COUNTER_TX_MULTICAST 0x19
1102 #define MIB_COUNTER_TX_UNICAST 0x1A
1103 #define MIB_COUNTER_TX_DEFERRED 0x1B
1104 #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1105 #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1106 #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1107 #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1109 #define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1110 #define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1117 * @mib_start: The starting counter index. Some ports do not start at 0.
1213 #define LINK_INT_WORKING (1 << 0)
1220 #define PAUSE_FLOW_CTRL (1 << 0)
1318 * duplex, and 0 for auto, which normally results in full
1321 * 0 for auto, which normally results in 100 Mbit.
1322 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1480 #define DRV_VERSION "1.0.0"
1486 static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1500 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE); in hw_dis_intr()
1512 hw->intr_blocked = 0; in hw_ena_intr()
1579 uint interrupt = 0; in hw_block_intr()
1594 status.rx.hw_owned = 0; in reset_desc()
1649 #define TABLE_READ 0x10
1655 } while (0)
1736 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1]; in sw_w_sta_mac_table()
1762 * Return 0 if the entry is valid; otherwise -1.
1775 return 0; in sw_r_vlan_table()
1805 for (timeout = 100; timeout > 0; timeout--) { in port_r_mib_cnt()
1890 mib->cnt_ptr = 0; in port_r_cnt()
1891 return 0; in port_r_cnt()
1906 mib->cnt_ptr = 0; in port_init_cnt()
1916 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); in port_init_cnt()
1917 mib->cnt_ptr = 0; in port_init_cnt()
1934 * Return 0 if the bits are not set.
1983 * Return 0 if the port is not set.
2083 * Return 0 if the bits are not set.
2151 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8); in sw_cfg_broad_storm()
2184 port_cfg_broad_storm(hw, port, 0); in sw_dis_broad_storm()
2212 for (port = 0; port < TOTAL_PORT_NUM; port++) in sw_init_broad_storm()
2248 writel(0, hw->io + addr); in sw_dis_prio_rate()
2263 for (port = 0; port < TOTAL_PORT_NUM; port++) { in sw_init_prio_rate()
2264 for (prio = 0; prio < PRIO_QUEUES; prio++) { in sw_init_prio_rate()
2266 sw->port_cfg[port].tx_rate[prio] = 0; in sw_init_prio_rate()
2322 sw_cfg_fast_aging(hw, 0); in sw_flush_dyn_mac_table()
2405 for (port = 0; port < TOTAL_PORT_NUM; port++) { in sw_init_mirror()
2406 port_cfg_mirror_sniffer(hw, port, 0); in sw_init_mirror()
2407 port_cfg_mirror_rx(hw, port, 0); in sw_init_mirror()
2408 port_cfg_mirror_tx(hw, port, 0); in sw_init_mirror()
2410 sw_cfg_mirror_rx_tx(hw, 0); in sw_init_mirror()
2427 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set); in sw_cfg_unk_def_port()
2432 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0); in sw_chk_unk_def_port()
2494 port_cfg_diffserv(hw, port, 0); in sw_dis_diffserv()
2506 port_cfg_802_1p(hw, port, 0); in sw_dis_802_1p()
2569 port_cfg_prio(hw, port, 0); in sw_dis_multi_queue()
2588 sw->p_802_1p[0] = 0; in sw_init_prio()
2589 sw->p_802_1p[1] = 0; in sw_init_prio()
2599 * queue 0. in sw_init_prio()
2601 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++) in sw_init_prio()
2602 sw->diffserv[tos] = 0; in sw_init_prio()
2605 for (port = 0; port < TOTAL_PORT_NUM; port++) { in sw_init_prio()
2609 sw_cfg_replace_vid(hw, port, 0); in sw_init_prio()
2611 sw->port_cfg[port].port_prio = 0; in sw_init_prio()
2614 sw_cfg_replace_null_vid(hw, 0); in sw_init_prio()
2647 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) { in sw_init_vlan()
2654 for (port = 0; port < TOTAL_PORT_NUM; port++) { in sw_init_vlan()
2695 for (i = 0; i < 6; i += 2) { in sw_get_addr()
2712 for (i = 0; i < 6; i += 2) { in sw_set_addr()
2756 STP_STATE_DISABLED = 0,
2817 #define STP_ENTRY 0
2833 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) { in sw_clr_sta_mac_table()
2837 entry->override, 0, in sw_clr_sta_mac_table()
2853 entry->mac_addr[0] = 0x01; in sw_init_stp()
2854 entry->mac_addr[1] = 0x80; in sw_init_stp()
2855 entry->mac_addr[2] = 0xC2; in sw_init_stp()
2856 entry->mac_addr[3] = 0x00; in sw_init_stp()
2857 entry->mac_addr[4] = 0x00; in sw_init_stp()
2858 entry->mac_addr[5] = 0x00; in sw_init_stp()
2881 entry->valid = 0; in sw_block_addr()
2996 #define AT93C_CODE 0
2997 #define AT93C_WR_OFF 0x00
2998 #define AT93C_WR_ALL 0x10
2999 #define AT93C_ER_ALL 0x20
3000 #define AT93C_WR_ON 0x30
3045 u16 temp = 0; in spi_r()
3047 for (i = 15; i >= 0; i--) { in spi_r()
3051 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0; in spi_r()
3063 for (i = 15; i >= 0; i--) { in spi_w()
3064 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : in spi_w()
3079 for (i = 1; i >= 0; i--) { in spi_reg()
3080 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : in spi_reg()
3086 for (i = 5; i >= 0; i--) { in spi_reg()
3087 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : in spi_reg()
3093 #define EEPROM_DATA_RESERVED 0
3238 rx = tx = 0; in determine_flow_ctrl()
3291 int change = 0; in port_get_link_speed()
3295 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { in port_get_link_speed()
3377 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { in port_set_link_speed()
3381 cfg = 0; in port_set_link_speed()
3427 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { in port_force_link_speed()
3451 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) in port_set_power_saving()
3466 * Return 1 if PMEN pin is asserted; otherwise, 0.
3475 return 0; in hw_chk_wol_pme_status()
3565 u8 val = 0; in hw_set_wol_frame()
3572 i *= 0x10; in hw_set_wol_frame()
3573 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i); in hw_set_wol_frame()
3574 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i); in hw_set_wol_frame()
3576 bits = len = from = to = 0; in hw_set_wol_frame()
3615 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 }; in hw_add_wol_arp()
3617 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, in hw_add_wol_arp()
3618 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in hw_add_wol_arp()
3619 0x08, 0x06, in hw_add_wol_arp()
3620 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, in hw_add_wol_arp()
3621 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in hw_add_wol_arp()
3622 0x00, 0x00, 0x00, 0x00, in hw_add_wol_arp()
3623 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in hw_add_wol_arp()
3624 0x00, 0x00, 0x00, 0x00 }; in hw_add_wol_arp()
3638 static const u8 mask[] = { 0x3F }; in hw_add_wol_bcast()
3639 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; in hw_add_wol_bcast()
3656 static const u8 mask[] = { 0x3F }; in hw_add_wol_mcast()
3657 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 }; in hw_add_wol_mcast()
3674 static const u8 mask[] = { 0x3F }; in hw_add_wol_ucast()
3676 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr); in hw_add_wol_ucast()
3706 * Return number of ports or 0 if not right.
3710 int rc = 0; in hw_init()
3727 return 0; in hw_init()
3751 /* Write 0 to clear device reset. */ in hw_reset()
3752 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET); in hw_reset()
3809 shift = 0; in ksz_check_desc_num()
3836 for (i = 0; i < desc_info->alloc; i++) { in hw_init_desc()
3847 desc_info->last = desc_info->next = 0; in hw_init_desc()
3871 info->last = info->next = 0; in hw_reset_pkts()
3897 if (0 == hw->rx_stop) in hw_start_rx()
3909 hw->rx_stop = 0; in hw_stop_rx()
3946 hw->enabled = 0; in hw_disable()
3970 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3976 return 0; in hw_alloc_pkt()
4011 hw->tx_int_cnt = 0; in hw_send_pkt()
4012 hw->tx_size = 0; in hw_send_pkt()
4020 writel(0, hw->io + KS_DMA_TX_START); in hw_send_pkt()
4028 return 0 == *addr1 && 0 == *addr2; in empty_addr()
4042 for (i = 0; i < ETH_ALEN; i++) in hw_set_addr()
4059 for (i = 0; i < ETH_ALEN; i++) in hw_read_addr()
4081 mac_addr_hi = 0; in hw_ena_add_addr()
4082 for (i = 0; i < 2; i++) { in hw_ena_add_addr()
4087 mac_addr_lo = 0; in hw_ena_add_addr()
4102 for (i = 0; i < ADDITIONAL_ENTRIES; i++) { in hw_set_add_addr()
4104 writel(0, hw->io + ADD_ADDR_INCR * i + in hw_set_add_addr()
4117 return 0; in hw_add_addr()
4118 for (i = 0; i < hw->addr_list_size; i++) { in hw_add_addr()
4120 return 0; in hw_add_addr()
4127 return 0; in hw_add_addr()
4136 for (i = 0; i < hw->addr_list_size; i++) { in hw_del_addr()
4139 writel(0, hw->io + ADD_ADDR_INCR * i + in hw_del_addr()
4141 return 0; in hw_del_addr()
4157 for (i = 0; i < HW_MULTICAST_SIZE; i++) { in hw_clr_multicast()
4158 hw->multi_bits[i] = 0; in hw_clr_multicast()
4160 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i); in hw_clr_multicast()
4178 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE); in hw_set_grp_addr()
4180 for (i = 0; i < hw->multi_list_size; i++) { in hw_set_grp_addr()
4181 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f; in hw_set_grp_addr()
4187 for (i = 0; i < HW_MULTICAST_SIZE; i++) in hw_set_grp_addr()
4245 for (port = 0; port < SWITCH_PORT_NUM; port++) { in sw_enable()
4281 for (port = 0; port < SWITCH_PORT_NUM; port++) in sw_setup()
4309 info->cnt = 0; in ksz_start_timer()
4326 info->max = 0; in ksz_stop_timer()
4334 info->max = 0; in ksz_init_timer()
4336 timer_setup(&info->timer, function, 0); in ksz_init_timer()
4342 if (info->max > 0) { in ksz_update_timer()
4347 info->max = 0; in ksz_update_timer()
4348 } else if (info->max < 0) { in ksz_update_timer()
4362 * Return 0 if successful.
4371 return 0; in ksz_alloc_soft_desc()
4381 * Return 0 if successful.
4399 adapter->desc_pool.alloc_size = 0; in ksz_alloc_desc()
4406 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0); in ksz_alloc_desc()
4419 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0)) in ksz_alloc_desc()
4424 return 0; in ksz_alloc_desc()
4442 dma_buf->dma = 0; in free_dma_buf()
4459 for (i = 0; i < hw->rx_desc_info.alloc; i++) { in ksz_init_rx_buffers()
4488 * Return 0 if successful.
4499 hw->tx_int_cnt = 0; in ksz_alloc_mem()
4509 hw->tx_int_cnt = 0; in ksz_alloc_mem()
4528 return 0; in ksz_alloc_mem()
4545 hw->rx_desc_info.ring_phys = 0; in ksz_free_desc()
4546 hw->tx_desc_info.ring_phys = 0; in ksz_free_desc()
4556 adapter->desc_pool.alloc_size = 0; in ksz_free_desc()
4580 for (i = 0; i < desc_info->alloc; i++) { in ksz_free_buffers()
4614 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM); in get_mib_counters()
4615 for (i = 0, port = first; i < cnt; i++, port++) { in get_mib_counters()
4667 frag = 0; in send_packet()
4798 for (port = 0; port < hw->dev_count; port++) { in tx_done()
4824 * Return 0 if successful; otherwise an error code indicating failure.
4833 int rc = 0; in netdev_tx()
4840 memset(&skb->data[skb->len], 0, 50 - skb->len); in netdev_tx()
4847 memset(&skb->data[org_skb->len], 0, in netdev_tx()
4922 transmit_cleanup(hw_priv, 0); in netdev_tx_timeout()
4940 for (port = 0; port < SWITCH_PORT_NUM; port++) { in netdev_tx_timeout()
5011 } while (0); in rx_proc()
5025 return 0; in rx_proc()
5033 struct net_device *dev = hw->port_info[0].pdev; in dev_rcv_packets()
5037 int received = 0; in dev_rcv_packets()
5069 struct net_device *dev = hw->port_info[0].pdev; in port_rcv_packets()
5073 int received = 0; in port_rcv_packets()
5114 struct net_device *dev = hw->port_info[0].pdev; in dev_rcv_special()
5118 int received = 0; in dev_rcv_special()
5208 if (0 == hw->rx_stop) in handle_rx_stop()
5215 hw->rx_stop = 0; in handle_rx_stop()
5233 uint int_enable = 0; in netdev_intr()
5290 } while (0); in netdev_intr()
5327 for (port = 0; port < SWITCH_PORT_NUM; port++) { in bridge_change()
5344 * Return 0 if successful; otherwise an error code indicating failure.
5371 if (port->first_port > 0) in netdev_close()
5397 transmit_cleanup(hw_priv, 0); in netdev_close()
5406 return 0; in netdev_close()
5438 int rc = 0; in prepare_hardware()
5448 hw->promiscuous = 0; in prepare_hardware()
5449 hw->all_multi = 0; in prepare_hardware()
5450 hw->multi_list_size = 0; in prepare_hardware()
5459 return 0; in prepare_hardware()
5481 * Return 0 if successful; otherwise an error code indicating failure.
5491 int rc = 0; in netdev_open()
5493 priv->multicast = 0; in netdev_open()
5494 priv->promiscuous = 0; in netdev_open()
5497 memset(&dev->stats, 0, sizeof(struct net_device_stats)); in netdev_open()
5498 memset((void *) port->counter, 0, in netdev_open()
5505 for (i = 0; i < hw->mib_port_cnt; i++) { in netdev_open()
5518 hw_cfg_wol_pme(hw, 0); in netdev_open()
5524 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) { in netdev_open()
5529 hw->port_info[p].partner = 0xFF; in netdev_open()
5536 if (port->first_port > 0) in netdev_open()
5566 return 0; in netdev_open()
5601 dev->stats.multicast = 0; in netdev_query_statistics()
5602 dev->stats.collisions = 0; in netdev_query_statistics()
5603 dev->stats.rx_length_errors = 0; in netdev_query_statistics()
5604 dev->stats.rx_crc_errors = 0; in netdev_query_statistics()
5605 dev->stats.rx_frame_errors = 0; in netdev_query_statistics()
5606 dev->stats.tx_window_errors = 0; in netdev_query_statistics()
5608 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { in netdev_query_statistics()
5642 * Return 0 to indicate success.
5652 if (priv->port.first_port > 0) in netdev_set_mac_address()
5663 if (priv->port.first_port > 0) in netdev_set_mac_address()
5669 return 0; in netdev_set_mac_address()
5751 int i = 0; in netdev_set_rx_mode()
5775 hw->multi_list_size = 0; in netdev_set_rx_mode()
5793 return 0; in netdev_change_mtu()
5807 return 0; in netdev_change_mtu()
5818 * Return 0 to indicate success.
5826 int result = 0; in netdev_ioctl()
5909 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++) in mdio_write()
5917 #define EEPROM_SIZE 0x40
5919 static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5936 * Return 0 if successful; otherwise an error code.
5953 return 0; in netdev_get_link_ksettings()
5963 * Return 0 if successful; otherwise an error code.
5993 if (0 == cmd->base.duplex) in netdev_set_link_ksettings()
6005 port->duplex = 0; in netdev_set_link_ksettings()
6006 port->speed = 0; in netdev_set_link_ksettings()
6007 port->force_link = 0; in netdev_set_link_ksettings()
6013 port->force_link = 0; in netdev_set_link_ksettings()
6034 * Return 0 if successful; otherwise an error code.
6094 { 0, 0 }
6108 int regs_len = 0x10 * sizeof(u32); in netdev_get_regs_len()
6136 regs->version = 0; in netdev_get_regs()
6137 for (len = 0; len < 0x40; len += 4) { in netdev_get_regs()
6171 memset(&wol->sopass, 0, sizeof(wol->sopass)); in netdev_get_wol()
6181 * Return 0 if successful; otherwise an error code.
6201 return 0; in netdev_set_wol()
6246 #define EEPROM_MAGIC 0x10A18842
6256 * Return 0 if successful; otherwise an error code.
6273 return 0; in netdev_get_eeprom()
6284 * Return 0 if successful; otherwise an error code.
6304 for (i = 0; i < EEPROM_SIZE; i++) in netdev_set_eeprom()
6310 return 0; in netdev_set_eeprom()
6327 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1; in netdev_get_pauseparam()
6330 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0; in netdev_get_pauseparam()
6332 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0; in netdev_get_pauseparam()
6336 SWITCH_RX_FLOW_CTRL)) ? 1 : 0; in netdev_get_pauseparam()
6339 SWITCH_TX_FLOW_CTRL)) ? 1 : 0; in netdev_get_pauseparam()
6351 * Return 0 if successful; otherwise an error code.
6368 port->force_link = 0; in netdev_set_pauseparam()
6388 return 0; in netdev_set_pauseparam()
6519 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) { in netdev_get_ethtool_stats()
6540 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) { in netdev_get_ethtool_stats()
6541 if (0 == i) { in netdev_get_ethtool_stats()
6559 for (i = 0; i < n; i++) in netdev_get_ethtool_stats()
6570 * Return 0 if successful; otherwise an error code.
6592 return 0; in netdev_set_features()
6641 for (i = 0; i < hw->mib_port_cnt; i++) { in mib_read_work()
6650 hw_priv->counter[i].read = 0; in mib_read_work()
6653 if (0 == mib->cnt_ptr) { in mib_read_work()
6667 mib->link_down = 0; in mib_read_work()
6685 hw_priv->pme_wait = 0; in mib_monitor()
6767 * Return 0 if successful; otherwise an error code indicating failure.
6792 priv->mii_if.phy_id_mask = 0x1; in netdev_init()
6793 priv->mii_if.reg_num_mask = 0x7; in netdev_init()
6802 return 0; in netdev_init()
6845 i = j = num = got_num = 0; in get_mac_addr()
6852 if (digit >= 0) in get_mac_addr()
6873 num = got_num = 0; in get_mac_addr()
6883 #define KS884X_DMA_MASK (~0x0UL)
6891 for (i = 0; i < 3; i++) in read_other_addr()
6893 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) { in read_other_addr()
6894 sw->other_addr[5] = (u8) data[0]; in read_other_addr()
6895 sw->other_addr[4] = (u8)(data[0] >> 8); in read_other_addr()
6899 sw->other_addr[0] = (u8)(data[2] >> 8); in read_other_addr()
6904 #define PCI_VENDOR_ID_MICREL_KS 0x16c6
6936 reg_base = pci_resource_start(pdev, 0); in pcidev_init()
6937 reg_len = pci_resource_len(pdev, 0); in pcidev_init()
6938 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) in pcidev_init()
6969 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */ in pcidev_init()
6977 hw->addr_list_size = 0; in pcidev_init()
7006 for (i = 0; i < hw->mib_port_cnt; i++) in pcidev_init()
7007 hw->port_mib[i].mib_start = 0; in pcidev_init()
7022 for (i = 0; i < TOTAL_PORT_NUM; i++) in pcidev_init()
7025 if (macaddr[0] != ':') in pcidev_init()
7035 if (mac1addr[0] != ':') in pcidev_init()
7044 hw_priv->wol_enable = 0; in pcidev_init()
7053 for (i = 0; i < hw->dev_count; i++) { in pcidev_init()
7073 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) { in pcidev_init()
7106 return 0; in pcidev_init()
7109 for (i = 0; i < hw->dev_count; i++) { in pcidev_init()
7138 release_mem_region(pci_resource_start(pdev, 0), in pcidev_exit()
7139 pci_resource_len(pdev, 0)); in pcidev_exit()
7140 for (i = 0; i < hw_priv->hw.dev_count; i++) { in pcidev_exit()
7162 hw_cfg_wol_pme(hw, 0); in pcidev_resume()
7163 for (i = 0; i < hw->dev_count; i++) { in pcidev_resume()
7173 return 0; in pcidev_resume()
7186 for (i = 0; i < hw->dev_count; i++) { in pcidev_suspend()
7202 return 0; in pcidev_suspend()
7208 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7210 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7212 { 0 }
7233 module_param_named(message, msg_enable, int, 0);
7234 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7236 module_param(macaddr, charp, 0);
7237 module_param(mac1addr, charp, 0);
7238 module_param(fast_aging, int, 0);
7239 module_param(multi_dev, int, 0);
7240 module_param(stp, int, 0);