Lines Matching +full:0 +full:x10100
21 #define MTK_TX_DMA_BUF_LEN 0x3fff
27 #define MTK_DMA_DUMMY_DESC 0xffffffff
61 #define MTK_RST_GL 0x04
62 #define RST_GL_PSE BIT(0)
65 #define MTK_INT_STATUS2 0x08
70 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
73 #define MTK_FE_INT_GRP 0x20
76 #define MTK_CDMQ_IG_CTRL 0x1400
77 #define MTK_CDMQ_STAG_EN BIT(0)
80 #define MTK_CDMP_EG_CTRL 0x404
83 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
87 #define MTK_GDMA_TO_PDMA 0x0
88 #define MTK_GDMA_DROP_ALL 0x7777
91 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
94 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
97 #define MTK_PRX_BASE_PTR0 0x900
98 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
101 #define MTK_PRX_MAX_CNT0 0x904
102 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
105 #define MTK_PRX_CRX_IDX0 0x908
106 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
109 #define MTK_PDMA_LRO_CTRL_DW0 0x980
110 #define MTK_LRO_EN BIT(0)
113 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
114 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
116 #define MTK_PDMA_LRO_CTRL_DW1 0x984
117 #define MTK_PDMA_LRO_CTRL_DW2 0x988
118 #define MTK_PDMA_LRO_CTRL_DW3 0x98c
123 #define MTK_PDMA_GLO_CFG 0xa04
128 #define MTK_PDMA_RST_IDX 0xa08
133 #define MTK_PDMA_DELAY_INT 0xa0c
143 #define MTK_PDMA_INT_STATUS 0xa20
146 #define MTK_PDMA_INT_MASK 0xa28
149 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
152 #define MTK_PDMA_INT_GRP1 0xa50
153 #define MTK_PDMA_INT_GRP2 0xa54
156 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04
157 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
161 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
162 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
163 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
164 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
165 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
166 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
167 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
168 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
171 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
172 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
173 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
176 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
180 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
183 #define MTK_QRX_BASE_PTR0 0x1900
186 #define MTK_QRX_MAX_CNT0 0x1904
189 #define MTK_QRX_CRX_IDX0 0x1908
192 #define MTK_QRX_DRX_IDX0 0x190C
195 #define MTK_QDMA_GLO_CFG 0x1A04
204 #define MTK_TX_DMA_EN BIT(0)
208 #define MTK_QDMA_RST_IDX 0x1A08
211 #define MTK_QDMA_DELAY_INT 0x1A0C
214 #define MTK_QDMA_FC_THRES 0x1A10
217 #define FC_THRES_MIN 0x4444
220 #define MTK_QDMA_INT_STATUS 0x1A18
229 #define MTK_TX_DONE_INT0 BIT(0)
235 #define MTK_QDMA_INT_GRP1 0x1a20
236 #define MTK_QDMA_INT_GRP2 0x1a24
237 #define MTK_RLS_DONE_INT BIT(0)
240 #define MTK_QDMA_INT_MASK 0x1A1C
243 #define MTK_QDMA_HRED2 0x1A44
246 #define MTK_QTX_CTX_PTR 0x1B00
249 #define MTK_QTX_DTX_PTR 0x1B04
252 #define MTK_QTX_CRX_PTR 0x1B10
255 #define MTK_QTX_DRX_PTR 0x1B14
258 #define MTK_QDMA_FQ_HEAD 0x1B20
261 #define MTK_QDMA_FQ_TAIL 0x1B24
264 #define MTK_QDMA_FQ_CNT 0x1B28
267 #define MTK_QDMA_FQ_BLEN 0x1B2C
270 #define MTK_GDM1_TX_GBCNT 0x2400
271 #define MTK_STAT_OFFSET 0x40
274 #define TX_DMA_CHKSUM (0x7 << 29)
277 #define TX_DMA_FPORT_MASK 0x7
286 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
296 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
297 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
300 #define RX_DMA_VID(_x) ((_x) & 0xfff)
306 #define RX_DMA_FPORT_MASK 0x7
309 #define MTK_PHY_IAC 0x10004
318 #define MTK_MAC_MISC 0x1000c
319 #define MTK_MUX_TO_ESW BIT(0)
322 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
335 #define MAC_MCR_FORCE_LINK BIT(0)
339 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
348 #define MAC_MSR_LINK BIT(0)
351 #define TRGMII_RCK_CTRL 0x10300
352 #define DQSI0(x) ((x << 0) & GENMASK(6, 0))
363 #define TRGMII_TCK_CTRL 0x10340
370 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
371 #define TD_DM_DRVP(x) ((x) & 0xf)
372 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
375 #define INTF_MODE 0x10390
376 #define TRGMII_INTF_DIS BIT(0)
380 #define INTF_MODE_RGMII_10_100 0
383 #define GPIO_OD33_CTRL8 0x4c0
384 #define GPIO_BIAS_CTRL 0xed0
385 #define GPIO_DRV_SEL10 0xf00
388 #define ETHSYS_CHIPID0_3 0x0
389 #define ETHSYS_CHIPID4_7 0x4
395 #define ETHSYS_SYSCFG 0x10
399 #define ETHSYS_SYSCFG0 0x14
400 #define SYSCFG0_GE_MASK 0x3
410 #define ETHSYS_CLKCFG0 0x2c
417 #define ETHSYS_RSTCTRL 0x34
423 #define SGMSYS_PCS_CONTROL_1 0x0
434 #define SGMSYS_PCS_LINK_TIMER 0x18
435 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
438 #define SGMSYS_SGMII_MODE 0x20
439 #define SGMII_IF_MODE_BIT0 BIT(0)
441 #define SGMII_SPEED_10 0x0
453 #define SGMSYS_ANA_RG_CS3 0x2028
455 #define RG_PHY_SPEED_1_25G 0x0
459 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
463 #define INFRA_MISC2 0x70c
464 #define CO_QPHY_SEL BIT(0)
468 #define MT7628_PDMA_OFFSET 0x0800
469 #define MT7628_SDM_OFFSET 0x0c00
471 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
472 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
473 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
474 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
475 #define MT7628_PST_DTX_IDX0 BIT(0)
477 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
478 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
529 MTK_TX_FLAGS_SINGLE0 = 0x01,
530 MTK_TX_FLAGS_PAGE0 = 0x02,
535 MTK_TX_FLAGS_FPORT0 = 0x04,
536 MTK_TX_FLAGS_FPORT1 = 0x08,
576 #define MT7621_CLKS_BITMAP (0)
577 #define MT7628_CLKS_BITMAP (0)
640 MTK_RX_FLAGS_NORMAL = 0,
666 MTK_RGMII_BIT = 0,
741 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
744 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
748 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
757 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
806 #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
807 #define MTK_SGMII_PHYSPEED_1000 BIT(0)