Lines Matching +full:0 +full:x1032
57 #define SKGE_EEPROM_MAGIC 0x9933aabb
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
88 { 0 }
125 return 0x4000; in skge_get_regs_len()
140 memset(p, 0, regs->len); in skge_get_regs()
153 return 0; in wol_supported()
155 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in wol_supported()
156 return 0; in wol_supported()
200 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); in skge_wol_init()
217 ctrl = 0; in skge_wol_init()
256 return 0; in skge_set_wol()
318 return 0; in skge_get_link_ksettings()
327 int err = 0; in skge_set_link_ksettings()
371 if ((setting & supported) == 0) in skge_set_link_ksettings()
390 return 0; in skge_set_link_ksettings()
470 dev->stats.tx_bytes = data[0]; in skge_get_stats()
487 for (i = 0; i < ARRAY_SIZE(skge_stats); i++) in skge_get_strings()
510 int err = 0; in skge_set_ring_param()
512 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || in skge_set_ring_param()
549 return 0; in skge_nway_reset()
570 int err = 0; in skge_set_pauseparam()
596 return 0; in skge_set_pauseparam()
624 ecmd->rx_coalesce_usecs = 0; in skge_get_coalesce()
625 ecmd->tx_coalesce_usecs = 0; in skge_get_coalesce()
637 return 0; in skge_get_coalesce()
650 if (ecmd->rx_coalesce_usecs == 0) in skge_set_coalesce()
660 if (ecmd->tx_coalesce_usecs == 0) in skge_set_coalesce()
671 if (msk == 0) in skge_set_coalesce()
677 return 0; in skge_set_coalesce()
693 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); in skge_led()
697 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); in skge_led()
727 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
745 PHY_M_LED_MO_100(MO_LED_ON) : 0)); in skge_led()
748 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
783 return 0; in skge_set_phys_id()
834 while (length > 0) { in skge_get_eeprom()
843 return 0; in skge_get_eeprom()
861 while (length > 0) { in skge_set_eeprom()
875 return 0; in skge_set_eeprom()
920 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { in skge_ring_alloc()
932 return 0; in skge_ring_alloc()
953 rd->csum1 = 0; in skge_rx_setup()
954 rd->csum2 = 0; in skge_rx_setup()
961 return 0; in skge_rx_setup()
972 rd->csum2 = 0; in skge_rx_reuse()
991 rd->control = 0; in skge_rx_clean()
1023 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) { in skge_rx_fill()
1030 return 0; in skge_rx_fill()
1095 for (i = 0; i < PHY_RETRIES; i++) { in __xm_phy_read()
1105 return 0; in __xm_phy_read()
1110 u16 v = 0; in xm_phy_read()
1121 for (i = 0; i < PHY_RETRIES; i++) { in xm_phy_write()
1130 for (i = 0; i < PHY_RETRIES; i++) { in xm_phy_write()
1132 return 0; in xm_phy_write()
1153 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_init()
1154 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_init()
1155 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_init()
1156 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_init()
1168 static const u8 zero[8] = { 0 }; in genesis_reset()
1171 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in genesis_reset()
1176 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ in genesis_reset()
1177 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ in genesis_reset()
1178 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ in genesis_reset()
1182 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); in genesis_reset()
1194 [FLOW_MODE_NONE] = 0,
1220 if ((status & PHY_ST_LSYNC) == 0) { in bcom_check_link()
1252 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ in bcom_check_link()
1288 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, in bcom_phy_init()
1289 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, in bcom_phy_init()
1290 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, in bcom_phy_init()
1291 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, in bcom_phy_init()
1293 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, in bcom_phy_init()
1294 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, in bcom_phy_init()
1311 for (i = 0; i < ARRAY_SIZE(C0hack); i++) in bcom_phy_init()
1321 for (i = 0; i < ARRAY_SIZE(A1hack); i++) in bcom_phy_init()
1386 u16 ctrl = 0; in xm_phy_init()
1427 if ((status & PHY_ST_LSYNC) == 0) { in xm_check_link()
1429 return 0; in xm_check_link()
1436 return 0; in xm_check_link()
1441 return 0; in xm_check_link()
1456 return 0; in xm_check_link()
1459 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ in xm_check_link()
1507 for (i = 0; i < 3; i++) { in xm_link_timer()
1533 static const u8 zero[6] = { 0 }; in genesis_mac_init()
1535 for (i = 0; i < 10; i++) { in genesis_mac_init()
1557 if (port == 0) in genesis_mac_init()
1659 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_mac_init()
1660 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_mac_init()
1661 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_mac_init()
1662 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_mac_init()
1680 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); in genesis_mac_init()
1700 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); in genesis_stop()
1708 } while (--retries > 0); in genesis_stop()
1713 if (port == 0) { in genesis_stop()
1751 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 in genesis_get_stats()
1767 "mac interrupt status 0x%x\n", status); in genesis_mac_intr()
1815 /* XM_MAC_PTIME = 0xffff (maximum) */ in genesis_link_up()
1817 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); in genesis_link_up()
1872 "phy interrupt status 0x%x\n", isrc); in bcom_phy_intr()
1901 for (i = 0; i < PHY_RETRIES; i++) { in gm_phy_write()
1905 return 0; in gm_phy_write()
1920 for (i = 0; i < PHY_RETRIES; i++) { in __gm_phy_read()
1929 return 0; in __gm_phy_read()
1934 u16 v = 0; in gm_phy_read()
1953 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); in yukon_init()
1965 ctrl = 0; in yukon_init()
1966 ct1000 = 0; in yukon_init()
2030 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ in yukon_reset()
2031 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ in yukon_reset()
2032 gma_write16(hw, port, GM_MC_ADDR_H2, 0); in yukon_reset()
2033 gma_write16(hw, port, GM_MC_ADDR_H3, 0); in yukon_reset()
2034 gma_write16(hw, port, GM_MC_ADDR_H4, 0); in yukon_reset()
2048 return 0; in is_yukon_lite_a0()
2051 skge_write8(hw, B2_FAR + 3, 0xff); in is_yukon_lite_a0()
2052 ret = (skge_read8(hw, B2_FAR + 3) != 0); in is_yukon_lite_a0()
2143 for (i = 0; i < GM_MIB_CNT_SIZE; i++) in yukon_mac_init()
2155 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); in yukon_mac_init()
2179 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); in yukon_mac_init()
2180 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); in yukon_mac_init()
2181 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); in yukon_mac_init()
2231 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in yukon_stop()
2252 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 in yukon_get_stats()
2269 "mac interrupt status 0x%x\n", status); in yukon_mac_intr()
2349 "phy interrupt status 0x%x 0x%x\n", istatus, phystat); in yukon_phy_intr()
2372 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ in yukon_phy_intr()
2453 u16 val = 0; in skge_ioctl()
2457 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2459 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2468 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2471 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2514 u32 watermark = 0x600; in skge_qset()
2518 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) in skge_qset()
2621 return 0; in skge_up()
2652 return 0; in skge_down()
2666 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask); in skge_down()
2690 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); in skge_down()
2691 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); in skge_down()
2698 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); in skge_down()
2723 return 0; in skge_down()
2729 return ((ring->to_clean > ring->to_use) ? 0 : ring->count) in skge_avail()
2772 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) in skge_xmit_frame()
2777 td->csum_offs = 0; in skge_xmit_frame()
2789 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in skge_xmit_frame()
2792 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0, in skge_xmit_frame()
2838 while (i-- > 0) { in skge_xmit_frame()
2878 td->control = 0; in skge_tx_clean()
2902 return 0; in skge_change_mtu()
2916 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2923 bit = ~crc & 0x3f; in genesis_add_filter()
2944 memset(filter, 0xff, sizeof(filter)); in genesis_set_multicast()
2946 memset(filter, 0, sizeof(filter)); in genesis_set_multicast()
2962 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f; in yukon_add_filter()
2977 memset(filter, 0, sizeof(filter)); in yukon_set_multicast()
2985 memset(filter, 0xff, sizeof(filter)); in yukon_set_multicast()
3000 (u16)filter[0] | ((u16)filter[1] << 8)); in yukon_set_multicast()
3022 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; in bad_phy_status()
3025 (status & GMR_FS_RX_OK) == 0; in bad_phy_status()
3052 "rx slot %td status 0x%x len %d\n", in skge_rx_get()
3095 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) { in skge_rx_get()
3118 "rx err, slot %td control 0x%x status 0x%x\n", in skge_rx_get()
3148 unsigned int bytes_compl = 0, pkts_compl = 0; in skge_tx_done()
3196 int work_done = 0; in skge_poll()
3252 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in skge_mac_parity()
3293 skge_mac_parity(hw, 0); in skge_error_irq()
3300 hw->dev[0]->name); in skge_error_irq()
3346 for (port = 0; port < hw->ports; port++) { in skge_extirq()
3372 int handled = 0; in skge_intr()
3377 if (status == 0 || status == ~0) in skge_intr()
3388 struct skge_port *skge = netdev_priv(hw->dev[0]); in skge_intr()
3397 ++hw->dev[0]->stats.rx_over_errors; in skge_intr()
3403 skge_mac_intr(hw, 0); in skge_intr()
3482 return 0; in skge_set_mac_address()
3500 for (i = 0; i < ARRAY_SIZE(skge_chips); i++) in skge_board_name()
3504 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id); in skge_board_name()
3528 skge_write8(hw, B2_TST_CTRL2, 0); in skge_reset()
3541 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; in skge_reset()
3556 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", in skge_reset()
3576 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", in skge_reset()
3589 /* special case: 4 x 64k x 36, offset = 0x80000 */ in skge_reset()
3590 hw->ram_size = 0x100000; in skge_reset()
3591 hw->ram_offset = 0x80000; in skge_reset()
3594 } else if (t8 == 0) in skge_reset()
3595 hw->ram_size = 0x20000; in skge_reset()
3627 for (i = 0; i < hw->ports; i++) { in skge_reset()
3639 for (i = 0; i < hw->ports; i++) in skge_reset()
3668 skge_write32(hw, B0_IMSK, 0); in skge_reset()
3670 for (i = 0; i < hw->ports; i++) { in skge_reset()
3677 return 0; in skge_reset()
3718 return 0; in skge_debug_show()
3852 timer_setup(&skge->link_timer, xm_link_timer, 0); in skge_devinit()
3878 int err, using_dac = 0; in skge_probe()
3898 using_dac = 0; in skge_probe()
3932 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000); in skge_probe()
3942 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n", in skge_probe()
3944 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, in skge_probe()
3947 dev = skge_devinit(hw, 0, using_dac); in skge_probe()
3990 return 0; in skge_probe()
4025 dev0 = hw->dev[0]; in skge_remove()
4031 hw->intr_mask = 0; in skge_remove()
4034 skge_write32(hw, B0_IMSK, 0); in skge_remove()
4061 return 0; in skge_suspend()
4063 for (i = 0; i < hw->ports; i++) { in skge_suspend()
4074 skge_write32(hw, B0_IMSK, 0); in skge_suspend()
4076 return 0; in skge_suspend()
4085 return 0; in skge_resume()
4091 for (i = 0; i < hw->ports; i++) { in skge_resume()
4124 for (i = 0; i < hw->ports; i++) { in skge_shutdown()