Lines Matching +full:msi +full:- +full:base +full:- +full:vec
1 // SPDX-License-Identifier: GPL-2.0
25 #define DRV_NAME "octeontx2-af"
62 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_capabilities()
64 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; in rvu_setup_hw_capabilities()
65 hw->cap.nix_fixed_txschq_mapping = false; in rvu_setup_hw_capabilities()
66 hw->cap.nix_shaping = true; in rvu_setup_hw_capabilities()
67 hw->cap.nix_tx_link_bp = true; in rvu_setup_hw_capabilities()
68 hw->cap.nix_rx_multicast = true; in rvu_setup_hw_capabilities()
71 hw->cap.nix_fixed_txschq_mapping = true; in rvu_setup_hw_capabilities()
72 hw->cap.nix_txsch_per_cgx_lmac = 4; in rvu_setup_hw_capabilities()
73 hw->cap.nix_txsch_per_lbk_lmac = 132; in rvu_setup_hw_capabilities()
74 hw->cap.nix_txsch_per_sdp_lmac = 76; in rvu_setup_hw_capabilities()
75 hw->cap.nix_shaping = false; in rvu_setup_hw_capabilities()
76 hw->cap.nix_tx_link_bp = false; in rvu_setup_hw_capabilities()
78 hw->cap.nix_rx_multicast = false; in rvu_setup_hw_capabilities()
91 reg = rvu->afreg_base + ((block << 28) | offset); in rvu_poll_reg()
102 return -EBUSY; in rvu_poll_reg()
109 if (!rsrc->bmap) in rvu_alloc_rsrc()
110 return -EINVAL; in rvu_alloc_rsrc()
112 id = find_first_zero_bit(rsrc->bmap, rsrc->max); in rvu_alloc_rsrc()
113 if (id >= rsrc->max) in rvu_alloc_rsrc()
114 return -ENOSPC; in rvu_alloc_rsrc()
116 __set_bit(id, rsrc->bmap); in rvu_alloc_rsrc()
125 if (!rsrc->bmap) in rvu_alloc_rsrc_contig()
126 return -EINVAL; in rvu_alloc_rsrc_contig()
128 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); in rvu_alloc_rsrc_contig()
129 if (start >= rsrc->max) in rvu_alloc_rsrc_contig()
130 return -ENOSPC; in rvu_alloc_rsrc_contig()
132 bitmap_set(rsrc->bmap, start, nrsrc); in rvu_alloc_rsrc_contig()
138 if (!rsrc->bmap) in rvu_free_rsrc_contig()
140 if (start >= rsrc->max) in rvu_free_rsrc_contig()
143 bitmap_clear(rsrc->bmap, start, nrsrc); in rvu_free_rsrc_contig()
150 if (!rsrc->bmap) in rvu_rsrc_check_contig()
153 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); in rvu_rsrc_check_contig()
154 if (start >= rsrc->max) in rvu_rsrc_check_contig()
162 if (!rsrc->bmap) in rvu_free_rsrc()
165 __clear_bit(id, rsrc->bmap); in rvu_free_rsrc()
172 if (!rsrc->bmap) in rvu_rsrc_free_count()
175 used = bitmap_weight(rsrc->bmap, rsrc->max); in rvu_rsrc_free_count()
176 return (rsrc->max - used); in rvu_rsrc_free_count()
181 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), in rvu_alloc_bitmap()
183 if (!rsrc->bmap) in rvu_alloc_bitmap()
184 return -ENOMEM; in rvu_alloc_bitmap()
194 mutex_lock(&rvu->rsrc_lock); in rvu_get_lf()
195 for (lf = 0; lf < block->lf.max; lf++) { in rvu_get_lf()
196 if (block->fn_map[lf] == pcifunc) { in rvu_get_lf()
198 mutex_unlock(&rvu->rsrc_lock); in rvu_get_lf()
204 mutex_unlock(&rvu->rsrc_lock); in rvu_get_lf()
205 return -ENODEV; in rvu_get_lf()
216 int devnum, blkaddr = -ENODEV; in rvu_get_blkaddr()
278 if (is_block_implemented(rvu->hw, blkaddr)) in rvu_get_blkaddr()
280 return -ENODEV; in rvu_get_blkaddr()
291 if (lf >= block->lf.max) { in rvu_update_rsrc_map()
292 dev_err(&rvu->pdev->dev, in rvu_update_rsrc_map()
294 __func__, lf, block->name, block->lf.max); in rvu_update_rsrc_map()
307 block->fn_map[lf] = attach ? pcifunc : 0; in rvu_update_rsrc_map()
309 switch (block->type) { in rvu_update_rsrc_map()
311 pfvf->npalf = attach ? true : false; in rvu_update_rsrc_map()
312 num_lfs = pfvf->npalf; in rvu_update_rsrc_map()
315 pfvf->nixlf = attach ? true : false; in rvu_update_rsrc_map()
316 num_lfs = pfvf->nixlf; in rvu_update_rsrc_map()
319 attach ? pfvf->sso++ : pfvf->sso--; in rvu_update_rsrc_map()
320 num_lfs = pfvf->sso; in rvu_update_rsrc_map()
323 attach ? pfvf->ssow++ : pfvf->ssow--; in rvu_update_rsrc_map()
324 num_lfs = pfvf->ssow; in rvu_update_rsrc_map()
327 attach ? pfvf->timlfs++ : pfvf->timlfs--; in rvu_update_rsrc_map()
328 num_lfs = pfvf->timlfs; in rvu_update_rsrc_map()
331 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; in rvu_update_rsrc_map()
332 num_lfs = pfvf->cptlfs; in rvu_update_rsrc_map()
336 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; in rvu_update_rsrc_map()
366 return ((cfg & 0xFFF) + func - 1); in rvu_get_hwvf()
373 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; in rvu_get_pfvf()
375 return &rvu->pf[rvu_get_pf(pcifunc)]; in rvu_get_pfvf()
384 if (pf >= rvu->hw->total_pfs) in is_pf_func_valid()
391 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; in is_pf_func_valid()
407 block = &hw->block[blkaddr]; in is_block_implemented()
408 return block->implemented; in is_block_implemented()
413 struct rvu_hwinfo *hw = rvu->hw; in rvu_check_block_implemented()
420 block = &hw->block[blkid]; in rvu_check_block_implemented()
423 block->implemented = true; in rvu_check_block_implemented()
444 if (!block->implemented) in rvu_lf_reset()
447 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); in rvu_lf_reset()
448 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), in rvu_lf_reset()
455 struct rvu_block *block = &rvu->hw->block[blkaddr]; in rvu_block_reset()
457 if (!block->implemented) in rvu_block_reset()
484 for (lf = 0; lf < block->lf.max; lf++) { in rvu_scan_block()
485 cfg = rvu_read64(rvu, block->addr, in rvu_scan_block()
486 block->lfcfg_reg | (lf << block->lfshift)); in rvu_scan_block()
491 __set_bit(lf, block->lf.bmap); in rvu_scan_block()
511 dev_warn(rvu->dev, in rvu_check_min_msix_vec()
513 pf, vf - 1, nvecs); in rvu_check_min_msix_vec()
525 dev_warn(rvu->dev, in rvu_check_min_msix_vec()
532 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_msix_resources()
539 for (pf = 0; pf < hw->total_pfs; pf++) { in rvu_setup_msix_resources()
547 pfvf = &rvu->pf[pf]; in rvu_setup_msix_resources()
550 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; in rvu_setup_msix_resources()
551 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); in rvu_setup_msix_resources()
554 err = rvu_alloc_bitmap(&pfvf->msix); in rvu_setup_msix_resources()
559 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, in rvu_setup_msix_resources()
561 if (!pfvf->msix_lfmap) in rvu_setup_msix_resources()
562 return -ENOMEM; in rvu_setup_msix_resources()
577 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); in rvu_setup_msix_resources()
583 pfvf = &rvu->hwvf[hwvf + vf]; in rvu_setup_msix_resources()
587 pfvf->msix.max = (cfg & 0xFFF) + 1; in rvu_setup_msix_resources()
588 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); in rvu_setup_msix_resources()
591 err = rvu_alloc_bitmap(&pfvf->msix); in rvu_setup_msix_resources()
595 pfvf->msix_lfmap = in rvu_setup_msix_resources()
596 devm_kcalloc(rvu->dev, pfvf->msix.max, in rvu_setup_msix_resources()
598 if (!pfvf->msix_lfmap) in rvu_setup_msix_resources()
599 return -ENOMEM; in rvu_setup_msix_resources()
609 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); in rvu_setup_msix_resources()
622 if (rvu->fwdata && rvu->fwdata->msixtr_base) in rvu_setup_msix_resources()
623 phy_addr = rvu->fwdata->msixtr_base; in rvu_setup_msix_resources()
627 iova = dma_map_resource(rvu->dev, phy_addr, in rvu_setup_msix_resources()
631 if (dma_mapping_error(rvu->dev, iova)) in rvu_setup_msix_resources()
632 return -ENOMEM; in rvu_setup_msix_resources()
635 rvu->msix_base_iova = iova; in rvu_setup_msix_resources()
636 rvu->msixtr_base_phy = phy_addr; in rvu_setup_msix_resources()
643 /* Restore msixtr base register */ in rvu_reset_msix()
645 rvu->msixtr_base_phy); in rvu_reset_msix()
650 struct rvu_hwinfo *hw = rvu->hw; in rvu_free_hw_resources()
662 block = &hw->block[id]; in rvu_free_hw_resources()
663 kfree(block->lf.bmap); in rvu_free_hw_resources()
667 for (id = 0; id < hw->total_pfs; id++) { in rvu_free_hw_resources()
668 pfvf = &rvu->pf[id]; in rvu_free_hw_resources()
669 kfree(pfvf->msix.bmap); in rvu_free_hw_resources()
672 for (id = 0; id < hw->total_vfs; id++) { in rvu_free_hw_resources()
673 pfvf = &rvu->hwvf[id]; in rvu_free_hw_resources()
674 kfree(pfvf->msix.bmap); in rvu_free_hw_resources()
677 /* Unmap MSIX vector base IOVA mapping */ in rvu_free_hw_resources()
678 if (!rvu->msix_base_iova) in rvu_free_hw_resources()
682 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, in rvu_free_hw_resources()
687 mutex_destroy(&rvu->rsrc_lock); in rvu_free_hw_resources()
692 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_pfvf_macaddress()
697 for (pf = 0; pf < hw->total_pfs; pf++) { in rvu_setup_pfvf_macaddress()
701 pfvf = &rvu->pf[pf]; in rvu_setup_pfvf_macaddress()
702 if (rvu->fwdata && pf < PF_MACNUM_MAX) { in rvu_setup_pfvf_macaddress()
703 mac = &rvu->fwdata->pf_macs[pf]; in rvu_setup_pfvf_macaddress()
705 u64_to_ether_addr(*mac, pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
707 eth_random_addr(pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
709 eth_random_addr(pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
715 pfvf = &rvu->hwvf[hwvf]; in rvu_setup_pfvf_macaddress()
716 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { in rvu_setup_pfvf_macaddress()
717 mac = &rvu->fwdata->vf_macs[hwvf]; in rvu_setup_pfvf_macaddress()
719 u64_to_ether_addr(*mac, pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
721 eth_random_addr(pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
723 eth_random_addr(pfvf->mac_addr); in rvu_setup_pfvf_macaddress()
734 /* Get firmware data base address */ in rvu_fwdata_init()
738 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); in rvu_fwdata_init()
739 if (!rvu->fwdata) in rvu_fwdata_init()
742 dev_err(rvu->dev, in rvu_fwdata_init()
744 iounmap(rvu->fwdata); in rvu_fwdata_init()
745 rvu->fwdata = NULL; in rvu_fwdata_init()
746 return -EINVAL; in rvu_fwdata_init()
750 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); in rvu_fwdata_init()
751 return -EIO; in rvu_fwdata_init()
756 if (rvu->fwdata) in rvu_fwdata_exit()
757 iounmap(rvu->fwdata); in rvu_fwdata_exit()
762 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_resources()
769 hw->total_pfs = (cfg >> 32) & 0xFF; in rvu_setup_hw_resources()
770 hw->total_vfs = (cfg >> 20) & 0xFFF; in rvu_setup_hw_resources()
771 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; in rvu_setup_hw_resources()
774 block = &hw->block[BLKADDR_NPA]; in rvu_setup_hw_resources()
775 if (!block->implemented) in rvu_setup_hw_resources()
778 block->lf.max = (cfg >> 16) & 0xFFF; in rvu_setup_hw_resources()
779 block->addr = BLKADDR_NPA; in rvu_setup_hw_resources()
780 block->type = BLKTYPE_NPA; in rvu_setup_hw_resources()
781 block->lfshift = 8; in rvu_setup_hw_resources()
782 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; in rvu_setup_hw_resources()
783 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; in rvu_setup_hw_resources()
784 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; in rvu_setup_hw_resources()
785 block->lfcfg_reg = NPA_PRIV_LFX_CFG; in rvu_setup_hw_resources()
786 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; in rvu_setup_hw_resources()
787 block->lfreset_reg = NPA_AF_LF_RST; in rvu_setup_hw_resources()
788 sprintf(block->name, "NPA"); in rvu_setup_hw_resources()
789 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
795 block = &hw->block[BLKADDR_NIX0]; in rvu_setup_hw_resources()
796 if (!block->implemented) in rvu_setup_hw_resources()
799 block->lf.max = cfg & 0xFFF; in rvu_setup_hw_resources()
800 block->addr = BLKADDR_NIX0; in rvu_setup_hw_resources()
801 block->type = BLKTYPE_NIX; in rvu_setup_hw_resources()
802 block->lfshift = 8; in rvu_setup_hw_resources()
803 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; in rvu_setup_hw_resources()
804 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIX0_CFG; in rvu_setup_hw_resources()
805 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIX0_CFG; in rvu_setup_hw_resources()
806 block->lfcfg_reg = NIX_PRIV_LFX_CFG; in rvu_setup_hw_resources()
807 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; in rvu_setup_hw_resources()
808 block->lfreset_reg = NIX_AF_LF_RST; in rvu_setup_hw_resources()
809 sprintf(block->name, "NIX"); in rvu_setup_hw_resources()
810 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
816 block = &hw->block[BLKADDR_SSO]; in rvu_setup_hw_resources()
817 if (!block->implemented) in rvu_setup_hw_resources()
820 block->lf.max = cfg & 0xFFFF; in rvu_setup_hw_resources()
821 block->addr = BLKADDR_SSO; in rvu_setup_hw_resources()
822 block->type = BLKTYPE_SSO; in rvu_setup_hw_resources()
823 block->multislot = true; in rvu_setup_hw_resources()
824 block->lfshift = 3; in rvu_setup_hw_resources()
825 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; in rvu_setup_hw_resources()
826 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; in rvu_setup_hw_resources()
827 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; in rvu_setup_hw_resources()
828 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; in rvu_setup_hw_resources()
829 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; in rvu_setup_hw_resources()
830 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; in rvu_setup_hw_resources()
831 sprintf(block->name, "SSO GROUP"); in rvu_setup_hw_resources()
832 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
838 block = &hw->block[BLKADDR_SSOW]; in rvu_setup_hw_resources()
839 if (!block->implemented) in rvu_setup_hw_resources()
841 block->lf.max = (cfg >> 56) & 0xFF; in rvu_setup_hw_resources()
842 block->addr = BLKADDR_SSOW; in rvu_setup_hw_resources()
843 block->type = BLKTYPE_SSOW; in rvu_setup_hw_resources()
844 block->multislot = true; in rvu_setup_hw_resources()
845 block->lfshift = 3; in rvu_setup_hw_resources()
846 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; in rvu_setup_hw_resources()
847 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; in rvu_setup_hw_resources()
848 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; in rvu_setup_hw_resources()
849 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; in rvu_setup_hw_resources()
850 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; in rvu_setup_hw_resources()
851 block->lfreset_reg = SSOW_AF_LF_HWS_RST; in rvu_setup_hw_resources()
852 sprintf(block->name, "SSOWS"); in rvu_setup_hw_resources()
853 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
859 block = &hw->block[BLKADDR_TIM]; in rvu_setup_hw_resources()
860 if (!block->implemented) in rvu_setup_hw_resources()
863 block->lf.max = cfg & 0xFFFF; in rvu_setup_hw_resources()
864 block->addr = BLKADDR_TIM; in rvu_setup_hw_resources()
865 block->type = BLKTYPE_TIM; in rvu_setup_hw_resources()
866 block->multislot = true; in rvu_setup_hw_resources()
867 block->lfshift = 3; in rvu_setup_hw_resources()
868 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; in rvu_setup_hw_resources()
869 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; in rvu_setup_hw_resources()
870 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; in rvu_setup_hw_resources()
871 block->lfcfg_reg = TIM_PRIV_LFX_CFG; in rvu_setup_hw_resources()
872 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; in rvu_setup_hw_resources()
873 block->lfreset_reg = TIM_AF_LF_RST; in rvu_setup_hw_resources()
874 sprintf(block->name, "TIM"); in rvu_setup_hw_resources()
875 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
881 block = &hw->block[BLKADDR_CPT0]; in rvu_setup_hw_resources()
882 if (!block->implemented) in rvu_setup_hw_resources()
885 block->lf.max = cfg & 0xFF; in rvu_setup_hw_resources()
886 block->addr = BLKADDR_CPT0; in rvu_setup_hw_resources()
887 block->type = BLKTYPE_CPT; in rvu_setup_hw_resources()
888 block->multislot = true; in rvu_setup_hw_resources()
889 block->lfshift = 3; in rvu_setup_hw_resources()
890 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; in rvu_setup_hw_resources()
891 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPT0_CFG; in rvu_setup_hw_resources()
892 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPT0_CFG; in rvu_setup_hw_resources()
893 block->lfcfg_reg = CPT_PRIV_LFX_CFG; in rvu_setup_hw_resources()
894 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; in rvu_setup_hw_resources()
895 block->lfreset_reg = CPT_AF_LF_RST; in rvu_setup_hw_resources()
896 sprintf(block->name, "CPT"); in rvu_setup_hw_resources()
897 err = rvu_alloc_bitmap(&block->lf); in rvu_setup_hw_resources()
903 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, in rvu_setup_hw_resources()
905 if (!rvu->pf) in rvu_setup_hw_resources()
906 return -ENOMEM; in rvu_setup_hw_resources()
908 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, in rvu_setup_hw_resources()
910 if (!rvu->hwvf) in rvu_setup_hw_resources()
911 return -ENOMEM; in rvu_setup_hw_resources()
913 mutex_init(&rvu->rsrc_lock); in rvu_setup_hw_resources()
922 block = &hw->block[blkid]; in rvu_setup_hw_resources()
923 if (!block->lf.bmap) in rvu_setup_hw_resources()
927 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, in rvu_setup_hw_resources()
929 if (!block->fn_map) { in rvu_setup_hw_resources()
930 err = -ENOMEM; in rvu_setup_hw_resources()
981 qmem_free(rvu->dev, aq->inst); in rvu_aq_free()
982 qmem_free(rvu->dev, aq->res); in rvu_aq_free()
983 devm_kfree(rvu->dev, aq); in rvu_aq_free()
992 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); in rvu_aq_alloc()
994 return -ENOMEM; in rvu_aq_alloc()
998 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); in rvu_aq_alloc()
1000 devm_kfree(rvu->dev, aq); in rvu_aq_alloc()
1005 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); in rvu_aq_alloc()
1011 spin_lock_init(&aq->lock); in rvu_aq_alloc()
1018 if (rvu->fwdata) { in rvu_mbox_handler_ready()
1019 rsp->rclk_freq = rvu->fwdata->rclk; in rvu_mbox_handler_ready()
1020 rsp->sclk_freq = rvu->fwdata->sclk; in rvu_mbox_handler_ready()
1032 return pfvf->npalf ? 1 : 0; in rvu_get_rsrc_mapcount()
1034 return pfvf->nixlf ? 1 : 0; in rvu_get_rsrc_mapcount()
1036 return pfvf->sso; in rvu_get_rsrc_mapcount()
1038 return pfvf->ssow; in rvu_get_rsrc_mapcount()
1040 return pfvf->timlfs; in rvu_get_rsrc_mapcount()
1042 return pfvf->cptlfs; in rvu_get_rsrc_mapcount()
1069 rvu_write64(rvu, block->addr, block->lookup_reg, val); in rvu_lookup_rsrc()
1072 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) in rvu_lookup_rsrc()
1075 val = rvu_read64(rvu, block->addr, block->lookup_reg); in rvu_lookup_rsrc()
1079 return -1; in rvu_lookup_rsrc()
1087 struct rvu_hwinfo *hw = rvu->hw; in rvu_detach_block()
1096 block = &hw->block[blkaddr]; in rvu_detach_block()
1098 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->type); in rvu_detach_block()
1108 rvu_write64(rvu, blkaddr, block->lfcfg_reg | in rvu_detach_block()
1109 (lf << block->lfshift), 0x00ULL); in rvu_detach_block()
1116 rvu_free_rsrc(&block->lf, lf); in rvu_detach_block()
1126 struct rvu_hwinfo *hw = rvu->hw; in rvu_detach_rsrcs()
1131 mutex_lock(&rvu->rsrc_lock); in rvu_detach_rsrcs()
1134 if (detach && detach->partial) in rvu_detach_rsrcs()
1141 block = &hw->block[blkid]; in rvu_detach_rsrcs()
1142 if (!block->lf.bmap) in rvu_detach_rsrcs()
1145 if (blkid == BLKADDR_NPA && !detach->npalf) in rvu_detach_rsrcs()
1147 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) in rvu_detach_rsrcs()
1149 else if ((blkid == BLKADDR_SSO) && !detach->sso) in rvu_detach_rsrcs()
1151 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) in rvu_detach_rsrcs()
1153 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) in rvu_detach_rsrcs()
1155 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) in rvu_detach_rsrcs()
1158 rvu_detach_block(rvu, pcifunc, block->type); in rvu_detach_rsrcs()
1161 mutex_unlock(&rvu->rsrc_lock); in rvu_detach_rsrcs()
1169 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); in rvu_mbox_handler_detach_resources()
1176 struct rvu_hwinfo *hw = rvu->hw; in rvu_attach_block()
1189 block = &hw->block[blkaddr]; in rvu_attach_block()
1190 if (!block->lf.bmap) in rvu_attach_block()
1195 lf = rvu_alloc_rsrc(&block->lf); in rvu_attach_block()
1200 rvu_write64(rvu, blkaddr, block->lfcfg_reg | in rvu_attach_block()
1201 (lf << block->lfshift), cfg); in rvu_attach_block()
1214 struct rvu_hwinfo *hw = rvu->hw; in rvu_check_rsrc_availability()
1219 if (req->npalf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NPA)) { in rvu_check_rsrc_availability()
1220 block = &hw->block[BLKADDR_NPA]; in rvu_check_rsrc_availability()
1221 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1224 } else if (req->npalf) { in rvu_check_rsrc_availability()
1225 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1228 return -EINVAL; in rvu_check_rsrc_availability()
1232 if (req->nixlf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NIX)) { in rvu_check_rsrc_availability()
1233 block = &hw->block[BLKADDR_NIX0]; in rvu_check_rsrc_availability()
1234 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1237 } else if (req->nixlf) { in rvu_check_rsrc_availability()
1238 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1241 return -EINVAL; in rvu_check_rsrc_availability()
1244 if (req->sso) { in rvu_check_rsrc_availability()
1245 block = &hw->block[BLKADDR_SSO]; in rvu_check_rsrc_availability()
1247 if (req->sso > block->lf.max) { in rvu_check_rsrc_availability()
1248 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1250 pcifunc, req->sso, block->lf.max); in rvu_check_rsrc_availability()
1251 return -EINVAL; in rvu_check_rsrc_availability()
1253 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); in rvu_check_rsrc_availability()
1254 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1256 if (req->sso > mappedlfs && in rvu_check_rsrc_availability()
1257 ((req->sso - mappedlfs) > free_lfs)) in rvu_check_rsrc_availability()
1261 if (req->ssow) { in rvu_check_rsrc_availability()
1262 block = &hw->block[BLKADDR_SSOW]; in rvu_check_rsrc_availability()
1263 if (req->ssow > block->lf.max) { in rvu_check_rsrc_availability()
1264 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1266 pcifunc, req->sso, block->lf.max); in rvu_check_rsrc_availability()
1267 return -EINVAL; in rvu_check_rsrc_availability()
1269 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); in rvu_check_rsrc_availability()
1270 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1271 if (req->ssow > mappedlfs && in rvu_check_rsrc_availability()
1272 ((req->ssow - mappedlfs) > free_lfs)) in rvu_check_rsrc_availability()
1276 if (req->timlfs) { in rvu_check_rsrc_availability()
1277 block = &hw->block[BLKADDR_TIM]; in rvu_check_rsrc_availability()
1278 if (req->timlfs > block->lf.max) { in rvu_check_rsrc_availability()
1279 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1281 pcifunc, req->timlfs, block->lf.max); in rvu_check_rsrc_availability()
1282 return -EINVAL; in rvu_check_rsrc_availability()
1284 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); in rvu_check_rsrc_availability()
1285 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1286 if (req->timlfs > mappedlfs && in rvu_check_rsrc_availability()
1287 ((req->timlfs - mappedlfs) > free_lfs)) in rvu_check_rsrc_availability()
1291 if (req->cptlfs) { in rvu_check_rsrc_availability()
1292 block = &hw->block[BLKADDR_CPT0]; in rvu_check_rsrc_availability()
1293 if (req->cptlfs > block->lf.max) { in rvu_check_rsrc_availability()
1294 dev_err(&rvu->pdev->dev, in rvu_check_rsrc_availability()
1296 pcifunc, req->cptlfs, block->lf.max); in rvu_check_rsrc_availability()
1297 return -EINVAL; in rvu_check_rsrc_availability()
1299 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); in rvu_check_rsrc_availability()
1300 free_lfs = rvu_rsrc_free_count(&block->lf); in rvu_check_rsrc_availability()
1301 if (req->cptlfs > mappedlfs && in rvu_check_rsrc_availability()
1302 ((req->cptlfs - mappedlfs) > free_lfs)) in rvu_check_rsrc_availability()
1309 dev_info(rvu->dev, "Request for %s failed\n", block->name); in rvu_check_rsrc_availability()
1310 return -ENOSPC; in rvu_check_rsrc_availability()
1317 u16 pcifunc = attach->hdr.pcifunc; in rvu_mbox_handler_attach_resources()
1321 if (!attach->modify) in rvu_mbox_handler_attach_resources()
1324 mutex_lock(&rvu->rsrc_lock); in rvu_mbox_handler_attach_resources()
1332 if (attach->npalf) in rvu_mbox_handler_attach_resources()
1335 if (attach->nixlf) in rvu_mbox_handler_attach_resources()
1338 if (attach->sso) { in rvu_mbox_handler_attach_resources()
1344 if (attach->modify) in rvu_mbox_handler_attach_resources()
1346 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, attach->sso); in rvu_mbox_handler_attach_resources()
1349 if (attach->ssow) { in rvu_mbox_handler_attach_resources()
1350 if (attach->modify) in rvu_mbox_handler_attach_resources()
1352 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, attach->ssow); in rvu_mbox_handler_attach_resources()
1355 if (attach->timlfs) { in rvu_mbox_handler_attach_resources()
1356 if (attach->modify) in rvu_mbox_handler_attach_resources()
1358 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, attach->timlfs); in rvu_mbox_handler_attach_resources()
1361 if (attach->cptlfs) { in rvu_mbox_handler_attach_resources()
1362 if (attach->modify) in rvu_mbox_handler_attach_resources()
1364 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, attach->cptlfs); in rvu_mbox_handler_attach_resources()
1368 mutex_unlock(&rvu->rsrc_lock); in rvu_mbox_handler_attach_resources()
1375 u16 vec; in rvu_get_msix_offset() local
1380 for (vec = 0; vec < pfvf->msix.max; vec++) { in rvu_get_msix_offset()
1381 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) in rvu_get_msix_offset()
1382 return vec; in rvu_get_msix_offset()
1390 u16 nvecs, vec, offset; in rvu_set_msix_offset() local
1393 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | in rvu_set_msix_offset()
1394 (lf << block->lfshift)); in rvu_set_msix_offset()
1398 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) in rvu_set_msix_offset()
1401 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); in rvu_set_msix_offset()
1404 rvu_write64(rvu, block->addr, block->msixcfg_reg | in rvu_set_msix_offset()
1405 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); in rvu_set_msix_offset()
1408 for (vec = 0; vec < nvecs; vec++) in rvu_set_msix_offset()
1409 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); in rvu_set_msix_offset()
1415 u16 nvecs, vec, offset; in rvu_clear_msix_offset() local
1418 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | in rvu_clear_msix_offset()
1419 (lf << block->lfshift)); in rvu_clear_msix_offset()
1423 rvu_write64(rvu, block->addr, block->msixcfg_reg | in rvu_clear_msix_offset()
1424 (lf << block->lfshift), cfg & ~0x7FFULL); in rvu_clear_msix_offset()
1426 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); in rvu_clear_msix_offset()
1429 for (vec = 0; vec < nvecs; vec++) in rvu_clear_msix_offset()
1430 pfvf->msix_lfmap[offset + vec] = 0; in rvu_clear_msix_offset()
1433 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); in rvu_clear_msix_offset()
1439 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_msix_offset()
1440 u16 pcifunc = req->hdr.pcifunc; in rvu_mbox_handler_msix_offset()
1445 if (!pfvf->msix.bmap) in rvu_mbox_handler_msix_offset()
1449 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); in rvu_mbox_handler_msix_offset()
1450 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); in rvu_mbox_handler_msix_offset()
1452 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NIX0], pcifunc, 0); in rvu_mbox_handler_msix_offset()
1453 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NIX0, lf); in rvu_mbox_handler_msix_offset()
1455 rsp->sso = pfvf->sso; in rvu_mbox_handler_msix_offset()
1456 for (slot = 0; slot < rsp->sso; slot++) { in rvu_mbox_handler_msix_offset()
1457 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1458 rsp->sso_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1462 rsp->ssow = pfvf->ssow; in rvu_mbox_handler_msix_offset()
1463 for (slot = 0; slot < rsp->ssow; slot++) { in rvu_mbox_handler_msix_offset()
1464 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1465 rsp->ssow_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1469 rsp->timlfs = pfvf->timlfs; in rvu_mbox_handler_msix_offset()
1470 for (slot = 0; slot < rsp->timlfs; slot++) { in rvu_mbox_handler_msix_offset()
1471 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1472 rsp->timlf_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1476 rsp->cptlfs = pfvf->cptlfs; in rvu_mbox_handler_msix_offset()
1477 for (slot = 0; slot < rsp->cptlfs; slot++) { in rvu_mbox_handler_msix_offset()
1478 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); in rvu_mbox_handler_msix_offset()
1479 rsp->cptlf_msixoff[slot] = in rvu_mbox_handler_msix_offset()
1488 u16 pcifunc = req->hdr.pcifunc; in rvu_mbox_handler_vf_flr()
1508 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_get_hw_cap()
1510 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; in rvu_mbox_handler_get_hw_cap()
1511 rsp->nix_shaping = hw->cap.nix_shaping; in rvu_mbox_handler_get_hw_cap()
1519 struct rvu *rvu = pci_get_drvdata(mbox->pdev); in rvu_process_mbox_msg()
1522 if (req->sig != OTX2_MBOX_REQ_SIG) in rvu_process_mbox_msg()
1525 switch (req->id) { in rvu_process_mbox_msg()
1540 return -ENOMEM; \ in rvu_process_mbox_msg()
1542 rsp->hdr.id = _id; \ in rvu_process_mbox_msg()
1543 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ in rvu_process_mbox_msg()
1544 rsp->hdr.pcifunc = req->pcifunc; \ in rvu_process_mbox_msg()
1545 rsp->hdr.rc = 0; \ in rvu_process_mbox_msg()
1552 rsp->hdr.rc = err; \ in rvu_process_mbox_msg()
1554 trace_otx2_msg_process(mbox->pdev, _id, err); \ in rvu_process_mbox_msg()
1555 return rsp ? err : -ENOMEM; \ in rvu_process_mbox_msg()
1562 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); in rvu_process_mbox_msg()
1563 return -ENODEV; in rvu_process_mbox_msg()
1569 struct rvu *rvu = mwork->rvu; in __rvu_mbox_handler()
1579 mw = &rvu->afpf_wq_info; in __rvu_mbox_handler()
1582 mw = &rvu->afvf_wq_info; in __rvu_mbox_handler()
1588 devid = mwork - mw->mbox_wrk; in __rvu_mbox_handler()
1589 mbox = &mw->mbox; in __rvu_mbox_handler()
1590 mdev = &mbox->dev[devid]; in __rvu_mbox_handler()
1593 req_hdr = mdev->mbase + mbox->rx_start; in __rvu_mbox_handler()
1594 if (mw->mbox_wrk[devid].num_msgs == 0) in __rvu_mbox_handler()
1597 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); in __rvu_mbox_handler()
1599 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { in __rvu_mbox_handler()
1600 msg = mdev->mbase + offset; in __rvu_mbox_handler()
1605 msg->pcifunc &= in __rvu_mbox_handler()
1607 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); in __rvu_mbox_handler()
1610 msg->pcifunc &= in __rvu_mbox_handler()
1612 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; in __rvu_mbox_handler()
1618 offset = mbox->rx_start + msg->next_msgoff; in __rvu_mbox_handler()
1622 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) in __rvu_mbox_handler()
1623 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", in __rvu_mbox_handler()
1624 err, otx2_mbox_id2name(msg->id), in __rvu_mbox_handler()
1625 msg->id, rvu_get_pf(msg->pcifunc), in __rvu_mbox_handler()
1626 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); in __rvu_mbox_handler()
1628 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", in __rvu_mbox_handler()
1629 err, otx2_mbox_id2name(msg->id), in __rvu_mbox_handler()
1630 msg->id, devid); in __rvu_mbox_handler()
1632 mw->mbox_wrk[devid].num_msgs = 0; in __rvu_mbox_handler()
1654 struct rvu *rvu = mwork->rvu; in __rvu_mbox_up_handler()
1664 mw = &rvu->afpf_wq_info; in __rvu_mbox_up_handler()
1667 mw = &rvu->afvf_wq_info; in __rvu_mbox_up_handler()
1673 devid = mwork - mw->mbox_wrk_up; in __rvu_mbox_up_handler()
1674 mbox = &mw->mbox_up; in __rvu_mbox_up_handler()
1675 mdev = &mbox->dev[devid]; in __rvu_mbox_up_handler()
1677 rsp_hdr = mdev->mbase + mbox->rx_start; in __rvu_mbox_up_handler()
1678 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { in __rvu_mbox_up_handler()
1679 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); in __rvu_mbox_up_handler()
1683 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); in __rvu_mbox_up_handler()
1685 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { in __rvu_mbox_up_handler()
1686 msg = mdev->mbase + offset; in __rvu_mbox_up_handler()
1688 if (msg->id >= MBOX_MSG_MAX) { in __rvu_mbox_up_handler()
1689 dev_err(rvu->dev, in __rvu_mbox_up_handler()
1690 "Mbox msg with unknown ID 0x%x\n", msg->id); in __rvu_mbox_up_handler()
1694 if (msg->sig != OTX2_MBOX_RSP_SIG) { in __rvu_mbox_up_handler()
1695 dev_err(rvu->dev, in __rvu_mbox_up_handler()
1697 msg->sig, msg->id); in __rvu_mbox_up_handler()
1701 switch (msg->id) { in __rvu_mbox_up_handler()
1705 if (msg->rc) in __rvu_mbox_up_handler()
1706 dev_err(rvu->dev, in __rvu_mbox_up_handler()
1708 msg->rc, msg->id); in __rvu_mbox_up_handler()
1712 offset = mbox->rx_start + msg->next_msgoff; in __rvu_mbox_up_handler()
1713 mdev->msgs_acked++; in __rvu_mbox_up_handler()
1715 mw->mbox_wrk_up[devid].up_num_msgs = 0; in __rvu_mbox_up_handler()
1751 reg_base = rvu->afreg_base; in rvu_mbox_init()
1758 reg_base = rvu->pfreg_base; in rvu_mbox_init()
1761 return -EINVAL; in rvu_mbox_init()
1764 mw->mbox_wq = alloc_workqueue(name, in rvu_mbox_init()
1767 if (!mw->mbox_wq) in rvu_mbox_init()
1768 return -ENOMEM; in rvu_mbox_init()
1770 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, in rvu_mbox_init()
1772 if (!mw->mbox_wrk) { in rvu_mbox_init()
1773 err = -ENOMEM; in rvu_mbox_init()
1777 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, in rvu_mbox_init()
1779 if (!mw->mbox_wrk_up) { in rvu_mbox_init()
1780 err = -ENOMEM; in rvu_mbox_init()
1790 dev_err(rvu->dev, "Unable to map mailbox region\n"); in rvu_mbox_init()
1791 err = -ENOMEM; in rvu_mbox_init()
1795 err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num); in rvu_mbox_init()
1799 err = otx2_mbox_init(&mw->mbox_up, hwbase, rvu->pdev, in rvu_mbox_init()
1805 mwork = &mw->mbox_wrk[i]; in rvu_mbox_init()
1806 mwork->rvu = rvu; in rvu_mbox_init()
1807 INIT_WORK(&mwork->work, mbox_handler); in rvu_mbox_init()
1809 mwork = &mw->mbox_wrk_up[i]; in rvu_mbox_init()
1810 mwork->rvu = rvu; in rvu_mbox_init()
1811 INIT_WORK(&mwork->work, mbox_up_handler); in rvu_mbox_init()
1818 destroy_workqueue(mw->mbox_wq); in rvu_mbox_init()
1824 if (mw->mbox_wq) { in rvu_mbox_destroy()
1825 flush_workqueue(mw->mbox_wq); in rvu_mbox_destroy()
1826 destroy_workqueue(mw->mbox_wq); in rvu_mbox_destroy()
1827 mw->mbox_wq = NULL; in rvu_mbox_destroy()
1830 if (mw->mbox.hwbase) in rvu_mbox_destroy()
1831 iounmap((void __iomem *)mw->mbox.hwbase); in rvu_mbox_destroy()
1833 otx2_mbox_destroy(&mw->mbox); in rvu_mbox_destroy()
1834 otx2_mbox_destroy(&mw->mbox_up); in rvu_mbox_destroy()
1847 if (!(intr & BIT_ULL(i - first))) in rvu_queue_work()
1850 mbox = &mw->mbox; in rvu_queue_work()
1851 mdev = &mbox->dev[i]; in rvu_queue_work()
1852 hdr = mdev->mbase + mbox->rx_start; in rvu_queue_work()
1854 /*The hdr->num_msgs is set to zero immediately in the interrupt in rvu_queue_work()
1857 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler in rvu_queue_work()
1862 if (hdr->num_msgs) { in rvu_queue_work()
1863 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; in rvu_queue_work()
1864 hdr->num_msgs = 0; in rvu_queue_work()
1865 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); in rvu_queue_work()
1867 mbox = &mw->mbox_up; in rvu_queue_work()
1868 mdev = &mbox->dev[i]; in rvu_queue_work()
1869 hdr = mdev->mbase + mbox->rx_start; in rvu_queue_work()
1870 if (hdr->num_msgs) { in rvu_queue_work()
1871 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; in rvu_queue_work()
1872 hdr->num_msgs = 0; in rvu_queue_work()
1873 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); in rvu_queue_work()
1881 int vfs = rvu->vfs; in rvu_mbox_intr_handler()
1888 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); in rvu_mbox_intr_handler()
1893 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); in rvu_mbox_intr_handler()
1900 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); in rvu_mbox_intr_handler()
1901 vfs -= 64; in rvu_mbox_intr_handler()
1907 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); in rvu_mbox_intr_handler()
1909 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); in rvu_mbox_intr_handler()
1916 struct rvu_hwinfo *hw = rvu->hw; in rvu_enable_mbox_intr()
1920 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); in rvu_enable_mbox_intr()
1924 INTR_MASK(hw->total_pfs) & ~1ULL); in rvu_enable_mbox_intr()
1933 block = &rvu->hw->block[blkaddr]; in rvu_blklf_teardown()
1935 block->type); in rvu_blklf_teardown()
1944 if (block->addr == BLKADDR_NIX0) in rvu_blklf_teardown()
1945 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); in rvu_blklf_teardown()
1946 else if (block->addr == BLKADDR_NPA) in rvu_blklf_teardown()
1951 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", in rvu_blklf_teardown()
1952 block->addr, lf); in rvu_blklf_teardown()
1959 mutex_lock(&rvu->flr_lock); in __rvu_flr_handler()
1960 /* Reset order should reflect inter-block dependencies: in __rvu_flr_handler()
1972 mutex_unlock(&rvu->flr_lock); in __rvu_flr_handler()
1984 vf = vf - 64; in rvu_afvf_flr_handler()
1995 struct rvu *rvu = flrwork->rvu; in rvu_flr_handler()
2000 pf = flrwork - rvu->flr_wrk; in rvu_flr_handler()
2001 if (pf >= rvu->hw->total_pfs) { in rvu_flr_handler()
2002 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); in rvu_flr_handler()
2037 dev = vf + start_vf + rvu->hw->total_pfs; in rvu_afvf_queue_flr_work()
2038 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); in rvu_afvf_queue_flr_work()
2055 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { in rvu_flr_intr_handler()
2058 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); in rvu_flr_intr_handler()
2070 if (rvu->vfs > 64) in rvu_flr_intr_handler()
2071 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); in rvu_flr_intr_handler()
2123 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { in rvu_me_pf_intr_handler()
2143 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
2147 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
2151 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_unregister_interrupts()
2153 for (irq = 0; irq < rvu->num_vec; irq++) { in rvu_unregister_interrupts()
2154 if (rvu->irq_allocated[irq]) in rvu_unregister_interrupts()
2155 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); in rvu_unregister_interrupts()
2158 pci_free_irq_vectors(rvu->pdev); in rvu_unregister_interrupts()
2159 rvu->num_vec = 0; in rvu_unregister_interrupts()
2164 struct rvu_pfvf *pfvf = &rvu->pf[0]; in rvu_afvf_msix_vectors_num_ok()
2167 pfvf = &rvu->pf[0]; in rvu_afvf_msix_vectors_num_ok()
2174 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && in rvu_afvf_msix_vectors_num_ok()
2182 rvu->num_vec = pci_msix_vec_count(rvu->pdev); in rvu_register_interrupts()
2184 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, in rvu_register_interrupts()
2186 if (!rvu->irq_name) in rvu_register_interrupts()
2187 return -ENOMEM; in rvu_register_interrupts()
2189 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, in rvu_register_interrupts()
2191 if (!rvu->irq_allocated) in rvu_register_interrupts()
2192 return -ENOMEM; in rvu_register_interrupts()
2194 /* Enable MSI-X */ in rvu_register_interrupts()
2195 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, in rvu_register_interrupts()
2196 rvu->num_vec, PCI_IRQ_MSIX); in rvu_register_interrupts()
2198 dev_err(rvu->dev, in rvu_register_interrupts()
2200 rvu->num_vec, ret); in rvu_register_interrupts()
2205 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); in rvu_register_interrupts()
2206 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), in rvu_register_interrupts()
2208 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); in rvu_register_interrupts()
2210 dev_err(rvu->dev, in rvu_register_interrupts()
2215 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; in rvu_register_interrupts()
2221 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], in rvu_register_interrupts()
2223 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), in rvu_register_interrupts()
2225 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], in rvu_register_interrupts()
2228 dev_err(rvu->dev, in rvu_register_interrupts()
2232 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; in rvu_register_interrupts()
2236 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); in rvu_register_interrupts()
2239 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_register_interrupts()
2242 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], in rvu_register_interrupts()
2244 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), in rvu_register_interrupts()
2246 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], in rvu_register_interrupts()
2249 dev_err(rvu->dev, in rvu_register_interrupts()
2252 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; in rvu_register_interrupts()
2256 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); in rvu_register_interrupts()
2259 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); in rvu_register_interrupts()
2262 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); in rvu_register_interrupts()
2273 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); in rvu_register_interrupts()
2274 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
2276 &rvu->irq_name[offset * NAME_SIZE], in rvu_register_interrupts()
2279 dev_err(rvu->dev, in rvu_register_interrupts()
2282 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
2288 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); in rvu_register_interrupts()
2289 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
2291 &rvu->irq_name[offset * NAME_SIZE], in rvu_register_interrupts()
2294 dev_err(rvu->dev, in rvu_register_interrupts()
2297 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
2301 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); in rvu_register_interrupts()
2302 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
2304 &rvu->irq_name[offset * NAME_SIZE], rvu); in rvu_register_interrupts()
2306 dev_err(rvu->dev, in rvu_register_interrupts()
2310 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
2313 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); in rvu_register_interrupts()
2314 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
2316 &rvu->irq_name[offset * NAME_SIZE], rvu); in rvu_register_interrupts()
2318 dev_err(rvu->dev, in rvu_register_interrupts()
2322 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
2326 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); in rvu_register_interrupts()
2327 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
2329 &rvu->irq_name[offset * NAME_SIZE], rvu); in rvu_register_interrupts()
2331 dev_err(rvu->dev, in rvu_register_interrupts()
2335 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
2338 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); in rvu_register_interrupts()
2339 ret = request_irq(pci_irq_vector(rvu->pdev, offset), in rvu_register_interrupts()
2341 &rvu->irq_name[offset * NAME_SIZE], rvu); in rvu_register_interrupts()
2343 dev_err(rvu->dev, in rvu_register_interrupts()
2347 rvu->irq_allocated[offset] = true; in rvu_register_interrupts()
2357 if (rvu->flr_wq) { in rvu_flr_wq_destroy()
2358 flush_workqueue(rvu->flr_wq); in rvu_flr_wq_destroy()
2359 destroy_workqueue(rvu->flr_wq); in rvu_flr_wq_destroy()
2360 rvu->flr_wq = NULL; in rvu_flr_wq_destroy()
2371 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { in rvu_flr_init()
2377 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", in rvu_flr_init()
2380 if (!rvu->flr_wq) in rvu_flr_init()
2381 return -ENOMEM; in rvu_flr_init()
2383 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); in rvu_flr_init()
2384 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, in rvu_flr_init()
2386 if (!rvu->flr_wrk) { in rvu_flr_init()
2387 destroy_workqueue(rvu->flr_wq); in rvu_flr_init()
2388 return -ENOMEM; in rvu_flr_init()
2392 rvu->flr_wrk[dev].rvu = rvu; in rvu_flr_init()
2393 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); in rvu_flr_init()
2396 mutex_init(&rvu->flr_lock); in rvu_flr_init()
2403 int vfs = rvu->vfs; in rvu_disable_afvf_intr()
2412 INTR_MASK(vfs - 64)); in rvu_disable_afvf_intr()
2413 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); in rvu_disable_afvf_intr()
2414 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); in rvu_disable_afvf_intr()
2419 int vfs = rvu->vfs; in rvu_enable_afvf_intr()
2437 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
2439 INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
2441 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
2442 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
2443 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
2451 void __iomem *base; in lbk_get_num_chans() local
2452 int ret = -EIO; in lbk_get_num_chans()
2459 base = pci_ioremap_bar(pdev, 0); in lbk_get_num_chans()
2460 if (!base) in lbk_get_num_chans()
2464 ret = (readq(base + 0x10) >> 32) & 0xffff; in lbk_get_num_chans()
2465 iounmap(base); in lbk_get_num_chans()
2474 struct pci_dev *pdev = rvu->pdev; in rvu_enable_sriov()
2478 dev_warn(&pdev->dev, in rvu_enable_sriov()
2500 rvu->vfs = vfs; in rvu_enable_sriov()
2502 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, in rvu_enable_sriov()
2514 rvu_mbox_destroy(&rvu->afvf_wq_info); in rvu_enable_sriov()
2524 rvu_mbox_destroy(&rvu->afvf_wq_info); in rvu_disable_sriov()
2525 pci_disable_sriov(rvu->pdev); in rvu_disable_sriov()
2532 strscpy(rvu->mkex_pfl_name, in rvu_update_module_params()
2538 struct device *dev = &pdev->dev; in rvu_probe()
2544 return -ENOMEM; in rvu_probe()
2546 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); in rvu_probe()
2547 if (!rvu->hw) { in rvu_probe()
2549 return -ENOMEM; in rvu_probe()
2553 rvu->pdev = pdev; in rvu_probe()
2554 rvu->dev = &pdev->dev; in rvu_probe()
2576 rvu->ptp = ptp_get(); in rvu_probe()
2577 if (IS_ERR(rvu->ptp)) { in rvu_probe()
2578 err = PTR_ERR(rvu->ptp); in rvu_probe()
2579 if (err == -EPROBE_DEFER) in rvu_probe()
2581 rvu->ptp = NULL; in rvu_probe()
2585 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); in rvu_probe()
2586 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); in rvu_probe()
2587 if (!rvu->afreg_base || !rvu->pfreg_base) { in rvu_probe()
2589 err = -ENOMEM; in rvu_probe()
2608 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, in rvu_probe()
2609 rvu->hw->total_pfs, rvu_afpf_mbox_handler, in rvu_probe()
2638 rvu_mbox_destroy(&rvu->afpf_wq_info); in rvu_probe()
2646 ptp_put(rvu->ptp); in rvu_probe()
2653 devm_kfree(&pdev->dev, rvu->hw); in rvu_probe()
2667 rvu_mbox_destroy(&rvu->afpf_wq_info); in rvu_remove()
2672 ptp_put(rvu->ptp); in rvu_remove()
2677 devm_kfree(&pdev->dev, rvu->hw); in rvu_remove()
2678 devm_kfree(&pdev->dev, rvu); in rvu_remove()