Lines Matching full:pe
22 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
26 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
30 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
33 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
35 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]); in mvpp2_prs_hw_write()
38 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
40 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
46 int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe, in mvpp2_prs_init_from_hw() argument
54 memset(pe, 0, sizeof(*pe)); in mvpp2_prs_init_from_hw()
55 pe->index = tid; in mvpp2_prs_init_from_hw()
58 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
60 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_init_from_hw()
62 if (pe->tcam[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_init_from_hw()
66 pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
69 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
71 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
101 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
103 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
104 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
105 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
106 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
110 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
114 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port)); in mvpp2_prs_tcam_port_set()
116 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port)); in mvpp2_prs_tcam_port_set()
120 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
123 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT(MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
124 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
125 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(~ports & MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
129 unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
131 return (~pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] >> 24) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
135 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
141 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(0xff << pos); in mvpp2_prs_tcam_data_byte_set()
142 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(MVPP2_PRS_TCAM_EN(0xff) << pos); in mvpp2_prs_tcam_data_byte_set()
143 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= byte << pos; in mvpp2_prs_tcam_data_byte_set()
144 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= MVPP2_PRS_TCAM_EN(enable << pos); in mvpp2_prs_tcam_data_byte_set()
148 void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
154 *byte = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> pos) & 0xff; in mvpp2_prs_tcam_data_byte_get()
155 *enable = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> (pos + 16)) & 0xff; in mvpp2_prs_tcam_data_byte_get()
159 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, in mvpp2_prs_tcam_data_cmp() argument
164 tcam_data = pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] & 0xffff; in mvpp2_prs_tcam_data_cmp()
169 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_ai_update() argument
179 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i); in mvpp2_prs_tcam_ai_update()
181 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i); in mvpp2_prs_tcam_ai_update()
184 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= MVPP2_PRS_TCAM_AI_EN(enable); in mvpp2_prs_tcam_ai_update()
188 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_ai_get() argument
190 return pe->tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK; in mvpp2_prs_tcam_ai_get()
194 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
197 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
198 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
202 static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_vid() argument
205 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf); in mvpp2_prs_match_vid()
206 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff); in mvpp2_prs_match_vid()
210 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
213 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num))); in mvpp2_prs_sram_bits_set()
217 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
220 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num))); in mvpp2_prs_sram_bits_clear()
224 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
234 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_OFFS + i, in mvpp2_prs_sram_ri_update()
237 mvpp2_prs_sram_bits_clear(pe, in mvpp2_prs_sram_ri_update()
241 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
246 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ri_get() argument
248 return pe->sram[MVPP2_PRS_SRAM_RI_WORD]; in mvpp2_prs_sram_ri_get()
252 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
262 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_OFFS + i, in mvpp2_prs_sram_ai_update()
265 mvpp2_prs_sram_bits_clear(pe, in mvpp2_prs_sram_ai_update()
269 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
274 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
281 bits = (pe->sram[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
282 (pe->sram[ai_off + 1] << (32 - ai_shift)); in mvpp2_prs_sram_ai_get()
290 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
295 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
297 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
303 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
308 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
311 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
315 pe->sram[MVPP2_BIT_TO_WORD(MVPP2_PRS_SRAM_SHIFT_OFFS)] |= in mvpp2_prs_sram_shift_set()
319 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
321 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
324 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
330 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
336 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
339 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
343 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
345 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
349 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
351 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
354 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
356 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
360 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
366 struct mvpp2_prs_entry pe; in mvpp2_prs_flow_find() local
377 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_flow_find()
378 bits = mvpp2_prs_sram_ai_get(&pe); in mvpp2_prs_flow_find()
411 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
415 mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL); in mvpp2_prs_mac_drop_all_set()
418 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_drop_all_set()
419 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
420 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
423 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
426 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
427 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
430 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
433 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
437 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
439 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
446 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_promisc_set() local
463 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_promisc_set()
465 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_promisc_set()
466 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
467 pe.index = tid; in mvpp2_prs_mac_promisc_set()
470 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_promisc_set()
473 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK); in mvpp2_prs_mac_promisc_set()
476 mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match, in mvpp2_prs_mac_promisc_set()
480 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_promisc_set()
484 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_promisc_set()
487 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
491 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
493 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_promisc_set()
500 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_set() local
513 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_dsa_tag_set()
516 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_tag_set()
517 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
518 pe.index = tid; in mvpp2_prs_dsa_tag_set()
521 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
525 mvpp2_prs_tcam_data_byte_set(&pe, 0, in mvpp2_prs_dsa_tag_set()
531 mvpp2_prs_sram_ai_update(&pe, 1, in mvpp2_prs_dsa_tag_set()
534 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_set()
538 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_dsa_tag_set()
541 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_dsa_tag_set()
544 mvpp2_prs_sram_shift_set(&pe, shift, in mvpp2_prs_dsa_tag_set()
548 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_set()
550 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_set()
554 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_dsa_tag_set()
558 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
560 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_set()
567 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_ethertype_set() local
584 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_dsa_tag_ethertype_set()
587 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_tag_ethertype_set()
588 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
589 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
592 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); in mvpp2_prs_dsa_tag_ethertype_set()
593 mvpp2_prs_match_etype(&pe, 2, 0); in mvpp2_prs_dsa_tag_ethertype_set()
595 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, in mvpp2_prs_dsa_tag_ethertype_set()
598 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, in mvpp2_prs_dsa_tag_ethertype_set()
602 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
606 mvpp2_prs_tcam_data_byte_set(&pe, in mvpp2_prs_dsa_tag_ethertype_set()
611 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_ethertype_set()
614 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_ethertype_set()
617 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_ethertype_set()
619 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_ethertype_set()
622 mvpp2_prs_tcam_port_map_set(&pe, port_mask); in mvpp2_prs_dsa_tag_ethertype_set()
626 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
628 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
634 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_find() local
647 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vlan_find()
648 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid); in mvpp2_prs_vlan_find()
653 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_vlan_find()
657 ai_bits = mvpp2_prs_tcam_ai_get(&pe); in mvpp2_prs_vlan_find()
676 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_add() local
680 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_add()
700 mvpp2_prs_init_from_hw(priv, &pe, tid_aux); in mvpp2_prs_vlan_add()
701 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_vlan_add()
710 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_add()
711 pe.index = tid; in mvpp2_prs_vlan_add()
712 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
714 mvpp2_prs_match_etype(&pe, 0, tpid); in mvpp2_prs_vlan_add()
717 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vlan_add()
720 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
723 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_vlan_add()
727 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE, in mvpp2_prs_vlan_add()
730 mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
732 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
734 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vlan_add()
737 mvpp2_prs_tcam_port_map_set(&pe, port_map); in mvpp2_prs_vlan_add()
739 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_add()
761 struct mvpp2_prs_entry pe; in mvpp2_prs_double_vlan_find() local
774 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_double_vlan_find()
776 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid1) && in mvpp2_prs_double_vlan_find()
777 mvpp2_prs_tcam_data_cmp(&pe, 4, tpid2); in mvpp2_prs_double_vlan_find()
782 ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK; in mvpp2_prs_double_vlan_find()
796 struct mvpp2_prs_entry pe; in mvpp2_prs_double_vlan_add() local
798 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_double_vlan_add()
823 mvpp2_prs_init_from_hw(priv, &pe, tid_aux); in mvpp2_prs_double_vlan_add()
824 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_double_vlan_add()
834 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_double_vlan_add()
835 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
836 pe.index = tid; in mvpp2_prs_double_vlan_add()
840 mvpp2_prs_match_etype(&pe, 0, tpid1); in mvpp2_prs_double_vlan_add()
841 mvpp2_prs_match_etype(&pe, 4, tpid2); in mvpp2_prs_double_vlan_add()
843 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
845 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_double_vlan_add()
847 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_double_vlan_add()
849 mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_double_vlan_add()
852 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
854 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_double_vlan_add()
858 mvpp2_prs_tcam_port_map_set(&pe, port_map); in mvpp2_prs_double_vlan_add()
859 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_double_vlan_add()
868 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_proto() local
881 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_proto()
882 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
883 pe.index = tid; in mvpp2_prs_ip4_proto()
886 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
887 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_proto()
889 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_proto()
892 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_proto()
894 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); in mvpp2_prs_ip4_proto()
896 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, in mvpp2_prs_ip4_proto()
898 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, in mvpp2_prs_ip4_proto()
901 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
902 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_proto()
904 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_proto()
907 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
908 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
916 pe.index = tid; in mvpp2_prs_ip4_proto()
918 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_ip4_proto()
919 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_ip4_proto()
920 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip4_proto()
922 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE, in mvpp2_prs_ip4_proto()
925 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0); in mvpp2_prs_ip4_proto()
926 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0); in mvpp2_prs_ip4_proto()
929 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
930 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
938 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_cast() local
946 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_cast()
947 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
948 pe.index = tid; in mvpp2_prs_ip4_cast()
952 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, in mvpp2_prs_ip4_cast()
954 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip4_cast()
959 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); in mvpp2_prs_ip4_cast()
960 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); in mvpp2_prs_ip4_cast()
961 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); in mvpp2_prs_ip4_cast()
962 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); in mvpp2_prs_ip4_cast()
963 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, in mvpp2_prs_ip4_cast()
971 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_cast()
972 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_cast()
974 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_cast()
977 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_cast()
980 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
981 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_cast()
990 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_proto() local
1002 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_proto()
1003 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1004 pe.index = tid; in mvpp2_prs_ip6_proto()
1007 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_proto()
1008 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_proto()
1009 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip6_proto()
1010 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_proto()
1014 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip6_proto()
1015 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_proto()
1018 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_proto()
1021 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1022 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_proto()
1030 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_cast() local
1041 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_cast()
1042 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1043 pe.index = tid; in mvpp2_prs_ip6_cast()
1046 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1047 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip6_cast()
1049 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_cast()
1052 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_cast()
1054 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, in mvpp2_prs_ip6_cast()
1056 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_cast()
1058 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_cast()
1061 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1062 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_cast()
1097 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
1101 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_def_flow_init()
1102 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1103 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1106 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
1109 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
1110 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
1113 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1114 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
1121 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
1123 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mh_init()
1125 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
1126 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1127 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
1129 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
1132 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
1135 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1136 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
1144 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
1146 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_init()
1149 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
1150 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1152 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
1154 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
1155 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
1158 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
1161 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1162 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
1173 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_init() local
1206 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_init()
1207 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_init()
1208 pe.index = MVPP2_PE_DSA_DEFAULT; in mvpp2_prs_dsa_init()
1209 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_init()
1212 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_dsa_init()
1213 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_dsa_init()
1216 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_dsa_init()
1219 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_dsa_init()
1221 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_init()
1227 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_init() local
1229 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_init()
1232 pe.index = MVPP2_PE_VID_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1233 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1235 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT); in mvpp2_prs_vid_init()
1238 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_vid_init()
1242 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_init()
1244 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_init()
1247 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vid_init()
1250 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1251 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_init()
1254 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_init()
1257 pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1258 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1260 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT, in mvpp2_prs_vid_init()
1264 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN, in mvpp2_prs_vid_init()
1268 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_init()
1270 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_init()
1273 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vid_init()
1276 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1277 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_init()
1283 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
1292 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1293 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1294 pe.index = tid; in mvpp2_prs_etype_init()
1296 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); in mvpp2_prs_etype_init()
1298 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
1300 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
1301 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1305 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1306 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1307 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1308 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1310 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1318 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1319 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1320 pe.index = tid; in mvpp2_prs_etype_init()
1322 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); in mvpp2_prs_etype_init()
1325 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1326 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1327 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1330 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1335 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1336 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1337 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1338 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1340 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1348 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1349 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1350 pe.index = tid; in mvpp2_prs_etype_init()
1352 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
1355 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1356 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1357 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1362 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1367 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1368 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1369 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1370 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1374 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1382 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1383 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1384 pe.index = tid; in mvpp2_prs_etype_init()
1386 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); in mvpp2_prs_etype_init()
1387 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
1392 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
1393 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1396 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_etype_init()
1399 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1404 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1405 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1406 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1407 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1409 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1417 pe.index = tid; in mvpp2_prs_etype_init()
1419 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
1424 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_etype_init()
1425 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_etype_init()
1426 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
1430 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1431 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1432 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1433 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
1435 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1443 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1444 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1445 pe.index = tid; in mvpp2_prs_etype_init()
1447 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); in mvpp2_prs_etype_init()
1450 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
1453 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
1454 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1457 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1461 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1462 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1463 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1464 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1466 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1469 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
1470 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1471 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
1474 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
1477 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1478 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1479 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1482 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1487 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1488 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1489 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1490 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1492 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1506 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_init() local
1540 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_init()
1541 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1542 pe.index = MVPP2_PE_VLAN_DBL; in mvpp2_prs_vlan_init()
1544 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vlan_init()
1547 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_init()
1548 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_vlan_init()
1551 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_vlan_init()
1554 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
1557 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1558 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
1561 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_init()
1562 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1563 pe.index = MVPP2_PE_VLAN_NONE; in mvpp2_prs_vlan_init()
1565 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
1566 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_vlan_init()
1570 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
1573 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1574 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
1582 struct mvpp2_prs_entry pe; in mvpp2_prs_pppoe_init() local
1591 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1592 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1593 pe.index = tid; in mvpp2_prs_pppoe_init()
1595 mvpp2_prs_match_etype(&pe, 0, PPP_IP); in mvpp2_prs_pppoe_init()
1597 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_pppoe_init()
1598 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_pppoe_init()
1601 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
1604 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1609 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1610 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1618 pe.index = tid; in mvpp2_prs_pppoe_init()
1620 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_pppoe_init()
1626 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_pppoe_init()
1627 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_pppoe_init()
1628 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_pppoe_init()
1632 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1633 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1641 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1642 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1643 pe.index = tid; in mvpp2_prs_pppoe_init()
1645 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); in mvpp2_prs_pppoe_init()
1647 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_pppoe_init()
1648 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_pppoe_init()
1651 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
1654 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1659 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1660 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1668 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1669 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1670 pe.index = tid; in mvpp2_prs_pppoe_init()
1672 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_pppoe_init()
1676 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_pppoe_init()
1677 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_pppoe_init()
1679 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1684 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1685 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1693 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_init() local
1726 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_init()
1727 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1728 pe.index = MVPP2_PE_IP4_PROTO_UN; in mvpp2_prs_ip4_init()
1731 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1732 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_init()
1734 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_init()
1737 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
1739 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip4_init()
1742 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
1744 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
1747 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1748 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
1751 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_init()
1752 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1753 pe.index = MVPP2_PE_IP4_ADDR_UN; in mvpp2_prs_ip4_init()
1756 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_init()
1757 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_init()
1758 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip4_init()
1761 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
1764 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
1767 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1768 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
1776 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_init() local
1819 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_init()
1820 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1821 pe.index = tid; in mvpp2_prs_ip6_init()
1824 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1825 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1826 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | in mvpp2_prs_ip6_init()
1831 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); in mvpp2_prs_ip6_init()
1832 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1836 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1837 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1840 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_init()
1841 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1842 pe.index = MVPP2_PE_IP6_PROTO_UN; in mvpp2_prs_ip6_init()
1845 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1846 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1847 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
1850 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_init()
1854 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1857 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1860 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1861 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1864 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
1865 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1866 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; in mvpp2_prs_ip6_init()
1869 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1870 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1871 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
1874 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1877 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1880 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1881 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1884 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
1885 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1886 pe.index = MVPP2_PE_IP6_ADDR_UN; in mvpp2_prs_ip6_init()
1889 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1890 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip6_init()
1892 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1895 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_init()
1897 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_init()
1899 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1902 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1903 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1912 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_range_find() local
1923 mvpp2_prs_init_from_hw(port->priv, &pe, tid); in mvpp2_prs_vid_range_find()
1925 mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]); in mvpp2_prs_vid_range_find()
1926 mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]); in mvpp2_prs_vid_range_find()
1947 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_entry_add() local
1950 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_entry_add()
1973 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
1974 pe.index = tid; in mvpp2_prs_vid_entry_add()
1977 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_vid_entry_add()
1979 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vid_entry_add()
1983 mvpp2_prs_tcam_port_set(&pe, port->id, true); in mvpp2_prs_vid_entry_add()
1986 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_entry_add()
1989 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_vid_entry_add()
1992 mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid); in mvpp2_prs_vid_entry_add()
1995 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_entry_add()
1998 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
1999 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_entry_add()
2054 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_enable_filtering() local
2059 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_enable_filtering()
2061 pe.index = tid; in mvpp2_prs_vid_enable_filtering()
2069 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2072 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_vid_enable_filtering()
2075 mvpp2_prs_tcam_port_set(&pe, port->id, true); in mvpp2_prs_vid_enable_filtering()
2078 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_enable_filtering()
2081 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_vid_enable_filtering()
2084 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_vid_enable_filtering()
2088 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_enable_filtering()
2091 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2092 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_enable_filtering()
2163 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2170 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2186 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_da_range_find() local
2199 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_da_range_find()
2200 entry_pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_da_range_find()
2202 if (mvpp2_prs_mac_range_equals(&pe, da, mask) && in mvpp2_prs_mac_da_range_find()
2216 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_da_accept() local
2219 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_da_accept()
2238 pe.index = tid; in mvpp2_prs_mac_da_accept()
2241 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_da_accept()
2243 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_da_accept()
2246 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2249 mvpp2_prs_tcam_port_set(&pe, port->id, add); in mvpp2_prs_mac_da_accept()
2252 pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_da_accept()
2257 mvpp2_prs_hw_inv(priv, pe.index); in mvpp2_prs_mac_da_accept()
2258 priv->prs_shadow[pe.index].valid = false; in mvpp2_prs_mac_da_accept()
2263 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_da_accept()
2268 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff); in mvpp2_prs_mac_da_accept()
2282 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2284 mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2288 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_da_accept()
2292 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
2293 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2294 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_da_accept()
2323 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_del_all() local
2336 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_del_all()
2338 pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_del_all()
2346 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], in mvpp2_prs_mac_del_all()
2413 struct mvpp2_prs_entry pe; in mvpp2_prs_add_flow() local
2417 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_add_flow()
2425 pe.index = tid; in mvpp2_prs_add_flow()
2430 mvpp2_prs_sram_ai_update(&pe, flow, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_add_flow()
2431 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_add_flow()
2434 mvpp2_prs_tcam_data_byte_set(&pe, i, ri_byte[i], in mvpp2_prs_add_flow()
2438 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2439 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2440 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_add_flow()
2441 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_add_flow()
2449 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow() local
2452 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_def_flow()
2465 pe.index = tid; in mvpp2_prs_def_flow()
2468 mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2469 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
2472 mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2474 mvpp2_prs_init_from_hw(port->priv, &pe, tid); in mvpp2_prs_def_flow()
2477 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2478 mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id)); in mvpp2_prs_def_flow()
2479 mvpp2_prs_hw_write(port->priv, &pe); in mvpp2_prs_def_flow()