marvell/mvpp2/mvpp2.h

1 /* SPDX-License-Identifier: GPL-2.0 */
346 /* Packet Processor per-port counters */
407 /* Per-port registers */
472 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
473  * relative to port->base.
509 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */
513 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
583 	(((index) < (q)->last_desc) ? ((index) + 1) : 0)
692 /* Maximum number of T-CONTs of PON port */
729 #define MVPP2_TX_DESC_ALIGN		(MVPP2_DESC_ALIGNED_SIZE - 1)
745 	(MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
747 	(MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
760 	((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE)
762 #define MVPP2_MAX_RX_BUF_SIZE	(PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM)
771 /* There are 7 supported high-level flows */
849 #define MVPP2_BM_POOL_SIZE_MAX		(16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
959 	/* Are we using page_pool with per-cpu pools? */
1012 /* Per-CPU port control */
1040 	/* Index of the C2 TCAM entry handling this rule */
1049 	/* TCAM key and mask for C2-based steering. These fields should be
1086 	/* Per-port registers' base address */
1100 	/* Per-CPU port control */
1119 	/* Per-port work and its lock to gather hardware statistics */
1280 /* Per-CPU Tx queue control */
1325 	/* Per-CPU control of physical Tx queues */
1344 	/* RX queue number, in the range 0-31 for physical RXQs */
1377 	/* Pool number in the range 0-7 */
1402 	((addr) >= (txq_pcpu)->tso_headers_dma && \
1403 	 (addr) < (txq_pcpu)->tso_headers_dma + \
1404 	 (txq_pcpu)->size * TSO_HEADER_SIZE)
1440 	return -1;  in mvpp22_tai_ptp_clock_index()
1446 	return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;  in mvpp22_rx_hwtstamping()