Lines Matching full:hw
13 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
14 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
15 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
16 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
17 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
18 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
20 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
21 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
22 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
23 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
25 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
26 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
27 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
29 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
31 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
33 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
43 * @hw: pointer to hardware structure
49 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) in ixgbe_device_supports_autoneg_fc() argument
55 switch (hw->phy.media_type) { in ixgbe_device_supports_autoneg_fc()
58 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
64 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_device_supports_autoneg_fc()
74 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) in ixgbe_device_supports_autoneg_fc()
81 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
101 hw_dbg(hw, "Device %x does not support flow control autoneg\n", in ixgbe_device_supports_autoneg_fc()
102 hw->device_id); in ixgbe_device_supports_autoneg_fc()
109 * @hw: pointer to hardware structure
113 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) in ixgbe_setup_fc_generic() argument
124 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { in ixgbe_setup_fc_generic()
125 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); in ixgbe_setup_fc_generic()
133 if (hw->fc.requested_mode == ixgbe_fc_default) in ixgbe_setup_fc_generic()
134 hw->fc.requested_mode = ixgbe_fc_full; in ixgbe_setup_fc_generic()
138 * HW will be able to do fc autoneg once the cable is plugged in. If in ixgbe_setup_fc_generic()
141 switch (hw->phy.media_type) { in ixgbe_setup_fc_generic()
144 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); in ixgbe_setup_fc_generic()
150 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_setup_fc_generic()
154 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc_generic()
171 switch (hw->fc.requested_mode) { in ixgbe_setup_fc_generic()
175 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
178 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
188 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
191 } else if (hw->phy.media_type == ixgbe_media_type_copper) { in ixgbe_setup_fc_generic()
209 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
212 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
216 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_setup_fc_generic()
220 if (hw->mac.type != ixgbe_mac_X540) { in ixgbe_setup_fc_generic()
225 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); in ixgbe_setup_fc_generic()
226 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); in ixgbe_setup_fc_generic()
229 if (hw->fc.strict_ieee) in ixgbe_setup_fc_generic()
232 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); in ixgbe_setup_fc_generic()
233 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); in ixgbe_setup_fc_generic()
241 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
246 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); in ixgbe_setup_fc_generic()
250 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && in ixgbe_setup_fc_generic()
251 ixgbe_device_supports_autoneg_fc(hw)) { in ixgbe_setup_fc_generic()
252 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc_generic()
256 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); in ixgbe_setup_fc_generic()
262 * @hw: pointer to hardware structure
269 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) in ixgbe_start_hw_generic() argument
276 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
279 hw->phy.ops.identify(hw); in ixgbe_start_hw_generic()
282 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
285 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
288 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); in ixgbe_start_hw_generic()
290 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); in ixgbe_start_hw_generic()
291 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_generic()
294 if (hw->mac.ops.setup_fc) { in ixgbe_start_hw_generic()
295 ret_val = hw->mac.ops.setup_fc(hw); in ixgbe_start_hw_generic()
301 switch (hw->mac.type) { in ixgbe_start_hw_generic()
305 hw->mac.ops.get_device_caps(hw, &device_caps); in ixgbe_start_hw_generic()
307 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
309 hw->need_crosstalk_fix = true; in ixgbe_start_hw_generic()
312 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
317 hw->adapter_stopped = false; in ixgbe_start_hw_generic()
324 * @hw: pointer to hw structure
332 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) in ixgbe_start_hw_gen2() argument
337 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_start_hw_gen2()
338 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); in ixgbe_start_hw_gen2()
339 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); in ixgbe_start_hw_gen2()
341 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_gen2()
348 * @hw: pointer to hardware structure
356 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) in ixgbe_init_hw_generic() argument
361 status = hw->mac.ops.reset_hw(hw); in ixgbe_init_hw_generic()
364 /* Start the HW */ in ixgbe_init_hw_generic()
365 status = hw->mac.ops.start_hw(hw); in ixgbe_init_hw_generic()
369 if (hw->mac.ops.init_led_link_act) in ixgbe_init_hw_generic()
370 hw->mac.ops.init_led_link_act(hw); in ixgbe_init_hw_generic()
377 * @hw: pointer to hardware structure
382 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) in ixgbe_clear_hw_cntrs_generic() argument
386 IXGBE_READ_REG(hw, IXGBE_CRCERRS); in ixgbe_clear_hw_cntrs_generic()
387 IXGBE_READ_REG(hw, IXGBE_ILLERRC); in ixgbe_clear_hw_cntrs_generic()
388 IXGBE_READ_REG(hw, IXGBE_ERRBC); in ixgbe_clear_hw_cntrs_generic()
389 IXGBE_READ_REG(hw, IXGBE_MSPDC); in ixgbe_clear_hw_cntrs_generic()
391 IXGBE_READ_REG(hw, IXGBE_MPC(i)); in ixgbe_clear_hw_cntrs_generic()
393 IXGBE_READ_REG(hw, IXGBE_MLFC); in ixgbe_clear_hw_cntrs_generic()
394 IXGBE_READ_REG(hw, IXGBE_MRFC); in ixgbe_clear_hw_cntrs_generic()
395 IXGBE_READ_REG(hw, IXGBE_RLEC); in ixgbe_clear_hw_cntrs_generic()
396 IXGBE_READ_REG(hw, IXGBE_LXONTXC); in ixgbe_clear_hw_cntrs_generic()
397 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); in ixgbe_clear_hw_cntrs_generic()
398 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
399 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); in ixgbe_clear_hw_cntrs_generic()
400 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); in ixgbe_clear_hw_cntrs_generic()
402 IXGBE_READ_REG(hw, IXGBE_LXONRXC); in ixgbe_clear_hw_cntrs_generic()
403 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); in ixgbe_clear_hw_cntrs_generic()
407 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); in ixgbe_clear_hw_cntrs_generic()
408 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); in ixgbe_clear_hw_cntrs_generic()
409 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
410 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
411 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
413 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); in ixgbe_clear_hw_cntrs_generic()
414 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); in ixgbe_clear_hw_cntrs_generic()
417 if (hw->mac.type >= ixgbe_mac_82599EB) in ixgbe_clear_hw_cntrs_generic()
419 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); in ixgbe_clear_hw_cntrs_generic()
420 IXGBE_READ_REG(hw, IXGBE_PRC64); in ixgbe_clear_hw_cntrs_generic()
421 IXGBE_READ_REG(hw, IXGBE_PRC127); in ixgbe_clear_hw_cntrs_generic()
422 IXGBE_READ_REG(hw, IXGBE_PRC255); in ixgbe_clear_hw_cntrs_generic()
423 IXGBE_READ_REG(hw, IXGBE_PRC511); in ixgbe_clear_hw_cntrs_generic()
424 IXGBE_READ_REG(hw, IXGBE_PRC1023); in ixgbe_clear_hw_cntrs_generic()
425 IXGBE_READ_REG(hw, IXGBE_PRC1522); in ixgbe_clear_hw_cntrs_generic()
426 IXGBE_READ_REG(hw, IXGBE_GPRC); in ixgbe_clear_hw_cntrs_generic()
427 IXGBE_READ_REG(hw, IXGBE_BPRC); in ixgbe_clear_hw_cntrs_generic()
428 IXGBE_READ_REG(hw, IXGBE_MPRC); in ixgbe_clear_hw_cntrs_generic()
429 IXGBE_READ_REG(hw, IXGBE_GPTC); in ixgbe_clear_hw_cntrs_generic()
430 IXGBE_READ_REG(hw, IXGBE_GORCL); in ixgbe_clear_hw_cntrs_generic()
431 IXGBE_READ_REG(hw, IXGBE_GORCH); in ixgbe_clear_hw_cntrs_generic()
432 IXGBE_READ_REG(hw, IXGBE_GOTCL); in ixgbe_clear_hw_cntrs_generic()
433 IXGBE_READ_REG(hw, IXGBE_GOTCH); in ixgbe_clear_hw_cntrs_generic()
434 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_clear_hw_cntrs_generic()
436 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); in ixgbe_clear_hw_cntrs_generic()
437 IXGBE_READ_REG(hw, IXGBE_RUC); in ixgbe_clear_hw_cntrs_generic()
438 IXGBE_READ_REG(hw, IXGBE_RFC); in ixgbe_clear_hw_cntrs_generic()
439 IXGBE_READ_REG(hw, IXGBE_ROC); in ixgbe_clear_hw_cntrs_generic()
440 IXGBE_READ_REG(hw, IXGBE_RJC); in ixgbe_clear_hw_cntrs_generic()
441 IXGBE_READ_REG(hw, IXGBE_MNGPRC); in ixgbe_clear_hw_cntrs_generic()
442 IXGBE_READ_REG(hw, IXGBE_MNGPDC); in ixgbe_clear_hw_cntrs_generic()
443 IXGBE_READ_REG(hw, IXGBE_MNGPTC); in ixgbe_clear_hw_cntrs_generic()
444 IXGBE_READ_REG(hw, IXGBE_TORL); in ixgbe_clear_hw_cntrs_generic()
445 IXGBE_READ_REG(hw, IXGBE_TORH); in ixgbe_clear_hw_cntrs_generic()
446 IXGBE_READ_REG(hw, IXGBE_TPR); in ixgbe_clear_hw_cntrs_generic()
447 IXGBE_READ_REG(hw, IXGBE_TPT); in ixgbe_clear_hw_cntrs_generic()
448 IXGBE_READ_REG(hw, IXGBE_PTC64); in ixgbe_clear_hw_cntrs_generic()
449 IXGBE_READ_REG(hw, IXGBE_PTC127); in ixgbe_clear_hw_cntrs_generic()
450 IXGBE_READ_REG(hw, IXGBE_PTC255); in ixgbe_clear_hw_cntrs_generic()
451 IXGBE_READ_REG(hw, IXGBE_PTC511); in ixgbe_clear_hw_cntrs_generic()
452 IXGBE_READ_REG(hw, IXGBE_PTC1023); in ixgbe_clear_hw_cntrs_generic()
453 IXGBE_READ_REG(hw, IXGBE_PTC1522); in ixgbe_clear_hw_cntrs_generic()
454 IXGBE_READ_REG(hw, IXGBE_MPTC); in ixgbe_clear_hw_cntrs_generic()
455 IXGBE_READ_REG(hw, IXGBE_BPTC); in ixgbe_clear_hw_cntrs_generic()
457 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); in ixgbe_clear_hw_cntrs_generic()
458 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); in ixgbe_clear_hw_cntrs_generic()
459 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
460 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); in ixgbe_clear_hw_cntrs_generic()
461 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); in ixgbe_clear_hw_cntrs_generic()
462 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); in ixgbe_clear_hw_cntrs_generic()
463 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); in ixgbe_clear_hw_cntrs_generic()
464 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); in ixgbe_clear_hw_cntrs_generic()
466 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); in ixgbe_clear_hw_cntrs_generic()
467 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); in ixgbe_clear_hw_cntrs_generic()
471 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { in ixgbe_clear_hw_cntrs_generic()
472 if (hw->phy.id == 0) in ixgbe_clear_hw_cntrs_generic()
473 hw->phy.ops.identify(hw); in ixgbe_clear_hw_cntrs_generic()
474 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
475 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
476 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
477 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
485 * @hw: pointer to hardware structure
491 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, in ixgbe_read_pba_string_generic() argument
501 hw_dbg(hw, "PBA string buffer was null\n"); in ixgbe_read_pba_string_generic()
505 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); in ixgbe_read_pba_string_generic()
507 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
511 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); in ixgbe_read_pba_string_generic()
513 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
523 hw_dbg(hw, "NVM PBA number is not stored as string\n"); in ixgbe_read_pba_string_generic()
527 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
557 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); in ixgbe_read_pba_string_generic()
559 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
564 hw_dbg(hw, "NVM PBA number section invalid length\n"); in ixgbe_read_pba_string_generic()
570 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
579 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); in ixgbe_read_pba_string_generic()
581 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
594 * @hw: pointer to hardware structure
601 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) in ixgbe_get_mac_addr_generic() argument
607 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); in ixgbe_get_mac_addr_generic()
608 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); in ixgbe_get_mac_addr_generic()
651 * @hw: pointer to hardware structure
655 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) in ixgbe_get_bus_info_generic() argument
659 hw->bus.type = ixgbe_bus_type_pci_express; in ixgbe_get_bus_info_generic()
662 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); in ixgbe_get_bus_info_generic()
664 hw->bus.width = ixgbe_convert_bus_width(link_status); in ixgbe_get_bus_info_generic()
665 hw->bus.speed = ixgbe_convert_bus_speed(link_status); in ixgbe_get_bus_info_generic()
667 hw->mac.ops.set_lan_id(hw); in ixgbe_get_bus_info_generic()
674 * @hw: pointer to the HW structure
679 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) in ixgbe_set_lan_id_multi_port_pcie() argument
681 struct ixgbe_bus_info *bus = &hw->bus; in ixgbe_set_lan_id_multi_port_pcie()
685 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); in ixgbe_set_lan_id_multi_port_pcie()
690 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); in ixgbe_set_lan_id_multi_port_pcie()
695 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { in ixgbe_set_lan_id_multi_port_pcie()
696 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); in ixgbe_set_lan_id_multi_port_pcie()
704 * @hw: pointer to hardware structure
711 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) in ixgbe_stop_adapter_generic() argument
720 hw->adapter_stopped = true; in ixgbe_stop_adapter_generic()
723 hw->mac.ops.disable_rx(hw); in ixgbe_stop_adapter_generic()
726 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); in ixgbe_stop_adapter_generic()
729 IXGBE_READ_REG(hw, IXGBE_EICR); in ixgbe_stop_adapter_generic()
732 for (i = 0; i < hw->mac.max_tx_queues; i++) in ixgbe_stop_adapter_generic()
733 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); in ixgbe_stop_adapter_generic()
736 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_stop_adapter_generic()
737 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); in ixgbe_stop_adapter_generic()
740 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); in ixgbe_stop_adapter_generic()
744 IXGBE_WRITE_FLUSH(hw); in ixgbe_stop_adapter_generic()
751 return ixgbe_disable_pcie_master(hw); in ixgbe_stop_adapter_generic()
756 * @hw: pointer to hardware structure
761 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) in ixgbe_init_led_link_act_generic() argument
763 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_led_link_act_generic()
767 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_init_led_link_act_generic()
783 switch (hw->mac.type) { in ixgbe_init_led_link_act_generic()
799 * @hw: pointer to hardware structure
802 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_on_generic() argument
804 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_on_generic()
812 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_on_generic()
813 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_on_generic()
820 * @hw: pointer to hardware structure
823 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_off_generic() argument
825 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_off_generic()
833 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_off_generic()
834 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_off_generic()
841 * @hw: pointer to hardware structure
846 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) in ixgbe_init_eeprom_params_generic() argument
848 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_eeprom_params_generic()
864 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_init_eeprom_params_generic()
882 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", in ixgbe_init_eeprom_params_generic()
891 * @hw: pointer to hardware structure
898 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang_generic() argument
904 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_buffer_bit_bang_generic()
909 if (offset + words > hw->eeprom.word_size) in ixgbe_write_eeprom_buffer_bit_bang_generic()
916 if ((hw->eeprom.word_page_size == 0) && in ixgbe_write_eeprom_buffer_bit_bang_generic()
918 ixgbe_detect_eeprom_page_size_generic(hw, offset); in ixgbe_write_eeprom_buffer_bit_bang_generic()
928 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_write_eeprom_buffer_bit_bang_generic()
940 * @hw: pointer to hardware structure
948 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang() argument
958 status = ixgbe_acquire_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
962 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_write_eeprom_buffer_bit_bang()
963 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
968 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
971 ixgbe_shift_out_eeprom_bits(hw, in ixgbe_write_eeprom_buffer_bit_bang()
975 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
980 if ((hw->eeprom.address_bits == 8) && in ixgbe_write_eeprom_buffer_bit_bang()
985 ixgbe_shift_out_eeprom_bits(hw, write_opcode, in ixgbe_write_eeprom_buffer_bit_bang()
987 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_write_eeprom_buffer_bit_bang()
988 hw->eeprom.address_bits); in ixgbe_write_eeprom_buffer_bit_bang()
990 page_size = hw->eeprom.word_page_size; in ixgbe_write_eeprom_buffer_bit_bang()
996 ixgbe_shift_out_eeprom_bits(hw, word, 16); in ixgbe_write_eeprom_buffer_bit_bang()
1007 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1011 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1018 * @hw: pointer to hardware structure
1025 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eeprom_generic() argument
1027 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_generic()
1029 if (offset >= hw->eeprom.word_size) in ixgbe_write_eeprom_generic()
1032 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); in ixgbe_write_eeprom_generic()
1037 * @hw: pointer to hardware structure
1044 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang_generic() argument
1050 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_buffer_bit_bang_generic()
1055 if (offset + words > hw->eeprom.word_size) in ixgbe_read_eeprom_buffer_bit_bang_generic()
1067 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_read_eeprom_buffer_bit_bang_generic()
1079 * @hw: pointer to hardware structure
1086 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang() argument
1095 status = ixgbe_acquire_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1099 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_read_eeprom_buffer_bit_bang()
1100 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1105 ixgbe_standby_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1109 if ((hw->eeprom.address_bits == 8) && in ixgbe_read_eeprom_buffer_bit_bang()
1114 ixgbe_shift_out_eeprom_bits(hw, read_opcode, in ixgbe_read_eeprom_buffer_bit_bang()
1116 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_read_eeprom_buffer_bit_bang()
1117 hw->eeprom.address_bits); in ixgbe_read_eeprom_buffer_bit_bang()
1120 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); in ixgbe_read_eeprom_buffer_bit_bang()
1125 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1132 * @hw: pointer to hardware structure
1138 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_bit_bang_generic() argument
1141 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_bit_bang_generic()
1143 if (offset >= hw->eeprom.word_size) in ixgbe_read_eeprom_bit_bang_generic()
1146 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_read_eeprom_bit_bang_generic()
1151 * @hw: pointer to hardware structure
1158 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eerd_buffer_generic() argument
1165 hw->eeprom.ops.init_params(hw); in ixgbe_read_eerd_buffer_generic()
1170 if (offset >= hw->eeprom.word_size) in ixgbe_read_eerd_buffer_generic()
1177 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); in ixgbe_read_eerd_buffer_generic()
1178 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); in ixgbe_read_eerd_buffer_generic()
1181 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> in ixgbe_read_eerd_buffer_generic()
1184 hw_dbg(hw, "Eeprom read timed out\n"); in ixgbe_read_eerd_buffer_generic()
1194 * @hw: pointer to hardware structure
1201 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, in ixgbe_detect_eeprom_page_size_generic() argument
1211 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; in ixgbe_detect_eeprom_page_size_generic()
1212 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, in ixgbe_detect_eeprom_page_size_generic()
1214 hw->eeprom.word_page_size = 0; in ixgbe_detect_eeprom_page_size_generic()
1218 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_detect_eeprom_page_size_generic()
1226 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; in ixgbe_detect_eeprom_page_size_generic()
1228 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", in ixgbe_detect_eeprom_page_size_generic()
1229 hw->eeprom.word_page_size); in ixgbe_detect_eeprom_page_size_generic()
1235 * @hw: pointer to hardware structure
1241 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) in ixgbe_read_eerd_generic() argument
1243 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); in ixgbe_read_eerd_generic()
1248 * @hw: pointer to hardware structure
1255 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eewr_buffer_generic() argument
1262 hw->eeprom.ops.init_params(hw); in ixgbe_write_eewr_buffer_generic()
1267 if (offset >= hw->eeprom.word_size) in ixgbe_write_eewr_buffer_generic()
1275 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1277 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1281 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); in ixgbe_write_eewr_buffer_generic()
1283 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1285 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1295 * @hw: pointer to hardware structure
1301 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eewr_generic() argument
1303 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); in ixgbe_write_eewr_generic()
1308 * @hw: pointer to hardware structure
1314 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) in ixgbe_poll_eerd_eewr_done() argument
1321 reg = IXGBE_READ_REG(hw, IXGBE_EERD); in ixgbe_poll_eerd_eewr_done()
1323 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); in ixgbe_poll_eerd_eewr_done()
1335 * @hw: pointer to hardware structure
1340 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) in ixgbe_acquire_eeprom() argument
1345 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) in ixgbe_acquire_eeprom()
1348 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1352 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1355 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1364 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1365 hw_dbg(hw, "Could not acquire EEPROM grant\n"); in ixgbe_acquire_eeprom()
1367 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_acquire_eeprom()
1374 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1375 IXGBE_WRITE_FLUSH(hw); in ixgbe_acquire_eeprom()
1382 * @hw: pointer to hardware structure
1386 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_get_eeprom_semaphore() argument
1398 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1405 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1411 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1418 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1420 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); in ixgbe_get_eeprom_semaphore()
1427 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1431 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_get_eeprom_semaphore()
1436 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1447 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1448 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1457 * @hw: pointer to hardware structure
1461 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_release_eeprom_semaphore() argument
1465 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_release_eeprom_semaphore()
1469 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_release_eeprom_semaphore()
1470 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom_semaphore()
1475 * @hw: pointer to hardware structure
1477 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) in ixgbe_ready_eeprom() argument
1489 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, in ixgbe_ready_eeprom()
1491 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); in ixgbe_ready_eeprom()
1496 ixgbe_standby_eeprom(hw); in ixgbe_ready_eeprom()
1504 hw_dbg(hw, "SPI EEPROM Status error\n"); in ixgbe_ready_eeprom()
1513 * @hw: pointer to hardware structure
1515 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) in ixgbe_standby_eeprom() argument
1519 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_standby_eeprom()
1523 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1524 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1527 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1528 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1534 * @hw: pointer to hardware structure
1538 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, in ixgbe_shift_out_eeprom_bits() argument
1545 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_out_eeprom_bits()
1566 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1567 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1571 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1572 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1583 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1584 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1589 * @hw: pointer to hardware structure
1592 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) in ixgbe_shift_in_eeprom_bits() argument
1605 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1611 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1613 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1619 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1627 * @hw: pointer to hardware structure
1630 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_raise_eeprom_clk() argument
1637 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_raise_eeprom_clk()
1638 IXGBE_WRITE_FLUSH(hw); in ixgbe_raise_eeprom_clk()
1644 * @hw: pointer to hardware structure
1647 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_lower_eeprom_clk() argument
1654 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_lower_eeprom_clk()
1655 IXGBE_WRITE_FLUSH(hw); in ixgbe_lower_eeprom_clk()
1661 * @hw: pointer to hardware structure
1663 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) in ixgbe_release_eeprom() argument
1667 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_release_eeprom()
1672 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1673 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom()
1679 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1681 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_release_eeprom()
1687 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_release_eeprom()
1688 hw->eeprom.semaphore_delay * 2000); in ixgbe_release_eeprom()
1693 * @hw: pointer to hardware structure
1695 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_calc_eeprom_checksum_generic() argument
1706 if (hw->eeprom.ops.read(hw, i, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1707 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1715 if (hw->eeprom.ops.read(hw, i, &pointer)) { in ixgbe_calc_eeprom_checksum_generic()
1716 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1724 if (hw->eeprom.ops.read(hw, pointer, &length)) { in ixgbe_calc_eeprom_checksum_generic()
1725 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1733 if (hw->eeprom.ops.read(hw, j, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1734 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1748 * @hw: pointer to hardware structure
1754 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, in ixgbe_validate_eeprom_checksum_generic() argument
1766 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_validate_eeprom_checksum_generic()
1768 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1772 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_validate_eeprom_checksum_generic()
1778 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); in ixgbe_validate_eeprom_checksum_generic()
1780 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1799 * @hw: pointer to hardware structure
1801 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_update_eeprom_checksum_generic() argument
1811 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_update_eeprom_checksum_generic()
1813 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_update_eeprom_checksum_generic()
1817 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_update_eeprom_checksum_generic()
1823 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); in ixgbe_update_eeprom_checksum_generic()
1830 * @hw: pointer to hardware structure
1838 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ixgbe_set_rar_generic() argument
1842 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_rar_generic()
1846 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_set_rar_generic()
1851 hw->mac.ops.set_vmdq(hw, index, vmdq); in ixgbe_set_rar_generic()
1854 * HW expects these in little endian so we reverse the byte in ixgbe_set_rar_generic()
1866 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_set_rar_generic()
1877 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); in ixgbe_set_rar_generic()
1878 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_rar_generic()
1879 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_set_rar_generic()
1886 * @hw: pointer to hardware structure
1891 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_clear_rar_generic() argument
1894 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_rar_generic()
1898 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_clear_rar_generic()
1907 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_clear_rar_generic()
1914 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_clear_rar_generic()
1915 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_rar_generic()
1916 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); in ixgbe_clear_rar_generic()
1919 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_clear_rar_generic()
1926 * @hw: pointer to hardware structure
1932 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) in ixgbe_init_rx_addrs_generic() argument
1935 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_init_rx_addrs_generic()
1942 if (!is_valid_ether_addr(hw->mac.addr)) { in ixgbe_init_rx_addrs_generic()
1944 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1946 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1949 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); in ixgbe_init_rx_addrs_generic()
1950 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1952 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); in ixgbe_init_rx_addrs_generic()
1956 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_init_rx_addrs_generic()
1958 hw->addr_ctrl.overflow_promisc = 0; in ixgbe_init_rx_addrs_generic()
1960 hw->addr_ctrl.rar_used_count = 1; in ixgbe_init_rx_addrs_generic()
1963 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); in ixgbe_init_rx_addrs_generic()
1965 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); in ixgbe_init_rx_addrs_generic()
1966 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); in ixgbe_init_rx_addrs_generic()
1970 hw->addr_ctrl.mta_in_use = 0; in ixgbe_init_rx_addrs_generic()
1971 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_init_rx_addrs_generic()
1973 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_init_rx_addrs_generic()
1974 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_init_rx_addrs_generic()
1975 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); in ixgbe_init_rx_addrs_generic()
1977 if (hw->mac.ops.init_uta_tables) in ixgbe_init_rx_addrs_generic()
1978 hw->mac.ops.init_uta_tables(hw); in ixgbe_init_rx_addrs_generic()
1985 * @hw: pointer to hardware structure
1995 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_mta_vector() argument
1999 switch (hw->mac.mc_filter_type) { in ixgbe_mta_vector()
2013 hw_dbg(hw, "MC filter type param set incorrectly\n"); in ixgbe_mta_vector()
2024 * @hw: pointer to hardware structure
2029 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_set_mta() argument
2035 hw->addr_ctrl.mta_in_use++; in ixgbe_set_mta()
2037 vector = ixgbe_mta_vector(hw, mc_addr); in ixgbe_set_mta()
2038 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); in ixgbe_set_mta()
2051 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); in ixgbe_set_mta()
2056 * @hw: pointer to hardware structure
2064 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, in ixgbe_update_mc_addr_list_generic() argument
2074 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); in ixgbe_update_mc_addr_list_generic()
2075 hw->addr_ctrl.mta_in_use = 0; in ixgbe_update_mc_addr_list_generic()
2078 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_update_mc_addr_list_generic()
2079 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in ixgbe_update_mc_addr_list_generic()
2083 hw_dbg(hw, " Adding the multicast addresses:\n"); in ixgbe_update_mc_addr_list_generic()
2084 ixgbe_set_mta(hw, ha->addr); in ixgbe_update_mc_addr_list_generic()
2088 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_update_mc_addr_list_generic()
2089 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, in ixgbe_update_mc_addr_list_generic()
2090 hw->mac.mta_shadow[i]); in ixgbe_update_mc_addr_list_generic()
2092 if (hw->addr_ctrl.mta_in_use > 0) in ixgbe_update_mc_addr_list_generic()
2093 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, in ixgbe_update_mc_addr_list_generic()
2094 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); in ixgbe_update_mc_addr_list_generic()
2096 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); in ixgbe_update_mc_addr_list_generic()
2102 * @hw: pointer to hardware structure
2106 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) in ixgbe_enable_mc_generic() argument
2108 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_enable_mc_generic()
2111 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | in ixgbe_enable_mc_generic()
2112 hw->mac.mc_filter_type); in ixgbe_enable_mc_generic()
2119 * @hw: pointer to hardware structure
2123 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) in ixgbe_disable_mc_generic() argument
2125 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_disable_mc_generic()
2128 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_disable_mc_generic()
2135 * @hw: pointer to hardware structure
2139 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) in ixgbe_fc_enable_generic() argument
2147 if (!hw->fc.pause_time) in ixgbe_fc_enable_generic()
2152 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2153 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2154 if (!hw->fc.low_water[i] || in ixgbe_fc_enable_generic()
2155 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2156 hw_dbg(hw, "Invalid water mark configuration\n"); in ixgbe_fc_enable_generic()
2163 hw->mac.ops.fc_autoneg(hw); in ixgbe_fc_enable_generic()
2166 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); in ixgbe_fc_enable_generic()
2169 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); in ixgbe_fc_enable_generic()
2182 switch (hw->fc.current_mode) { in ixgbe_fc_enable_generic()
2186 * The code below will actually disable it in the HW. in ixgbe_fc_enable_generic()
2213 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_fc_enable_generic()
2219 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); in ixgbe_fc_enable_generic()
2220 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); in ixgbe_fc_enable_generic()
2224 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2225 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2226 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_fc_enable_generic()
2227 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); in ixgbe_fc_enable_generic()
2228 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_generic()
2230 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); in ixgbe_fc_enable_generic()
2238 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; in ixgbe_fc_enable_generic()
2241 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); in ixgbe_fc_enable_generic()
2245 reg = hw->fc.pause_time * 0x00010001U; in ixgbe_fc_enable_generic()
2247 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_fc_enable_generic()
2249 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); in ixgbe_fc_enable_generic()
2256 * @hw: pointer to hardware structure
2267 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, in ixgbe_negotiate_fc() argument
2281 if (hw->fc.requested_mode == ixgbe_fc_full) { in ixgbe_negotiate_fc()
2282 hw->fc.current_mode = ixgbe_fc_full; in ixgbe_negotiate_fc()
2283 hw_dbg(hw, "Flow Control = FULL.\n"); in ixgbe_negotiate_fc()
2285 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2286 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); in ixgbe_negotiate_fc()
2290 hw->fc.current_mode = ixgbe_fc_tx_pause; in ixgbe_negotiate_fc()
2291 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2294 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2295 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2297 hw->fc.current_mode = ixgbe_fc_none; in ixgbe_negotiate_fc()
2298 hw_dbg(hw, "Flow Control = NONE.\n"); in ixgbe_negotiate_fc()
2305 * @hw: pointer to hardware structure
2309 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_fiber() argument
2320 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); in ixgbe_fc_autoneg_fiber()
2325 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_fc_autoneg_fiber()
2326 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); in ixgbe_fc_autoneg_fiber()
2328 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, in ixgbe_fc_autoneg_fiber()
2339 * @hw: pointer to hardware structure
2343 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_backplane() argument
2353 links = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_fc_autoneg_backplane()
2357 if (hw->mac.type == ixgbe_mac_82599EB) { in ixgbe_fc_autoneg_backplane()
2358 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); in ixgbe_fc_autoneg_backplane()
2366 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_fc_autoneg_backplane()
2367 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); in ixgbe_fc_autoneg_backplane()
2369 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, in ixgbe_fc_autoneg_backplane()
2378 * @hw: pointer to hardware structure
2382 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_copper() argument
2387 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_fc_autoneg_copper()
2390 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, in ixgbe_fc_autoneg_copper()
2394 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, in ixgbe_fc_autoneg_copper()
2402 * @hw: pointer to hardware structure
2407 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) in ixgbe_fc_autoneg() argument
2422 if (hw->fc.disable_fc_autoneg) in ixgbe_fc_autoneg()
2425 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_fc_autoneg()
2429 switch (hw->phy.media_type) { in ixgbe_fc_autoneg()
2433 ret_val = ixgbe_fc_autoneg_fiber(hw); in ixgbe_fc_autoneg()
2438 ret_val = ixgbe_fc_autoneg_backplane(hw); in ixgbe_fc_autoneg()
2443 if (ixgbe_device_supports_autoneg_fc(hw)) in ixgbe_fc_autoneg()
2444 ret_val = ixgbe_fc_autoneg_copper(hw); in ixgbe_fc_autoneg()
2453 hw->fc.fc_was_autonegged = true; in ixgbe_fc_autoneg()
2455 hw->fc.fc_was_autonegged = false; in ixgbe_fc_autoneg()
2456 hw->fc.current_mode = hw->fc.requested_mode; in ixgbe_fc_autoneg()
2462 * @hw: pointer to hardware structure
2470 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) in ixgbe_pcie_timeout_poll() argument
2475 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); in ixgbe_pcie_timeout_poll()
2509 * @hw: pointer to hardware structure
2516 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) in ixgbe_disable_pcie_master() argument
2522 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); in ixgbe_disable_pcie_master()
2526 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) in ixgbe_disable_pcie_master()
2531 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); in ixgbe_disable_pcie_master()
2536 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || in ixgbe_disable_pcie_master()
2537 ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_master()
2543 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) in ixgbe_disable_pcie_master()
2555 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); in ixgbe_disable_pcie_master()
2557 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_disable_pcie_master()
2559 if (hw->mac.type >= ixgbe_mac_X550) in ixgbe_disable_pcie_master()
2566 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_disable_pcie_master()
2569 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_disable_pcie_master()
2570 if (ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_master()
2576 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); in ixgbe_disable_pcie_master()
2582 * @hw: pointer to hardware structure
2588 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_acquire_swfw_sync() argument
2601 if (ixgbe_get_eeprom_semaphore(hw)) in ixgbe_acquire_swfw_sync()
2604 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_acquire_swfw_sync()
2607 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_acquire_swfw_sync()
2608 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2612 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2619 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); in ixgbe_acquire_swfw_sync()
2627 * @hw: pointer to hardware structure
2633 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_release_swfw_sync() argument
2638 ixgbe_get_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2640 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_release_swfw_sync()
2642 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_release_swfw_sync()
2644 ixgbe_release_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2649 * @hw: pointer to hardware structure
2656 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) in prot_autoc_read_generic() argument
2659 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); in prot_autoc_read_generic()
2665 * @hw: pointer to hardware structure
2670 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) in prot_autoc_write_generic() argument
2672 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); in prot_autoc_write_generic()
2678 * @hw: pointer to hardware structure
2680 * Stops the receive data path and waits for the HW to internally
2683 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_buff_generic() argument
2689 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_disable_rx_buff_generic()
2691 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_disable_rx_buff_generic()
2693 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); in ixgbe_disable_rx_buff_generic()
2703 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); in ixgbe_disable_rx_buff_generic()
2711 * @hw: pointer to hardware structure
2715 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_buff_generic() argument
2719 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_enable_rx_buff_generic()
2721 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_enable_rx_buff_generic()
2722 IXGBE_WRITE_FLUSH(hw); in ixgbe_enable_rx_buff_generic()
2729 * @hw: pointer to hardware structure
2734 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_generic() argument
2737 hw->mac.ops.enable_rx(hw); in ixgbe_enable_rx_dma_generic()
2739 hw->mac.ops.disable_rx(hw); in ixgbe_enable_rx_dma_generic()
2746 * @hw: pointer to hardware structure
2749 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_start_generic() argument
2753 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_blink_led_start_generic()
2754 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_start_generic()
2765 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_blink_led_start_generic()
2768 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_start_generic()
2775 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_start_generic()
2779 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2786 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_start_generic()
2787 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2794 * @hw: pointer to hardware structure
2797 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_stop_generic() argument
2800 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_stop_generic()
2807 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_stop_generic()
2814 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_stop_generic()
2821 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_stop_generic()
2822 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_stop_generic()
2829 * @hw: pointer to hardware structure
2836 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, in ixgbe_get_san_mac_addr_offset() argument
2845 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, in ixgbe_get_san_mac_addr_offset()
2848 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_offset()
2856 * @hw: pointer to hardware structure
2864 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) in ixgbe_get_san_mac_addr_generic() argument
2874 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); in ixgbe_get_san_mac_addr_generic()
2880 hw->mac.ops.set_lan_id(hw); in ixgbe_get_san_mac_addr_generic()
2882 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : in ixgbe_get_san_mac_addr_generic()
2885 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, in ixgbe_get_san_mac_addr_generic()
2888 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_generic()
2909 * @hw: pointer to hardware structure
2914 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) in ixgbe_get_pcie_msix_count_generic() argument
2920 switch (hw->mac.type) { in ixgbe_get_pcie_msix_count_generic()
2937 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); in ixgbe_get_pcie_msix_count_generic()
2938 if (ixgbe_removed(hw->hw_addr)) in ixgbe_get_pcie_msix_count_generic()
2942 /* MSI-X count is zero-based in HW */ in ixgbe_get_pcie_msix_count_generic()
2953 * @hw: pointer to hardware struct
2957 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_clear_vmdq_generic() argument
2960 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_vmdq_generic()
2964 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_clear_vmdq_generic()
2968 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_clear_vmdq_generic()
2969 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_clear_vmdq_generic()
2971 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_vmdq_generic()
2979 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_clear_vmdq_generic()
2983 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_clear_vmdq_generic()
2988 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); in ixgbe_clear_vmdq_generic()
2991 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); in ixgbe_clear_vmdq_generic()
2996 rar != 0 && rar != hw->mac.san_mac_rar_index) in ixgbe_clear_vmdq_generic()
2997 hw->mac.ops.clear_rar(hw, rar); in ixgbe_clear_vmdq_generic()
3004 * @hw: pointer to hardware struct
3008 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_set_vmdq_generic() argument
3011 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_vmdq_generic()
3015 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_set_vmdq_generic()
3020 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_set_vmdq_generic()
3022 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); in ixgbe_set_vmdq_generic()
3024 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_set_vmdq_generic()
3026 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); in ixgbe_set_vmdq_generic()
3035 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3038 * @hw: pointer to hardware struct
3041 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) in ixgbe_set_vmdq_san_mac_generic() argument
3043 u32 rar = hw->mac.san_mac_rar_index; in ixgbe_set_vmdq_san_mac_generic()
3046 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); in ixgbe_set_vmdq_san_mac_generic()
3047 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3049 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3050 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); in ixgbe_set_vmdq_san_mac_generic()
3058 * @hw: pointer to hardware structure
3060 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) in ixgbe_init_uta_tables_generic() argument
3065 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); in ixgbe_init_uta_tables_generic()
3072 * @hw: pointer to hardware structure
3080 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) in ixgbe_find_vlvf_slot() argument
3104 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); in ixgbe_find_vlvf_slot()
3115 hw_dbg(hw, "No space in VLVF.\n"); in ixgbe_find_vlvf_slot()
3122 * @hw: pointer to hardware structure
3130 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, in ixgbe_set_vfta_generic() argument
3153 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); in ixgbe_set_vfta_generic()
3170 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) in ixgbe_set_vfta_generic()
3173 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); in ixgbe_set_vfta_generic()
3180 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); in ixgbe_set_vfta_generic()
3191 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { in ixgbe_set_vfta_generic()
3197 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
3200 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); in ixgbe_set_vfta_generic()
3201 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); in ixgbe_set_vfta_generic()
3224 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); in ixgbe_set_vfta_generic()
3225 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); in ixgbe_set_vfta_generic()
3230 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
3237 * @hw: pointer to hardware structure
3241 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) in ixgbe_clear_vfta_generic() argument
3245 for (offset = 0; offset < hw->mac.vft_size; offset++) in ixgbe_clear_vfta_generic()
3246 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); in ixgbe_clear_vfta_generic()
3249 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); in ixgbe_clear_vfta_generic()
3250 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); in ixgbe_clear_vfta_generic()
3251 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); in ixgbe_clear_vfta_generic()
3259 * @hw: pointer to hardware structure
3264 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) in ixgbe_need_crosstalk_fix() argument
3267 if (!hw->need_crosstalk_fix) in ixgbe_need_crosstalk_fix()
3271 switch (hw->mac.ops.get_media_type(hw)) { in ixgbe_need_crosstalk_fix()
3284 * @hw: pointer to hardware structure
3291 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, in ixgbe_check_mac_link_generic() argument
3300 if (ixgbe_need_crosstalk_fix(hw)) { in ixgbe_check_mac_link_generic()
3303 switch (hw->mac.type) { in ixgbe_check_mac_link_generic()
3305 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
3310 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
3327 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3329 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3332 hw_dbg(hw, "LINKS changed from %08X to %08X\n", in ixgbe_check_mac_link_generic()
3345 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3356 if ((hw->mac.type >= ixgbe_mac_X550) && in ixgbe_check_mac_link_generic()
3366 if ((hw->mac.type >= ixgbe_mac_X550) && in ixgbe_check_mac_link_generic()
3374 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || in ixgbe_check_mac_link_generic()
3375 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { in ixgbe_check_mac_link_generic()
3389 * @hw: pointer to hardware structure
3396 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, in ixgbe_get_wwn_prefix_generic() argument
3408 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) in ixgbe_get_wwn_prefix_generic()
3417 if (hw->eeprom.ops.read(hw, offset, &caps)) in ixgbe_get_wwn_prefix_generic()
3424 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) in ixgbe_get_wwn_prefix_generic()
3425 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3428 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) in ixgbe_get_wwn_prefix_generic()
3434 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3440 * @hw: pointer to hardware structure
3445 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_mac_anti_spoofing() argument
3451 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_mac_anti_spoofing()
3454 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_mac_anti_spoofing()
3459 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_mac_anti_spoofing()
3464 * @hw: pointer to hardware structure
3469 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_vlan_anti_spoofing() argument
3475 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_vlan_anti_spoofing()
3478 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_vlan_anti_spoofing()
3483 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_vlan_anti_spoofing()
3488 * @hw: pointer to hardware structure
3494 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) in ixgbe_get_device_caps_generic() argument
3496 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); in ixgbe_get_device_caps_generic()
3503 * @hw: pointer to hardware structure
3508 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, in ixgbe_set_rxpba_generic() argument
3513 u32 pbsize = hw->mac.rx_pb_size; in ixgbe_set_rxpba_generic()
3535 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3541 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3555 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); in ixgbe_set_rxpba_generic()
3556 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); in ixgbe_set_rxpba_generic()
3561 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3562 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3563 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); in ixgbe_set_rxpba_generic()
3591 * @hw: pointer to the HW structure
3603 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, in ixgbe_hic_unlocked() argument
3610 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_hic_unlocked()
3615 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); in ixgbe_hic_unlocked()
3616 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); in ixgbe_hic_unlocked()
3619 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
3621 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); in ixgbe_hic_unlocked()
3627 hw_dbg(hw, "Buffer length failure, not aligned to dword"); in ixgbe_hic_unlocked()
3637 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, in ixgbe_hic_unlocked()
3641 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); in ixgbe_hic_unlocked()
3644 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
3652 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) in ixgbe_hic_unlocked()
3660 * @hw: pointer to the HW structure
3675 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, in ixgbe_host_interface_command() argument
3689 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_host_interface_command()
3693 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
3697 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); in ixgbe_host_interface_command()
3709 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3719 hw_dbg(hw, "Buffer not large enough for reply message.\n"); in ixgbe_host_interface_command()
3729 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3734 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
3741 * @hw: pointer to the HW structure
3754 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, in ixgbe_set_fw_drv_ver_generic() argument
3765 fw_cmd.port_num = hw->bus.func; in ixgbe_set_fw_drv_ver_generic()
3777 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, in ixgbe_set_fw_drv_ver_generic()
3798 * @hw: pointer to the hardware structure
3804 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) in ixgbe_clear_tx_pending() argument
3813 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) in ixgbe_clear_tx_pending()
3821 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); in ixgbe_clear_tx_pending()
3822 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); in ixgbe_clear_tx_pending()
3825 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3831 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_clear_tx_pending()
3834 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_clear_tx_pending()
3835 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_tx_pending()
3842 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); in ixgbe_clear_tx_pending()
3843 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, in ixgbe_clear_tx_pending()
3847 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3851 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); in ixgbe_clear_tx_pending()
3852 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); in ixgbe_clear_tx_pending()
3870 * @hw: pointer to hardware structure
3876 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, in ixgbe_get_ets_data() argument
3881 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); in ixgbe_get_ets_data()
3888 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); in ixgbe_get_ets_data()
3900 * @hw: pointer to hardware structure
3904 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) in ixgbe_get_thermal_sensor_data_generic() argument
3912 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_get_thermal_sensor_data_generic()
3915 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_get_thermal_sensor_data_generic()
3918 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_get_thermal_sensor_data_generic()
3930 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), in ixgbe_get_thermal_sensor_data_generic()
3941 status = hw->phy.ops.read_i2c_byte(hw, in ixgbe_get_thermal_sensor_data_generic()
3955 * @hw: pointer to hardware structure
3960 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) in ixgbe_init_thermal_sensor_thresh_generic() argument
3970 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_init_thermal_sensor_thresh_generic()
3975 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_init_thermal_sensor_thresh_generic()
3978 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_init_thermal_sensor_thresh_generic()
3992 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { in ixgbe_init_thermal_sensor_thresh_generic()
3993 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_init_thermal_sensor_thresh_generic()
4003 hw->phy.ops.write_i2c_byte(hw, in ixgbe_init_thermal_sensor_thresh_generic()
4021 * @hw: pointer to hardware structure
4027 void ixgbe_get_orom_version(struct ixgbe_hw *hw, in ixgbe_get_orom_version() argument
4034 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); in ixgbe_get_orom_version()
4040 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); in ixgbe_get_orom_version()
4041 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); in ixgbe_get_orom_version()
4059 * @hw: pointer to hardware structure
4065 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, in ixgbe_get_oem_prod_version() argument
4071 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); in ixgbe_get_oem_prod_version()
4078 hw->eeprom.ops.read(hw, offset, &mod_len); in ixgbe_get_oem_prod_version()
4079 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); in ixgbe_get_oem_prod_version()
4086 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); in ixgbe_get_oem_prod_version()
4087 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); in ixgbe_get_oem_prod_version()
4103 * @hw: pointer to hardware structure
4108 void ixgbe_get_etk_id(struct ixgbe_hw *hw, in ixgbe_get_etk_id() argument
4113 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) in ixgbe_get_etk_id()
4115 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) in ixgbe_get_etk_id()
4130 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_generic() argument
4134 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_disable_rx_generic()
4136 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_disable_rx_generic()
4139 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_disable_rx_generic()
4142 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_disable_rx_generic()
4143 hw->mac.set_lben = true; in ixgbe_disable_rx_generic()
4145 hw->mac.set_lben = false; in ixgbe_disable_rx_generic()
4149 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); in ixgbe_disable_rx_generic()
4153 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_generic() argument
4157 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_enable_rx_generic()
4158 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); in ixgbe_enable_rx_generic()
4160 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_enable_rx_generic()
4161 if (hw->mac.set_lben) { in ixgbe_enable_rx_generic()
4164 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_enable_rx_generic()
4166 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_enable_rx_generic()
4167 hw->mac.set_lben = false; in ixgbe_enable_rx_generic()
4173 * @hw: pointer to hardware structure
4175 bool ixgbe_mng_present(struct ixgbe_hw *hw) in ixgbe_mng_present() argument
4179 if (hw->mac.type < ixgbe_mac_82599EB) in ixgbe_mng_present()
4182 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); in ixgbe_mng_present()
4189 * @hw: pointer to hardware structure
4195 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_multispeed_fiber() argument
4207 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); in ixgbe_setup_mac_link_multispeed_fiber()
4221 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4223 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4230 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4237 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4244 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4245 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4256 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_multispeed_fiber()
4272 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4274 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4281 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4288 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4295 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4296 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4302 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, in ixgbe_setup_mac_link_multispeed_fiber()
4316 status = ixgbe_setup_mac_link_multispeed_fiber(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4322 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_multispeed_fiber()
4325 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4328 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4335 * @hw: pointer to hardware structure
4340 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, in ixgbe_set_soft_rate_select_speed() argument
4355 hw_dbg(hw, "Invalid fixed module speed\n"); in ixgbe_set_soft_rate_select_speed()
4360 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4364 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4370 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4374 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4379 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
4383 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); in ixgbe_set_soft_rate_select_speed()
4389 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
4393 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); in ixgbe_set_soft_rate_select_speed()