1 // SPDX-License-Identifier: GPL-2.0
13  * igc_reset_hw_base - Reset hardware
14  * @hw: pointer to the HW structure
19 static s32 igc_reset_hw_base(struct igc_hw *hw)  in igc_reset_hw_base()  argument
22 	u32 ctrl;  in igc_reset_hw_base()  local
24 	/* Prevent the PCI-E bus from sticking if there is no TLP connection  in igc_reset_hw_base()
27 	ret_val = igc_disable_pcie_master(hw);  in igc_reset_hw_base()
29 		hw_dbg("PCI-E Master disable polling has failed\n");  in igc_reset_hw_base()
40 	ctrl = rd32(IGC_CTRL);  in igc_reset_hw_base()
43 	wr32(IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);  in igc_reset_hw_base()
45 	ret_val = igc_get_auto_rd_done(hw);  in igc_reset_hw_base()
62  * igc_init_nvm_params_base - Init NVM func ptrs.
63  * @hw: pointer to the HW structure
65 static s32 igc_init_nvm_params_base(struct igc_hw *hw)  in igc_init_nvm_params_base()  argument
67 	struct igc_nvm_info *nvm = &hw->nvm;  in igc_init_nvm_params_base()
74 	/* Added to a constant, "size" becomes the left-shift value  in igc_init_nvm_params_base()
85 	nvm->type = igc_nvm_eeprom_spi;  in igc_init_nvm_params_base()
86 	nvm->word_size = BIT(size);  in igc_init_nvm_params_base()
87 	nvm->opcode_bits = 8;  in igc_init_nvm_params_base()
88 	nvm->delay_usec = 1;  in igc_init_nvm_params_base()
90 	nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;  in igc_init_nvm_params_base()
91 	nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?  in igc_init_nvm_params_base()
94 	if (nvm->word_size == BIT(15))  in igc_init_nvm_params_base()
95 		nvm->page_size = 128;  in igc_init_nvm_params_base()
101  * igc_setup_copper_link_base - Configure copper link settings
102  * @hw: pointer to the HW structure
104  * Configures the link for auto-neg or forced speed and duplex.  Then we check
106  * and flow control are called.
108 static s32 igc_setup_copper_link_base(struct igc_hw *hw)  in igc_setup_copper_link_base()  argument
111 	u32 ctrl;  in igc_setup_copper_link_base()  local
113 	ctrl = rd32(IGC_CTRL);  in igc_setup_copper_link_base()
114 	ctrl |= IGC_CTRL_SLU;  in igc_setup_copper_link_base()
115 	ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);  in igc_setup_copper_link_base()
116 	wr32(IGC_CTRL, ctrl);  in igc_setup_copper_link_base()
118 	ret_val = igc_setup_copper_link(hw);  in igc_setup_copper_link_base()
124  * igc_init_mac_params_base - Init MAC func ptrs.
125  * @hw: pointer to the HW structure
127 static s32 igc_init_mac_params_base(struct igc_hw *hw)  in igc_init_mac_params_base()  argument
129 	struct igc_dev_spec_base *dev_spec = &hw->dev_spec._base;  in igc_init_mac_params_base()
130 	struct igc_mac_info *mac = &hw->mac;  in igc_init_mac_params_base()
133 	mac->mta_reg_count = 128;  in igc_init_mac_params_base()
134 	mac->rar_entry_count = IGC_RAR_ENTRIES;  in igc_init_mac_params_base()
137 	mac->ops.reset_hw = igc_reset_hw_base;  in igc_init_mac_params_base()
139 	mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;  in igc_init_mac_params_base()
140 	mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;  in igc_init_mac_params_base()
143 	if (mac->type == igc_i225)  in igc_init_mac_params_base()
144 		dev_spec->clear_semaphore_once = true;  in igc_init_mac_params_base()
147 	mac->ops.setup_physical_interface = igc_setup_copper_link_base;  in igc_init_mac_params_base()
153  * igc_init_phy_params_base - Init PHY func ptrs.
154  * @hw: pointer to the HW structure
156 static s32 igc_init_phy_params_base(struct igc_hw *hw)  in igc_init_phy_params_base()  argument
158 	struct igc_phy_info *phy = &hw->phy;  in igc_init_phy_params_base()
161 	if (hw->phy.media_type != igc_media_type_copper) {  in igc_init_phy_params_base()
162 		phy->type = igc_phy_none;  in igc_init_phy_params_base()
166 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;  in igc_init_phy_params_base()
167 	phy->reset_delay_us	= 100;  in igc_init_phy_params_base()
170 	hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >>  in igc_init_phy_params_base()
178 	ret_val = hw->phy.ops.reset(hw);  in igc_init_phy_params_base()
184 	ret_val = igc_get_phy_id(hw);  in igc_init_phy_params_base()
188 	igc_check_for_copper_link(hw);  in igc_init_phy_params_base()
191 	switch (phy->id) {  in igc_init_phy_params_base()
193 		phy->type	= igc_phy_i225;  in igc_init_phy_params_base()
196 		ret_val = -IGC_ERR_PHY;  in igc_init_phy_params_base()
204 static s32 igc_get_invariants_base(struct igc_hw *hw)  in igc_get_invariants_base()  argument
206 	struct igc_mac_info *mac = &hw->mac;  in igc_get_invariants_base()
209 	switch (hw->device_id) {  in igc_get_invariants_base()
224 		mac->type = igc_i225;  in igc_get_invariants_base()
227 		return -IGC_ERR_MAC_INIT;  in igc_get_invariants_base()
230 	hw->phy.media_type = igc_media_type_copper;  in igc_get_invariants_base()
233 	ret_val = igc_init_mac_params_base(hw);  in igc_get_invariants_base()
238 	ret_val = igc_init_nvm_params_base(hw);  in igc_get_invariants_base()
239 	switch (hw->mac.type) {  in igc_get_invariants_base()
241 		ret_val = igc_init_nvm_params_i225(hw);  in igc_get_invariants_base()
248 	ret_val = igc_init_phy_params_base(hw);  in igc_get_invariants_base()
257  * igc_acquire_phy_base - Acquire rights to access PHY
258  * @hw: pointer to the HW structure
263 static s32 igc_acquire_phy_base(struct igc_hw *hw)  in igc_acquire_phy_base()  argument
267 	return hw->mac.ops.acquire_swfw_sync(hw, mask);  in igc_acquire_phy_base()
271  * igc_release_phy_base - Release rights to access PHY
272  * @hw: pointer to the HW structure
277 static void igc_release_phy_base(struct igc_hw *hw)  in igc_release_phy_base()  argument
281 	hw->mac.ops.release_swfw_sync(hw, mask);  in igc_release_phy_base()
285  * igc_init_hw_base - Initialize hardware
286  * @hw: pointer to the HW structure
290 static s32 igc_init_hw_base(struct igc_hw *hw)  in igc_init_hw_base()  argument
292 	struct igc_mac_info *mac = &hw->mac;  in igc_init_hw_base()
293 	u16 i, rar_count = mac->rar_entry_count;  in igc_init_hw_base()
297 	igc_init_rx_addrs(hw, rar_count);  in igc_init_hw_base()
301 	for (i = 0; i < mac->mta_reg_count; i++)  in igc_init_hw_base()
306 	for (i = 0; i < mac->uta_reg_count; i++)  in igc_init_hw_base()
309 	/* Setup link and flow control */  in igc_init_hw_base()
310 	ret_val = igc_setup_link(hw);  in igc_init_hw_base()
317 	igc_clear_hw_cntrs_base(hw);  in igc_init_hw_base()
323  * igc_power_down_phy_copper_base - Remove link during PHY power down
324  * @hw: pointer to the HW structure
329 void igc_power_down_phy_copper_base(struct igc_hw *hw)  in igc_power_down_phy_copper_base()  argument
332 	if (!(igc_enable_mng_pass_thru(hw) || igc_check_reset_block(hw)))  in igc_power_down_phy_copper_base()
333 		igc_power_down_phy_copper(hw);  in igc_power_down_phy_copper_base()
337  * igc_rx_fifo_flush_base - Clean rx fifo after Rx enable
338  * @hw: pointer to the HW structure
345 void igc_rx_fifo_flush_base(struct igc_hw *hw)  in igc_rx_fifo_flush_base()  argument