Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
14 static s32 igb_set_default_fc(struct e1000_hw *hw);
15 static void igb_set_fc_watermarks(struct e1000_hw *hw);
18 * igb_get_bus_info_pcie - Get PCIe bus information
19 * @hw: pointer to the HW structure
25 s32 igb_get_bus_info_pcie(struct e1000_hw *hw) in igb_get_bus_info_pcie() argument
27 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
32 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
34 ret_val = igb_read_pcie_cap_reg(hw, in igb_get_bus_info_pcie()
38 bus->width = e1000_bus_width_unknown; in igb_get_bus_info_pcie()
39 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
43 bus->speed = e1000_bus_speed_2500; in igb_get_bus_info_pcie()
46 bus->speed = e1000_bus_speed_5000; in igb_get_bus_info_pcie()
49 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
53 bus->width = (enum e1000_bus_width)((pcie_link_status & in igb_get_bus_info_pcie()
59 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; in igb_get_bus_info_pcie()
65 * igb_clear_vfta - Clear VLAN filter table
66 * @hw: pointer to the HW structure
71 void igb_clear_vfta(struct e1000_hw *hw) in igb_clear_vfta() argument
75 for (offset = E1000_VLAN_FILTER_TBL_SIZE; offset--;) in igb_clear_vfta()
76 hw->mac.ops.write_vfta(hw, offset, 0); in igb_clear_vfta()
80 * igb_write_vfta - Write value to VLAN filter table
81 * @hw: pointer to the HW structure
88 void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) in igb_write_vfta() argument
90 struct igb_adapter *adapter = hw->back; in igb_write_vfta()
95 adapter->shadow_vfta[offset] = value; in igb_write_vfta()
99 * igb_init_rx_addrs - Initialize receive address's
100 * @hw: pointer to the HW structure
107 void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) in igb_init_rx_addrs() argument
115 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igb_init_rx_addrs()
117 /* Zero out the other (rar_entry_count - 1) receive addresses */ in igb_init_rx_addrs()
118 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); in igb_init_rx_addrs()
120 hw->mac.ops.rar_set(hw, mac_addr, i); in igb_init_rx_addrs()
124 * igb_find_vlvf_slot - find the VLAN id or the first empty slot
125 * @hw: pointer to hardware structure
132 static s32 igb_find_vlvf_slot(struct e1000_hw *hw, u32 vlan, bool vlvf_bypass) in igb_find_vlvf_slot() argument
145 first_empty_slot = vlvf_bypass ? -E1000_ERR_NO_SPACE : 0; in igb_find_vlvf_slot()
150 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 in igb_find_vlvf_slot()
152 for (regindex = E1000_VLVF_ARRAY_SIZE; --regindex > 0;) { in igb_find_vlvf_slot()
160 return first_empty_slot ? : -E1000_ERR_NO_SPACE; in igb_find_vlvf_slot()
164 * igb_vfta_set - enable or disable vlan in VLAN filter table
165 * @hw: pointer to the HW structure
174 s32 igb_vfta_set(struct e1000_hw *hw, u32 vlan, u32 vind, in igb_vfta_set() argument
177 struct igb_adapter *adapter = hw->back; in igb_vfta_set()
182 return -E1000_ERR_PARAM; in igb_vfta_set()
184 /* this is a 2 part operation - first the VFTA, then the in igb_vfta_set()
190 * The VFTA is a bitstring made up of 128 32-bit registers in igb_vfta_set()
192 * bits[11-5]: which register in igb_vfta_set()
193 * bits[4-0]: which bit in the register in igb_vfta_set()
197 vfta = adapter->shadow_vfta[regidx]; in igb_vfta_set()
214 if (!adapter->vfs_allocated_count) in igb_vfta_set()
217 vlvf_index = igb_find_vlvf_slot(hw, vlan, vlvf_bypass); in igb_vfta_set()
240 hw->mac.ops.write_vfta(hw, regidx, vfta); in igb_vfta_set()
271 hw->mac.ops.write_vfta(hw, regidx, vfta); in igb_vfta_set()
277 * igb_check_alt_mac_addr - Check for alternate MAC addr
278 * @hw: pointer to the HW structure
281 * can be setup by pre-boot software and must be treated like a permanent
283 * alternate MAC address is found it is saved in the hw struct and
287 s32 igb_check_alt_mac_addr(struct e1000_hw *hw) in igb_check_alt_mac_addr() argument
297 if (hw->mac.type >= e1000_82580) in igb_check_alt_mac_addr()
300 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, in igb_check_alt_mac_addr()
312 if (hw->bus.func == E1000_FUNC_1) in igb_check_alt_mac_addr()
314 if (hw->bus.func == E1000_FUNC_2) in igb_check_alt_mac_addr()
317 if (hw->bus.func == E1000_FUNC_3) in igb_check_alt_mac_addr()
321 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in igb_check_alt_mac_addr()
338 * same as the normal permanent MAC address stored by the HW into the in igb_check_alt_mac_addr()
341 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); in igb_check_alt_mac_addr()
348 * igb_rar_set - Set receive address register
349 * @hw: pointer to the HW structure
356 void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) in igb_rar_set() argument
360 /* HW expects these in little endian so we reverse the byte order in igb_rar_set()
373 /* Some bridges will combine consecutive 32-bit writes into in igb_rar_set()
384 * igb_mta_set - Set multicast filter table address
385 * @hw: pointer to the HW structure
388 * The multicast table address is a register array of 32-bit registers.
393 void igb_mta_set(struct e1000_hw *hw, u32 hash_value) in igb_mta_set() argument
397 /* The MTA is a register array of 32-bit registers. It is in igb_mta_set()
401 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a in igb_mta_set()
406 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); in igb_mta_set()
418 * igb_hash_mc_addr - Generate a multicast hash value
419 * @hw: pointer to the HW structure
426 static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) in igb_hash_mc_addr() argument
432 hash_mask = (hw->mac.mta_reg_count * 32) - 1; in igb_hash_mc_addr()
434 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts in igb_hash_mc_addr()
444 * left-shifts where the MSB of mc_addr[5] would still fall within in igb_hash_mc_addr()
447 * remaining number of bits. Thus 8 - bit_shift. The rest of the in igb_hash_mc_addr()
450 * 8-bit shifting total. in igb_hash_mc_addr()
453 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), in igb_hash_mc_addr()
465 switch (hw->mac.mc_filter_type) { in igb_hash_mc_addr()
480 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | in igb_hash_mc_addr()
487 * igb_update_mc_addr_list - Update Multicast addresses
488 * @hw: pointer to the HW structure
495 void igb_update_mc_addr_list(struct e1000_hw *hw, in igb_update_mc_addr_list() argument
502 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in igb_update_mc_addr_list()
506 hash_value = igb_hash_mc_addr(hw, mc_addr_list); in igb_update_mc_addr_list()
508 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); in igb_update_mc_addr_list()
511 hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); in igb_update_mc_addr_list()
516 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) in igb_update_mc_addr_list()
517 array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]); in igb_update_mc_addr_list()
522 * igb_clear_hw_cntrs_base - Clear base hardware counters
523 * @hw: pointer to the HW structure
527 void igb_clear_hw_cntrs_base(struct e1000_hw *hw) in igb_clear_hw_cntrs_base() argument
569 * igb_check_for_copper_link - Check for link (Copper)
570 * @hw: pointer to the HW structure
576 s32 igb_check_for_copper_link(struct e1000_hw *hw) in igb_check_for_copper_link() argument
578 struct e1000_mac_info *mac = &hw->mac; in igb_check_for_copper_link()
582 /* We only want to go out to the PHY registers to see if Auto-Neg in igb_check_for_copper_link()
587 if (!mac->get_link_status) { in igb_check_for_copper_link()
596 ret_val = igb_phy_has_link(hw, 1, 0, &link); in igb_check_for_copper_link()
603 mac->get_link_status = false; in igb_check_for_copper_link()
606 * immediately after link-up in igb_check_for_copper_link()
608 igb_check_downshift(hw); in igb_check_for_copper_link()
613 if (!mac->autoneg) { in igb_check_for_copper_link()
614 ret_val = -E1000_ERR_CONFIG; in igb_check_for_copper_link()
618 /* Auto-Neg is enabled. Auto Speed Detection takes care in igb_check_for_copper_link()
622 igb_config_collision_dist(hw); in igb_check_for_copper_link()
624 /* Configure Flow Control now that Auto-Neg has completed. in igb_check_for_copper_link()
625 * First, we need to restore the desired flow control in igb_check_for_copper_link()
626 * settings because we may have had to re-autoneg with a in igb_check_for_copper_link()
629 ret_val = igb_config_fc_after_link_up(hw); in igb_check_for_copper_link()
631 hw_dbg("Error configuring flow control\n"); in igb_check_for_copper_link()
638 * igb_setup_link - Setup flow control and link settings
639 * @hw: pointer to the HW structure
641 * Determines which flow control settings to use, then configures flow
642 * control. Calls the appropriate media-specific link configuration
647 s32 igb_setup_link(struct e1000_hw *hw) in igb_setup_link() argument
654 if (igb_check_reset_block(hw)) in igb_setup_link()
657 /* If requested flow control is set to default, set flow control in igb_setup_link()
658 * based on the EEPROM flow control settings. in igb_setup_link()
660 if (hw->fc.requested_mode == e1000_fc_default) { in igb_setup_link()
661 ret_val = igb_set_default_fc(hw); in igb_setup_link()
666 /* We want to save off the original Flow Control configuration just in igb_setup_link()
668 * hub or switch with different Flow Control capabilities. in igb_setup_link()
670 hw->fc.current_mode = hw->fc.requested_mode; in igb_setup_link()
672 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); in igb_setup_link()
675 ret_val = hw->mac.ops.setup_physical_interface(hw); in igb_setup_link()
679 /* Initialize the flow control address, type, and PAUSE timer in igb_setup_link()
680 * registers to their default values. This is done even if flow in igb_setup_link()
684 hw_dbg("Initializing the Flow Control address, type and timer regs\n"); in igb_setup_link()
689 wr32(E1000_FCTTV, hw->fc.pause_time); in igb_setup_link()
691 igb_set_fc_watermarks(hw); in igb_setup_link()
699 * igb_config_collision_dist - Configure collision distance
700 * @hw: pointer to the HW structure
706 void igb_config_collision_dist(struct e1000_hw *hw) in igb_config_collision_dist() argument
720 * igb_set_fc_watermarks - Set flow control high/low watermarks
721 * @hw: pointer to the HW structure
723 * Sets the flow control high/low threshold (watermark) registers. If
724 * flow control XON frame transmission is enabled, then set XON frame
727 static void igb_set_fc_watermarks(struct e1000_hw *hw) in igb_set_fc_watermarks() argument
731 /* Set the flow control receive threshold registers. Normally, in igb_set_fc_watermarks()
737 if (hw->fc.current_mode & e1000_fc_tx_pause) { in igb_set_fc_watermarks()
742 fcrtl = hw->fc.low_water; in igb_set_fc_watermarks()
743 if (hw->fc.send_xon) in igb_set_fc_watermarks()
746 fcrth = hw->fc.high_water; in igb_set_fc_watermarks()
753 * igb_set_default_fc - Set flow control default values
754 * @hw: pointer to the HW structure
756 * Read the EEPROM for the default values for flow control and store the
759 static s32 igb_set_default_fc(struct e1000_hw *hw) in igb_set_default_fc() argument
766 * that determine the hardware's default PAUSE (flow control) mode, in igb_set_default_fc()
767 * a bit that determines whether the HW defaults to enabling or in igb_set_default_fc()
768 * disabling auto-negotiation, and the direction of the in igb_set_default_fc()
769 * SW defined pins. If there is no SW over-ride of the flow in igb_set_default_fc()
770 * control setting, then the variable hw->fc will in igb_set_default_fc()
773 if (hw->mac.type == e1000_i350) in igb_set_default_fc()
774 lan_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); in igb_set_default_fc()
778 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG + lan_offset, in igb_set_default_fc()
786 hw->fc.requested_mode = e1000_fc_none; in igb_set_default_fc()
788 hw->fc.requested_mode = e1000_fc_tx_pause; in igb_set_default_fc()
790 hw->fc.requested_mode = e1000_fc_full; in igb_set_default_fc()
797 * igb_force_mac_fc - Force the MAC's flow control settings
798 * @hw: pointer to the HW structure
800 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
806 s32 igb_force_mac_fc(struct e1000_hw *hw) in igb_force_mac_fc() argument
808 u32 ctrl; in igb_force_mac_fc() local
811 ctrl = rd32(E1000_CTRL); in igb_force_mac_fc()
813 /* Because we didn't get link via the internal auto-negotiation in igb_force_mac_fc()
815 * auto-neg), we have to manually enable/disable transmit an in igb_force_mac_fc()
816 * receive flow control. in igb_force_mac_fc()
818 * The "Case" statement below enables/disable flow control in igb_force_mac_fc()
819 * according to the "hw->fc.current_mode" parameter. in igb_force_mac_fc()
822 * 0: Flow control is completely disabled in igb_force_mac_fc()
823 * 1: Rx flow control is enabled (we can receive pause in igb_force_mac_fc()
825 * 2: Tx flow control is enabled (we can send pause frames in igb_force_mac_fc()
827 * 3: Both Rx and TX flow control (symmetric) is enabled. in igb_force_mac_fc()
830 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); in igb_force_mac_fc()
832 switch (hw->fc.current_mode) { in igb_force_mac_fc()
834 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); in igb_force_mac_fc()
837 ctrl &= (~E1000_CTRL_TFCE); in igb_force_mac_fc()
838 ctrl |= E1000_CTRL_RFCE; in igb_force_mac_fc()
841 ctrl &= (~E1000_CTRL_RFCE); in igb_force_mac_fc()
842 ctrl |= E1000_CTRL_TFCE; in igb_force_mac_fc()
845 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); in igb_force_mac_fc()
848 hw_dbg("Flow control param set incorrectly\n"); in igb_force_mac_fc()
849 ret_val = -E1000_ERR_CONFIG; in igb_force_mac_fc()
853 wr32(E1000_CTRL, ctrl); in igb_force_mac_fc()
860 * igb_config_fc_after_link_up - Configures flow control after link
861 * @hw: pointer to the HW structure
863 * Checks the status of auto-negotiation after link up to ensure that the
865 * flow control needs to be forced also. If auto-negotiation is enabled
866 * and did not fail, then we configure flow control based on our link
869 s32 igb_config_fc_after_link_up(struct e1000_hw *hw) in igb_config_fc_after_link_up() argument
871 struct e1000_mac_info *mac = &hw->mac; in igb_config_fc_after_link_up()
877 /* Check for the case where we have fiber media and auto-neg failed in igb_config_fc_after_link_up()
881 if (mac->autoneg_failed) { in igb_config_fc_after_link_up()
882 if (hw->phy.media_type == e1000_media_type_internal_serdes) in igb_config_fc_after_link_up()
883 ret_val = igb_force_mac_fc(hw); in igb_config_fc_after_link_up()
885 if (hw->phy.media_type == e1000_media_type_copper) in igb_config_fc_after_link_up()
886 ret_val = igb_force_mac_fc(hw); in igb_config_fc_after_link_up()
890 hw_dbg("Error forcing flow control settings\n"); in igb_config_fc_after_link_up()
894 /* Check for the case where we have copper media and auto-neg is in igb_config_fc_after_link_up()
895 * enabled. In this case, we need to check and see if Auto-Neg in igb_config_fc_after_link_up()
897 * flow control configured. in igb_config_fc_after_link_up()
899 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { in igb_config_fc_after_link_up()
904 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igb_config_fc_after_link_up()
908 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, in igb_config_fc_after_link_up()
922 * flow control was negotiated. in igb_config_fc_after_link_up()
924 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, in igb_config_fc_after_link_up()
928 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, in igb_config_fc_after_link_up()
935 * Page Ability Register (Address 5) determine flow control in igb_config_fc_after_link_up()
938 * 1999, describes these PAUSE resolution bits and how flow in igb_config_fc_after_link_up()
944 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
955 * Symmetric Flow Control is enabled at both ends. The in igb_config_fc_after_link_up()
958 * For Symmetric Flow Control: in igb_config_fc_after_link_up()
962 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
970 * FULL flow control because we could not advertise RX in igb_config_fc_after_link_up()
974 if (hw->fc.requested_mode == e1000_fc_full) { in igb_config_fc_after_link_up()
975 hw->fc.current_mode = e1000_fc_full; in igb_config_fc_after_link_up()
976 hw_dbg("Flow Control = FULL.\n"); in igb_config_fc_after_link_up()
978 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
979 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igb_config_fc_after_link_up()
986 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
993 hw->fc.current_mode = e1000_fc_tx_pause; in igb_config_fc_after_link_up()
994 hw_dbg("Flow Control = TX PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1000 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1007 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1008 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1010 /* Per the IEEE spec, at this point flow control should be in igb_config_fc_after_link_up()
1013 * desired flow control, but can be forced on the link in igb_config_fc_after_link_up()
1014 * partner. So if we advertised no flow control, that is in igb_config_fc_after_link_up()
1016 * receive capability (Rx Pause Only or Full Flow Control) in igb_config_fc_after_link_up()
1018 * ourselves to enable Rx Flow Control only. We can do in igb_config_fc_after_link_up()
1020 * didn't want flow control enabled, and we enable Rx, no in igb_config_fc_after_link_up()
1023 * flow control enabled, then by us enabling RX only, we in igb_config_fc_after_link_up()
1030 else if ((hw->fc.requested_mode == e1000_fc_none) || in igb_config_fc_after_link_up()
1031 (hw->fc.requested_mode == e1000_fc_tx_pause) || in igb_config_fc_after_link_up()
1032 (hw->fc.strict_ieee)) { in igb_config_fc_after_link_up()
1033 hw->fc.current_mode = e1000_fc_none; in igb_config_fc_after_link_up()
1034 hw_dbg("Flow Control = NONE.\n"); in igb_config_fc_after_link_up()
1036 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1037 hw_dbg("Flow Control = RX PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1040 /* Now we need to do one last check... If we auto- in igb_config_fc_after_link_up()
1041 * negotiated to HALF DUPLEX, flow control should not be in igb_config_fc_after_link_up()
1044 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); in igb_config_fc_after_link_up()
1051 hw->fc.current_mode = e1000_fc_none; in igb_config_fc_after_link_up()
1054 * controller to use the correct flow control settings. in igb_config_fc_after_link_up()
1056 ret_val = igb_force_mac_fc(hw); in igb_config_fc_after_link_up()
1058 hw_dbg("Error forcing flow control settings\n"); in igb_config_fc_after_link_up()
1062 /* Check for the case where we have SerDes media and auto-neg is in igb_config_fc_after_link_up()
1063 * enabled. In this case, we need to check and see if Auto-Neg in igb_config_fc_after_link_up()
1065 * flow control configured. in igb_config_fc_after_link_up()
1067 if ((hw->phy.media_type == e1000_media_type_internal_serdes) in igb_config_fc_after_link_up()
1068 && mac->autoneg) { in igb_config_fc_after_link_up()
1083 * flow control was negotiated. in igb_config_fc_after_link_up()
1090 * Page Ability Register (PCS_LPAB) determine flow control in igb_config_fc_after_link_up()
1093 * 1999, describes these PAUSE resolution bits and how flow in igb_config_fc_after_link_up()
1099 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1110 * Symmetric Flow Control is enabled at both ends. The in igb_config_fc_after_link_up()
1113 * For Symmetric Flow Control: in igb_config_fc_after_link_up()
1117 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1125 * FULL flow control because we could not advertise Rx in igb_config_fc_after_link_up()
1129 if (hw->fc.requested_mode == e1000_fc_full) { in igb_config_fc_after_link_up()
1130 hw->fc.current_mode = e1000_fc_full; in igb_config_fc_after_link_up()
1131 hw_dbg("Flow Control = FULL.\n"); in igb_config_fc_after_link_up()
1133 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1134 hw_dbg("Flow Control = Rx PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1141 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1148 hw->fc.current_mode = e1000_fc_tx_pause; in igb_config_fc_after_link_up()
1149 hw_dbg("Flow Control = Tx PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1155 *-------|---------|-------|---------|-------------------- in igb_config_fc_after_link_up()
1162 hw->fc.current_mode = e1000_fc_rx_pause; in igb_config_fc_after_link_up()
1163 hw_dbg("Flow Control = Rx PAUSE frames only.\n"); in igb_config_fc_after_link_up()
1165 /* Per the IEEE spec, at this point flow control in igb_config_fc_after_link_up()
1168 hw->fc.current_mode = e1000_fc_none; in igb_config_fc_after_link_up()
1169 hw_dbg("Flow Control = NONE.\n"); in igb_config_fc_after_link_up()
1173 * controller to use the correct flow control settings. in igb_config_fc_after_link_up()
1179 ret_val = igb_force_mac_fc(hw); in igb_config_fc_after_link_up()
1181 hw_dbg("Error forcing flow control settings\n"); in igb_config_fc_after_link_up()
1191 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1192 * @hw: pointer to the HW structure
1199 s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, in igb_get_speed_and_duplex_copper() argument
1228 * igb_get_hw_semaphore - Acquire hardware semaphore
1229 * @hw: pointer to the HW structure
1231 * Acquire the HW semaphore to access the PHY or NVM
1233 s32 igb_get_hw_semaphore(struct e1000_hw *hw) in igb_get_hw_semaphore() argument
1237 s32 timeout = hw->nvm.word_size + 1; in igb_get_hw_semaphore()
1251 hw_dbg("Driver can't access device - SMBI bit is set.\n"); in igb_get_hw_semaphore()
1252 ret_val = -E1000_ERR_NVM; in igb_get_hw_semaphore()
1270 igb_put_hw_semaphore(hw); in igb_get_hw_semaphore()
1272 ret_val = -E1000_ERR_NVM; in igb_get_hw_semaphore()
1281 * igb_put_hw_semaphore - Release hardware semaphore
1282 * @hw: pointer to the HW structure
1286 void igb_put_hw_semaphore(struct e1000_hw *hw) in igb_put_hw_semaphore() argument
1298 * igb_get_auto_rd_done - Check for auto read completion
1299 * @hw: pointer to the HW structure
1303 s32 igb_get_auto_rd_done(struct e1000_hw *hw) in igb_get_auto_rd_done() argument
1317 hw_dbg("Auto read by HW from NVM has not completed.\n"); in igb_get_auto_rd_done()
1318 ret_val = -E1000_ERR_RESET; in igb_get_auto_rd_done()
1327 * igb_valid_led_default - Verify a valid default LED config
1328 * @hw: pointer to the HW structure
1334 static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data) in igb_valid_led_default() argument
1338 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); in igb_valid_led_default()
1345 switch (hw->phy.media_type) { in igb_valid_led_default()
1360 * igb_id_led_init -
1361 * @hw: pointer to the HW structure
1364 s32 igb_id_led_init(struct e1000_hw *hw) in igb_id_led_init() argument
1366 struct e1000_mac_info *mac = &hw->mac; in igb_id_led_init()
1375 if ((hw->mac.type == e1000_i210) || in igb_id_led_init()
1376 (hw->mac.type == e1000_i211)) in igb_id_led_init()
1377 ret_val = igb_valid_led_default_i210(hw, &data); in igb_id_led_init()
1379 ret_val = igb_valid_led_default(hw, &data); in igb_id_led_init()
1384 mac->ledctl_default = rd32(E1000_LEDCTL); in igb_id_led_init()
1385 mac->ledctl_mode1 = mac->ledctl_default; in igb_id_led_init()
1386 mac->ledctl_mode2 = mac->ledctl_default; in igb_id_led_init()
1394 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); in igb_id_led_init()
1395 mac->ledctl_mode1 |= ledctl_on << (i << 3); in igb_id_led_init()
1400 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); in igb_id_led_init()
1401 mac->ledctl_mode1 |= ledctl_off << (i << 3); in igb_id_led_init()
1411 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); in igb_id_led_init()
1412 mac->ledctl_mode2 |= ledctl_on << (i << 3); in igb_id_led_init()
1417 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); in igb_id_led_init()
1418 mac->ledctl_mode2 |= ledctl_off << (i << 3); in igb_id_led_init()
1431 * igb_cleanup_led - Set LED config to default operation
1432 * @hw: pointer to the HW structure
1437 s32 igb_cleanup_led(struct e1000_hw *hw) in igb_cleanup_led() argument
1439 wr32(E1000_LEDCTL, hw->mac.ledctl_default); in igb_cleanup_led()
1444 * igb_blink_led - Blink LED
1445 * @hw: pointer to the HW structure
1449 s32 igb_blink_led(struct e1000_hw *hw) in igb_blink_led() argument
1454 if (hw->phy.media_type == e1000_media_type_fiber) { in igb_blink_led()
1455 /* always blink LED0 for PCI-E fiber */ in igb_blink_led()
1465 ledctl_blink = hw->mac.ledctl_mode2; in igb_blink_led()
1467 u32 mode = (hw->mac.ledctl_mode2 >> i) & in igb_blink_led()
1469 u32 led_default = hw->mac.ledctl_default >> i; in igb_blink_led()
1489 * igb_led_off - Turn LED off
1490 * @hw: pointer to the HW structure
1494 s32 igb_led_off(struct e1000_hw *hw) in igb_led_off() argument
1496 switch (hw->phy.media_type) { in igb_led_off()
1498 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); in igb_led_off()
1508 * igb_disable_pcie_master - Disables PCI-express master access
1509 * @hw: pointer to the HW structure
1511 * Returns 0 (0) if successful, else returns -10
1512 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1515 * Disables PCI-Express master access and verifies there are no pending
1518 s32 igb_disable_pcie_master(struct e1000_hw *hw) in igb_disable_pcie_master() argument
1520 u32 ctrl; in igb_disable_pcie_master() local
1524 if (hw->bus.type != e1000_bus_type_pci_express) in igb_disable_pcie_master()
1527 ctrl = rd32(E1000_CTRL); in igb_disable_pcie_master()
1528 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; in igb_disable_pcie_master()
1529 wr32(E1000_CTRL, ctrl); in igb_disable_pcie_master()
1536 timeout--; in igb_disable_pcie_master()
1541 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; in igb_disable_pcie_master()
1550 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1551 * @hw: pointer to the HW structure
1553 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1556 s32 igb_validate_mdi_setting(struct e1000_hw *hw) in igb_validate_mdi_setting() argument
1561 if (hw->mac.type >= e1000_82580) in igb_validate_mdi_setting()
1564 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { in igb_validate_mdi_setting()
1566 hw->phy.mdix = 1; in igb_validate_mdi_setting()
1567 ret_val = -E1000_ERR_CONFIG; in igb_validate_mdi_setting()
1576 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1577 * @hw: pointer to the HW structure
1586 s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, in igb_write_8bit_ctrl_reg() argument
1605 ret_val = -E1000_ERR_PHY; in igb_write_8bit_ctrl_reg()
1614 * igb_enable_mng_pass_thru - Enable processing of ARP's
1615 * @hw: pointer to the HW structure
1620 bool igb_enable_mng_pass_thru(struct e1000_hw *hw) in igb_enable_mng_pass_thru() argument
1626 if (!hw->mac.asf_firmware_present) in igb_enable_mng_pass_thru()
1634 if (hw->mac.arc_subsystem_valid) { in igb_enable_mng_pass_thru()