Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
46 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
47 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
48 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
49 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
50 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
51 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
55 /* Due to a hw errata, if the host tries to configure the VFTA register
61 * igb_write_vfta_i350 - Write value to VLAN filter table
62 * @hw: pointer to the HW structure
69 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) in igb_write_vfta_i350() argument
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
83 * @hw: pointer to the HW structure
88 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) in igb_sgmii_uses_mdio_82575() argument
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
115 * @hw: pointer to the HW structure
119 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) in igb_check_for_link_media_swap() argument
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); in igb_check_for_link_media_swap()
139 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); in igb_check_for_link_media_swap()
143 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); in igb_check_for_link_media_swap()
152 if (port && (hw->dev_spec._82575.media_port != port)) { in igb_check_for_link_media_swap()
153 hw->dev_spec._82575.media_port = port; in igb_check_for_link_media_swap()
154 hw->dev_spec._82575.media_changed = true; in igb_check_for_link_media_swap()
159 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
162 igb_check_for_link_82575(hw); in igb_check_for_link_media_swap()
164 igb_check_for_link_82575(hw); in igb_check_for_link_media_swap()
166 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
175 * igb_init_phy_params_82575 - Init PHY func ptrs.
176 * @hw: pointer to the HW structure
178 static s32 igb_init_phy_params_82575(struct e1000_hw *hw) in igb_init_phy_params_82575() argument
180 struct e1000_phy_info *phy = &hw->phy; in igb_init_phy_params_82575()
184 if (hw->phy.media_type != e1000_media_type_copper) { in igb_init_phy_params_82575()
185 phy->type = e1000_phy_none; in igb_init_phy_params_82575()
189 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in igb_init_phy_params_82575()
190 phy->reset_delay_us = 100; in igb_init_phy_params_82575()
194 if (igb_sgmii_active_82575(hw)) { in igb_init_phy_params_82575()
195 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; in igb_init_phy_params_82575()
198 phy->ops.reset = igb_phy_hw_reset; in igb_init_phy_params_82575()
203 igb_reset_mdicnfg_82580(hw); in igb_init_phy_params_82575()
205 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { in igb_init_phy_params_82575()
206 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; in igb_init_phy_params_82575()
207 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; in igb_init_phy_params_82575()
209 switch (hw->mac.type) { in igb_init_phy_params_82575()
215 phy->ops.read_reg = igb_read_phy_reg_82580; in igb_init_phy_params_82575()
216 phy->ops.write_reg = igb_write_phy_reg_82580; in igb_init_phy_params_82575()
219 phy->ops.read_reg = igb_read_phy_reg_igp; in igb_init_phy_params_82575()
220 phy->ops.write_reg = igb_write_phy_reg_igp; in igb_init_phy_params_82575()
225 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> in igb_init_phy_params_82575()
228 /* Set phy->phy_addr and phy->id. */ in igb_init_phy_params_82575()
229 ret_val = igb_get_phy_id_82575(hw); in igb_init_phy_params_82575()
234 switch (phy->id) { in igb_init_phy_params_82575()
240 phy->type = e1000_phy_m88; in igb_init_phy_params_82575()
241 phy->ops.check_polarity = igb_check_polarity_m88; in igb_init_phy_params_82575()
242 phy->ops.get_phy_info = igb_get_phy_info_m88; in igb_init_phy_params_82575()
243 if (phy->id != M88E1111_I_PHY_ID) in igb_init_phy_params_82575()
244 phy->ops.get_cable_length = in igb_init_phy_params_82575()
247 phy->ops.get_cable_length = igb_get_cable_length_m88; in igb_init_phy_params_82575()
248 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; in igb_init_phy_params_82575()
250 if (phy->id == M88E1112_E_PHY_ID) { in igb_init_phy_params_82575()
253 ret_val = phy->ops.write_reg(hw, in igb_init_phy_params_82575()
259 ret_val = phy->ops.read_reg(hw, in igb_init_phy_params_82575()
269 hw->mac.ops.check_for_link = in igb_init_phy_params_82575()
272 if (phy->id == M88E1512_E_PHY_ID) { in igb_init_phy_params_82575()
273 ret_val = igb_initialize_M88E1512_phy(hw); in igb_init_phy_params_82575()
277 if (phy->id == M88E1543_E_PHY_ID) { in igb_init_phy_params_82575()
278 ret_val = igb_initialize_M88E1543_phy(hw); in igb_init_phy_params_82575()
284 phy->type = e1000_phy_igp_3; in igb_init_phy_params_82575()
285 phy->ops.get_phy_info = igb_get_phy_info_igp; in igb_init_phy_params_82575()
286 phy->ops.get_cable_length = igb_get_cable_length_igp_2; in igb_init_phy_params_82575()
287 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; in igb_init_phy_params_82575()
288 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; in igb_init_phy_params_82575()
289 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; in igb_init_phy_params_82575()
293 phy->type = e1000_phy_82580; in igb_init_phy_params_82575()
294 phy->ops.force_speed_duplex = in igb_init_phy_params_82575()
296 phy->ops.get_cable_length = igb_get_cable_length_82580; in igb_init_phy_params_82575()
297 phy->ops.get_phy_info = igb_get_phy_info_82580; in igb_init_phy_params_82575()
298 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; in igb_init_phy_params_82575()
299 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; in igb_init_phy_params_82575()
302 phy->type = e1000_phy_i210; in igb_init_phy_params_82575()
303 phy->ops.check_polarity = igb_check_polarity_m88; in igb_init_phy_params_82575()
304 phy->ops.get_cfg_done = igb_get_cfg_done_i210; in igb_init_phy_params_82575()
305 phy->ops.get_phy_info = igb_get_phy_info_m88; in igb_init_phy_params_82575()
306 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; in igb_init_phy_params_82575()
307 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; in igb_init_phy_params_82575()
308 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; in igb_init_phy_params_82575()
309 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; in igb_init_phy_params_82575()
312 phy->type = e1000_phy_bcm54616; in igb_init_phy_params_82575()
315 ret_val = -E1000_ERR_PHY; in igb_init_phy_params_82575()
324 * igb_init_nvm_params_82575 - Init NVM func ptrs.
325 * @hw: pointer to the HW structure
327 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) in igb_init_nvm_params_82575() argument
329 struct e1000_nvm_info *nvm = &hw->nvm; in igb_init_nvm_params_82575()
336 /* Added to a constant, "size" becomes the left-shift value in igb_init_nvm_params_82575()
347 nvm->word_size = BIT(size); in igb_init_nvm_params_82575()
348 nvm->opcode_bits = 8; in igb_init_nvm_params_82575()
349 nvm->delay_usec = 1; in igb_init_nvm_params_82575()
351 switch (nvm->override) { in igb_init_nvm_params_82575()
353 nvm->page_size = 32; in igb_init_nvm_params_82575()
354 nvm->address_bits = 16; in igb_init_nvm_params_82575()
357 nvm->page_size = 8; in igb_init_nvm_params_82575()
358 nvm->address_bits = 8; in igb_init_nvm_params_82575()
361 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; in igb_init_nvm_params_82575()
362 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? in igb_init_nvm_params_82575()
366 if (nvm->word_size == BIT(15)) in igb_init_nvm_params_82575()
367 nvm->page_size = 128; in igb_init_nvm_params_82575()
369 nvm->type = e1000_nvm_eeprom_spi; in igb_init_nvm_params_82575()
372 nvm->ops.acquire = igb_acquire_nvm_82575; in igb_init_nvm_params_82575()
373 nvm->ops.release = igb_release_nvm_82575; in igb_init_nvm_params_82575()
374 nvm->ops.write = igb_write_nvm_spi; in igb_init_nvm_params_82575()
375 nvm->ops.validate = igb_validate_nvm_checksum; in igb_init_nvm_params_82575()
376 nvm->ops.update = igb_update_nvm_checksum; in igb_init_nvm_params_82575()
377 if (nvm->word_size < BIT(15)) in igb_init_nvm_params_82575()
378 nvm->ops.read = igb_read_nvm_eerd; in igb_init_nvm_params_82575()
380 nvm->ops.read = igb_read_nvm_spi; in igb_init_nvm_params_82575()
383 switch (hw->mac.type) { in igb_init_nvm_params_82575()
385 nvm->ops.validate = igb_validate_nvm_checksum_82580; in igb_init_nvm_params_82575()
386 nvm->ops.update = igb_update_nvm_checksum_82580; in igb_init_nvm_params_82575()
390 nvm->ops.validate = igb_validate_nvm_checksum_i350; in igb_init_nvm_params_82575()
391 nvm->ops.update = igb_update_nvm_checksum_i350; in igb_init_nvm_params_82575()
401 * igb_init_mac_params_82575 - Init MAC func ptrs.
402 * @hw: pointer to the HW structure
404 static s32 igb_init_mac_params_82575(struct e1000_hw *hw) in igb_init_mac_params_82575() argument
406 struct e1000_mac_info *mac = &hw->mac; in igb_init_mac_params_82575()
407 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_init_mac_params_82575()
410 mac->mta_reg_count = 128; in igb_init_mac_params_82575()
412 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; in igb_init_mac_params_82575()
414 switch (mac->type) { in igb_init_mac_params_82575()
416 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; in igb_init_mac_params_82575()
419 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; in igb_init_mac_params_82575()
423 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; in igb_init_mac_params_82575()
426 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; in igb_init_mac_params_82575()
430 if (mac->type >= e1000_82580) in igb_init_mac_params_82575()
431 mac->ops.reset_hw = igb_reset_hw_82580; in igb_init_mac_params_82575()
433 mac->ops.reset_hw = igb_reset_hw_82575; in igb_init_mac_params_82575()
435 if (mac->type >= e1000_i210) { in igb_init_mac_params_82575()
436 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; in igb_init_mac_params_82575()
437 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; in igb_init_mac_params_82575()
440 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; in igb_init_mac_params_82575()
441 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; in igb_init_mac_params_82575()
444 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) in igb_init_mac_params_82575()
445 mac->ops.write_vfta = igb_write_vfta_i350; in igb_init_mac_params_82575()
447 mac->ops.write_vfta = igb_write_vfta; in igb_init_mac_params_82575()
450 mac->asf_firmware_present = true; in igb_init_mac_params_82575()
452 mac->arc_subsystem_valid = in igb_init_mac_params_82575()
456 if (mac->type >= e1000_i350) in igb_init_mac_params_82575()
457 dev_spec->eee_disable = false; in igb_init_mac_params_82575()
459 dev_spec->eee_disable = true; in igb_init_mac_params_82575()
461 if (mac->type >= e1000_i210) in igb_init_mac_params_82575()
462 dev_spec->clear_semaphore_once = true; in igb_init_mac_params_82575()
464 mac->ops.setup_physical_interface = in igb_init_mac_params_82575()
465 (hw->phy.media_type == e1000_media_type_copper) in igb_init_mac_params_82575()
469 if (mac->type == e1000_82580 || mac->type == e1000_i350) { in igb_init_mac_params_82575()
470 switch (hw->device_id) { in igb_init_mac_params_82575()
478 hw->dev_spec._82575.mas_capable = true; in igb_init_mac_params_82575()
486 * igb_set_sfp_media_type_82575 - derives SFP module media type.
487 * @hw: pointer to the HW structure
492 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) in igb_set_sfp_media_type_82575() argument
496 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_set_sfp_media_type_82575()
497 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; in igb_set_sfp_media_type_82575()
510 ret_val = igb_read_sfp_data_byte(hw, in igb_set_sfp_media_type_82575()
516 timeout--; in igb_set_sfp_media_type_82575()
521 ret_val = igb_read_sfp_data_byte(hw, in igb_set_sfp_media_type_82575()
530 dev_spec->module_plugged = true; in igb_set_sfp_media_type_82575()
531 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { in igb_set_sfp_media_type_82575()
532 hw->phy.media_type = e1000_media_type_internal_serdes; in igb_set_sfp_media_type_82575()
533 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) { in igb_set_sfp_media_type_82575()
534 dev_spec->sgmii_active = true; in igb_set_sfp_media_type_82575()
535 hw->phy.media_type = e1000_media_type_internal_serdes; in igb_set_sfp_media_type_82575()
536 } else if (eth_flags->e1000_base_t) { in igb_set_sfp_media_type_82575()
537 dev_spec->sgmii_active = true; in igb_set_sfp_media_type_82575()
538 hw->phy.media_type = e1000_media_type_copper; in igb_set_sfp_media_type_82575()
540 hw->phy.media_type = e1000_media_type_unknown; in igb_set_sfp_media_type_82575()
545 hw->phy.media_type = e1000_media_type_unknown; in igb_set_sfp_media_type_82575()
554 static s32 igb_get_invariants_82575(struct e1000_hw *hw) in igb_get_invariants_82575() argument
556 struct e1000_mac_info *mac = &hw->mac; in igb_get_invariants_82575()
557 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_get_invariants_82575()
562 switch (hw->device_id) { in igb_get_invariants_82575()
566 mac->type = e1000_82575; in igb_get_invariants_82575()
576 mac->type = e1000_82576; in igb_get_invariants_82575()
588 mac->type = e1000_82580; in igb_get_invariants_82575()
594 mac->type = e1000_i350; in igb_get_invariants_82575()
602 mac->type = e1000_i210; in igb_get_invariants_82575()
605 mac->type = e1000_i211; in igb_get_invariants_82575()
610 mac->type = e1000_i354; in igb_get_invariants_82575()
613 return -E1000_ERR_MAC_INIT; in igb_get_invariants_82575()
623 hw->phy.media_type = e1000_media_type_copper; in igb_get_invariants_82575()
624 dev_spec->sgmii_active = false; in igb_get_invariants_82575()
625 dev_spec->module_plugged = false; in igb_get_invariants_82575()
632 hw->phy.media_type = e1000_media_type_internal_serdes; in igb_get_invariants_82575()
636 if (igb_sgmii_uses_mdio_82575(hw)) { in igb_get_invariants_82575()
637 hw->phy.media_type = e1000_media_type_copper; in igb_get_invariants_82575()
638 dev_spec->sgmii_active = true; in igb_get_invariants_82575()
644 ret_val = igb_set_sfp_media_type_82575(hw); in igb_get_invariants_82575()
646 (hw->phy.media_type == e1000_media_type_unknown)) { in igb_get_invariants_82575()
650 hw->phy.media_type = e1000_media_type_internal_serdes; in igb_get_invariants_82575()
653 hw->phy.media_type = e1000_media_type_copper; in igb_get_invariants_82575()
654 dev_spec->sgmii_active = true; in igb_get_invariants_82575()
663 if (dev_spec->sgmii_active) in igb_get_invariants_82575()
676 ret_val = igb_init_mac_params_82575(hw); in igb_get_invariants_82575()
681 ret_val = igb_init_nvm_params_82575(hw); in igb_get_invariants_82575()
682 switch (hw->mac.type) { in igb_get_invariants_82575()
685 ret_val = igb_init_nvm_params_i210(hw); in igb_get_invariants_82575()
694 /* if part supports SR-IOV then initialize mailbox parameters */ in igb_get_invariants_82575()
695 switch (mac->type) { in igb_get_invariants_82575()
698 igb_init_mbx_params_pf(hw); in igb_get_invariants_82575()
705 ret_val = igb_init_phy_params_82575(hw); in igb_get_invariants_82575()
712 * igb_acquire_phy_82575 - Acquire rights to access PHY
713 * @hw: pointer to the HW structure
718 static s32 igb_acquire_phy_82575(struct e1000_hw *hw) in igb_acquire_phy_82575() argument
722 if (hw->bus.func == E1000_FUNC_1) in igb_acquire_phy_82575()
724 else if (hw->bus.func == E1000_FUNC_2) in igb_acquire_phy_82575()
726 else if (hw->bus.func == E1000_FUNC_3) in igb_acquire_phy_82575()
729 return hw->mac.ops.acquire_swfw_sync(hw, mask); in igb_acquire_phy_82575()
733 * igb_release_phy_82575 - Release rights to access PHY
734 * @hw: pointer to the HW structure
739 static void igb_release_phy_82575(struct e1000_hw *hw) in igb_release_phy_82575() argument
743 if (hw->bus.func == E1000_FUNC_1) in igb_release_phy_82575()
745 else if (hw->bus.func == E1000_FUNC_2) in igb_release_phy_82575()
747 else if (hw->bus.func == E1000_FUNC_3) in igb_release_phy_82575()
750 hw->mac.ops.release_swfw_sync(hw, mask); in igb_release_phy_82575()
754 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
755 * @hw: pointer to the HW structure
762 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, in igb_read_phy_reg_sgmii_82575() argument
765 s32 ret_val = -E1000_ERR_PARAM; in igb_read_phy_reg_sgmii_82575()
772 ret_val = hw->phy.ops.acquire(hw); in igb_read_phy_reg_sgmii_82575()
776 ret_val = igb_read_phy_reg_i2c(hw, offset, data); in igb_read_phy_reg_sgmii_82575()
778 hw->phy.ops.release(hw); in igb_read_phy_reg_sgmii_82575()
785 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
786 * @hw: pointer to the HW structure
793 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, in igb_write_phy_reg_sgmii_82575() argument
796 s32 ret_val = -E1000_ERR_PARAM; in igb_write_phy_reg_sgmii_82575()
804 ret_val = hw->phy.ops.acquire(hw); in igb_write_phy_reg_sgmii_82575()
808 ret_val = igb_write_phy_reg_i2c(hw, offset, data); in igb_write_phy_reg_sgmii_82575()
810 hw->phy.ops.release(hw); in igb_write_phy_reg_sgmii_82575()
817 * igb_get_phy_id_82575 - Retrieve PHY addr and id
818 * @hw: pointer to the HW structure
823 static s32 igb_get_phy_id_82575(struct e1000_hw *hw) in igb_get_phy_id_82575() argument
825 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id_82575()
832 if (hw->mac.type == e1000_i354) in igb_get_phy_id_82575()
833 igb_get_phy_id(hw); in igb_get_phy_id_82575()
836 * we find one that works. For non-SGMII PHYs in igb_get_phy_id_82575()
838 * work. The result of this function should mean phy->phy_addr in igb_get_phy_id_82575()
839 * and phy->id are set correctly. in igb_get_phy_id_82575()
841 if (!(igb_sgmii_active_82575(hw))) { in igb_get_phy_id_82575()
842 phy->addr = 1; in igb_get_phy_id_82575()
843 ret_val = igb_get_phy_id(hw); in igb_get_phy_id_82575()
847 if (igb_sgmii_uses_mdio_82575(hw)) { in igb_get_phy_id_82575()
848 switch (hw->mac.type) { in igb_get_phy_id_82575()
853 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; in igb_get_phy_id_82575()
862 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; in igb_get_phy_id_82575()
865 ret_val = -E1000_ERR_PHY; in igb_get_phy_id_82575()
868 ret_val = igb_get_phy_id(hw); in igb_get_phy_id_82575()
879 * Therefore, we need to test 1-7 in igb_get_phy_id_82575()
881 for (phy->addr = 1; phy->addr < 8; phy->addr++) { in igb_get_phy_id_82575()
882 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); in igb_get_phy_id_82575()
885 phy_id, phy->addr); in igb_get_phy_id_82575()
892 hw_dbg("PHY address %u was unreadable\n", phy->addr); in igb_get_phy_id_82575()
897 if (phy->addr == 8) { in igb_get_phy_id_82575()
898 phy->addr = 0; in igb_get_phy_id_82575()
899 ret_val = -E1000_ERR_PHY; in igb_get_phy_id_82575()
902 ret_val = igb_get_phy_id(hw); in igb_get_phy_id_82575()
913 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
914 * @hw: pointer to the HW structure
918 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) in igb_phy_hw_reset_sgmii_82575() argument
920 struct e1000_phy_info *phy = &hw->phy; in igb_phy_hw_reset_sgmii_82575()
932 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); in igb_phy_hw_reset_sgmii_82575()
936 ret_val = igb_phy_sw_reset(hw); in igb_phy_hw_reset_sgmii_82575()
940 if (phy->id == M88E1512_E_PHY_ID) in igb_phy_hw_reset_sgmii_82575()
941 ret_val = igb_initialize_M88E1512_phy(hw); in igb_phy_hw_reset_sgmii_82575()
942 if (phy->id == M88E1543_E_PHY_ID) in igb_phy_hw_reset_sgmii_82575()
943 ret_val = igb_initialize_M88E1543_phy(hw); in igb_phy_hw_reset_sgmii_82575()
949 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
950 * @hw: pointer to the HW structure
961 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) in igb_set_d0_lplu_state_82575() argument
963 struct e1000_phy_info *phy = &hw->phy; in igb_set_d0_lplu_state_82575()
967 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); in igb_set_d0_lplu_state_82575()
973 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in igb_set_d0_lplu_state_82575()
979 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in igb_set_d0_lplu_state_82575()
982 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in igb_set_d0_lplu_state_82575()
988 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in igb_set_d0_lplu_state_82575()
995 if (phy->smart_speed == e1000_smart_speed_on) { in igb_set_d0_lplu_state_82575()
996 ret_val = phy->ops.read_reg(hw, in igb_set_d0_lplu_state_82575()
1002 ret_val = phy->ops.write_reg(hw, in igb_set_d0_lplu_state_82575()
1006 } else if (phy->smart_speed == e1000_smart_speed_off) { in igb_set_d0_lplu_state_82575()
1007 ret_val = phy->ops.read_reg(hw, in igb_set_d0_lplu_state_82575()
1013 ret_val = phy->ops.write_reg(hw, in igb_set_d0_lplu_state_82575()
1025 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1026 * @hw: pointer to the HW structure
1037 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) in igb_set_d0_lplu_state_82580() argument
1039 struct e1000_phy_info *phy = &hw->phy; in igb_set_d0_lplu_state_82580()
1057 if (phy->smart_speed == e1000_smart_speed_on) in igb_set_d0_lplu_state_82580()
1059 else if (phy->smart_speed == e1000_smart_speed_off) in igb_set_d0_lplu_state_82580()
1067 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1068 * @hw: pointer to the HW structure
1080 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) in igb_set_d3_lplu_state_82580() argument
1082 struct e1000_phy_info *phy = &hw->phy; in igb_set_d3_lplu_state_82580()
1094 if (phy->smart_speed == e1000_smart_speed_on) in igb_set_d3_lplu_state_82580()
1096 else if (phy->smart_speed == e1000_smart_speed_off) in igb_set_d3_lplu_state_82580()
1098 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || in igb_set_d3_lplu_state_82580()
1099 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || in igb_set_d3_lplu_state_82580()
1100 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { in igb_set_d3_lplu_state_82580()
1111 * igb_acquire_nvm_82575 - Request for access to EEPROM
1112 * @hw: pointer to the HW structure
1117 * EEPROM access and return -E1000_ERR_NVM (-1).
1119 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) in igb_acquire_nvm_82575() argument
1123 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); in igb_acquire_nvm_82575()
1127 ret_val = igb_acquire_nvm(hw); in igb_acquire_nvm_82575()
1130 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); in igb_acquire_nvm_82575()
1137 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1138 * @hw: pointer to the HW structure
1143 static void igb_release_nvm_82575(struct e1000_hw *hw) in igb_release_nvm_82575() argument
1145 igb_release_nvm(hw); in igb_release_nvm_82575()
1146 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); in igb_release_nvm_82575()
1150 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1151 * @hw: pointer to the HW structure
1157 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) in igb_acquire_swfw_sync_82575() argument
1166 if (igb_get_hw_semaphore(hw)) { in igb_acquire_swfw_sync_82575()
1167 ret_val = -E1000_ERR_SWFW_SYNC; in igb_acquire_swfw_sync_82575()
1178 igb_put_hw_semaphore(hw); in igb_acquire_swfw_sync_82575()
1185 ret_val = -E1000_ERR_SWFW_SYNC; in igb_acquire_swfw_sync_82575()
1192 igb_put_hw_semaphore(hw); in igb_acquire_swfw_sync_82575()
1199 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1200 * @hw: pointer to the HW structure
1206 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) in igb_release_swfw_sync_82575() argument
1210 while (igb_get_hw_semaphore(hw) != 0) in igb_release_swfw_sync_82575()
1217 igb_put_hw_semaphore(hw); in igb_release_swfw_sync_82575()
1221 * igb_get_cfg_done_82575 - Read config done bit
1222 * @hw: pointer to the HW structure
1225 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1227 * 0. If we were to return with error, EEPROM-less silicon
1230 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) in igb_get_cfg_done_82575() argument
1235 if (hw->bus.func == 1) in igb_get_cfg_done_82575()
1237 else if (hw->bus.func == E1000_FUNC_2) in igb_get_cfg_done_82575()
1239 else if (hw->bus.func == E1000_FUNC_3) in igb_get_cfg_done_82575()
1246 timeout--; in igb_get_cfg_done_82575()
1253 (hw->phy.type == e1000_phy_igp_3)) in igb_get_cfg_done_82575()
1254 igb_phy_init_script_igp3(hw); in igb_get_cfg_done_82575()
1260 * igb_get_link_up_info_82575 - Get link speed/duplex info
1261 * @hw: pointer to the HW structure
1269 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, in igb_get_link_up_info_82575() argument
1274 if (hw->phy.media_type != e1000_media_type_copper) in igb_get_link_up_info_82575()
1275 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, in igb_get_link_up_info_82575()
1278 ret_val = igb_get_speed_and_duplex_copper(hw, speed, in igb_get_link_up_info_82575()
1285 * igb_check_for_link_82575 - Check for link
1286 * @hw: pointer to the HW structure
1291 static s32 igb_check_for_link_82575(struct e1000_hw *hw) in igb_check_for_link_82575() argument
1296 if (hw->phy.media_type != e1000_media_type_copper) { in igb_check_for_link_82575()
1297 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, in igb_check_for_link_82575()
1303 hw->mac.get_link_status = !hw->mac.serdes_has_link; in igb_check_for_link_82575()
1305 /* Configure Flow Control now that Auto-Neg has completed. in igb_check_for_link_82575()
1306 * First, we need to restore the desired flow control in igb_check_for_link_82575()
1307 * settings because we may have had to re-autoneg with a in igb_check_for_link_82575()
1310 ret_val = igb_config_fc_after_link_up(hw); in igb_check_for_link_82575()
1312 hw_dbg("Error configuring flow control\n"); in igb_check_for_link_82575()
1314 ret_val = igb_check_for_copper_link(hw); in igb_check_for_link_82575()
1321 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1322 * @hw: pointer to the HW structure
1324 void igb_power_up_serdes_link_82575(struct e1000_hw *hw) in igb_power_up_serdes_link_82575() argument
1329 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in igb_power_up_serdes_link_82575()
1330 !igb_sgmii_active_82575(hw)) in igb_power_up_serdes_link_82575()
1349 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1350 * @hw: pointer to the HW structure
1354 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1357 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, in igb_get_pcs_speed_and_duplex_82575() argument
1360 struct e1000_mac_info *mac = &hw->mac; in igb_get_pcs_speed_and_duplex_82575()
1364 mac->serdes_has_link = false; in igb_get_pcs_speed_and_duplex_82575()
1368 /* Read the PCS Status register for link state. For non-copper mode, in igb_get_pcs_speed_and_duplex_82575()
1379 mac->serdes_has_link = true; in igb_get_pcs_speed_and_duplex_82575()
1396 if (mac->type == e1000_i354) { in igb_get_pcs_speed_and_duplex_82575()
1413 * igb_shutdown_serdes_link_82575 - Remove link during power down
1414 * @hw: pointer to the HW structure
1419 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) in igb_shutdown_serdes_link_82575() argument
1423 if (hw->phy.media_type != e1000_media_type_internal_serdes && in igb_shutdown_serdes_link_82575()
1424 igb_sgmii_active_82575(hw)) in igb_shutdown_serdes_link_82575()
1427 if (!igb_enable_mng_pass_thru(hw)) { in igb_shutdown_serdes_link_82575()
1445 * igb_reset_hw_82575 - Reset hardware
1446 * @hw: pointer to the HW structure
1451 static s32 igb_reset_hw_82575(struct e1000_hw *hw) in igb_reset_hw_82575() argument
1453 u32 ctrl; in igb_reset_hw_82575() local
1456 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igb_reset_hw_82575()
1459 ret_val = igb_disable_pcie_master(hw); in igb_reset_hw_82575()
1461 hw_dbg("PCI-E Master disable polling has failed.\n"); in igb_reset_hw_82575()
1464 ret_val = igb_set_pcie_completion_timeout(hw); in igb_reset_hw_82575()
1466 hw_dbg("PCI-E Set completion timeout has failed.\n"); in igb_reset_hw_82575()
1477 ctrl = rd32(E1000_CTRL); in igb_reset_hw_82575()
1480 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); in igb_reset_hw_82575()
1482 ret_val = igb_get_auto_rd_done(hw); in igb_reset_hw_82575()
1493 igb_reset_init_script_82575(hw); in igb_reset_hw_82575()
1500 ret_val = igb_check_alt_mac_addr(hw); in igb_reset_hw_82575()
1506 * igb_init_hw_82575 - Initialize hardware
1507 * @hw: pointer to the HW structure
1511 static s32 igb_init_hw_82575(struct e1000_hw *hw) in igb_init_hw_82575() argument
1513 struct e1000_mac_info *mac = &hw->mac; in igb_init_hw_82575()
1515 u16 i, rar_count = mac->rar_entry_count; in igb_init_hw_82575()
1517 if ((hw->mac.type >= e1000_i210) && in igb_init_hw_82575()
1518 !(igb_get_flash_presence_i210(hw))) { in igb_init_hw_82575()
1519 ret_val = igb_pll_workaround_i210(hw); in igb_init_hw_82575()
1525 ret_val = igb_id_led_init(hw); in igb_init_hw_82575()
1533 igb_clear_vfta(hw); in igb_init_hw_82575()
1536 igb_init_rx_addrs(hw, rar_count); in igb_init_hw_82575()
1540 for (i = 0; i < mac->mta_reg_count; i++) in igb_init_hw_82575()
1545 for (i = 0; i < mac->uta_reg_count; i++) in igb_init_hw_82575()
1548 /* Setup link and flow control */ in igb_init_hw_82575()
1549 ret_val = igb_setup_link(hw); in igb_init_hw_82575()
1556 igb_clear_hw_cntrs_82575(hw); in igb_init_hw_82575()
1561 * igb_setup_copper_link_82575 - Configure copper link settings
1562 * @hw: pointer to the HW structure
1564 * Configures the link for auto-neg or forced speed and duplex. Then we check
1566 * and flow control are called.
1568 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) in igb_setup_copper_link_82575() argument
1570 u32 ctrl; in igb_setup_copper_link_82575() local
1574 ctrl = rd32(E1000_CTRL); in igb_setup_copper_link_82575()
1575 ctrl |= E1000_CTRL_SLU; in igb_setup_copper_link_82575()
1576 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); in igb_setup_copper_link_82575()
1577 wr32(E1000_CTRL, ctrl); in igb_setup_copper_link_82575()
1580 switch (hw->mac.type) { in igb_setup_copper_link_82575()
1593 ret_val = igb_setup_serdes_link_82575(hw); in igb_setup_copper_link_82575()
1597 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { in igb_setup_copper_link_82575()
1601 ret_val = hw->phy.ops.reset(hw); in igb_setup_copper_link_82575()
1607 switch (hw->phy.type) { in igb_setup_copper_link_82575()
1610 switch (hw->phy.id) { in igb_setup_copper_link_82575()
1616 ret_val = igb_copper_link_setup_m88_gen2(hw); in igb_setup_copper_link_82575()
1619 ret_val = igb_copper_link_setup_m88(hw); in igb_setup_copper_link_82575()
1624 ret_val = igb_copper_link_setup_igp(hw); in igb_setup_copper_link_82575()
1627 ret_val = igb_copper_link_setup_82580(hw); in igb_setup_copper_link_82575()
1633 ret_val = -E1000_ERR_PHY; in igb_setup_copper_link_82575()
1640 ret_val = igb_setup_copper_link(hw); in igb_setup_copper_link_82575()
1646 * igb_setup_serdes_link_82575 - Setup link for serdes
1647 * @hw: pointer to the HW structure
1649 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1652 * for auto-negotiation or forces speed/duplex.
1654 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) in igb_setup_serdes_link_82575() argument
1661 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && in igb_setup_serdes_link_82575()
1662 !igb_sgmii_active_82575(hw)) in igb_setup_serdes_link_82575()
1682 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { in igb_setup_serdes_link_82575()
1695 pcs_autoneg = hw->mac.autoneg; in igb_setup_serdes_link_82575()
1709 if (hw->mac.type == e1000_82575 || in igb_setup_serdes_link_82575()
1710 hw->mac.type == e1000_82576) { in igb_setup_serdes_link_82575()
1711 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); in igb_setup_serdes_link_82575()
1721 /* non-SGMII modes only supports a speed of 1000/Full for the in igb_setup_serdes_link_82575()
1748 /* Disable force flow control for autoneg */ in igb_setup_serdes_link_82575()
1751 /* Configure flow control advertisement for autoneg */ in igb_setup_serdes_link_82575()
1754 switch (hw->fc.requested_mode) { in igb_setup_serdes_link_82575()
1773 /* Force flow control for forced link */ in igb_setup_serdes_link_82575()
1781 if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) in igb_setup_serdes_link_82575()
1782 igb_force_mac_fc(hw); in igb_setup_serdes_link_82575()
1788 * igb_sgmii_active_82575 - Return sgmii state
1789 * @hw: pointer to the HW structure
1795 static bool igb_sgmii_active_82575(struct e1000_hw *hw) in igb_sgmii_active_82575() argument
1797 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_sgmii_active_82575()
1798 return dev_spec->sgmii_active; in igb_sgmii_active_82575()
1802 * igb_reset_init_script_82575 - Inits HW defaults after reset
1803 * @hw: pointer to the HW structure
1805 * Inits recommended HW defaults after a reset when there is no EEPROM
1808 static s32 igb_reset_init_script_82575(struct e1000_hw *hw) in igb_reset_init_script_82575() argument
1810 if (hw->mac.type == e1000_82575) { in igb_reset_init_script_82575()
1813 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); in igb_reset_init_script_82575()
1814 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); in igb_reset_init_script_82575()
1815 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); in igb_reset_init_script_82575()
1816 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); in igb_reset_init_script_82575()
1819 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); in igb_reset_init_script_82575()
1820 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); in igb_reset_init_script_82575()
1823 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); in igb_reset_init_script_82575()
1824 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); in igb_reset_init_script_82575()
1825 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); in igb_reset_init_script_82575()
1826 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); in igb_reset_init_script_82575()
1829 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); in igb_reset_init_script_82575()
1830 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); in igb_reset_init_script_82575()
1831 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); in igb_reset_init_script_82575()
1838 * igb_read_mac_addr_82575 - Read device MAC address
1839 * @hw: pointer to the HW structure
1841 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) in igb_read_mac_addr_82575() argument
1849 ret_val = igb_check_alt_mac_addr(hw); in igb_read_mac_addr_82575()
1853 ret_val = igb_read_mac_addr(hw); in igb_read_mac_addr_82575()
1860 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1861 * @hw: pointer to the HW structure
1866 void igb_power_down_phy_copper_82575(struct e1000_hw *hw) in igb_power_down_phy_copper_82575() argument
1869 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) in igb_power_down_phy_copper_82575()
1870 igb_power_down_phy_copper(hw); in igb_power_down_phy_copper_82575()
1874 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1875 * @hw: pointer to the HW structure
1879 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) in igb_clear_hw_cntrs_82575() argument
1881 igb_clear_hw_cntrs_base(hw); in igb_clear_hw_cntrs_82575()
1931 if (hw->phy.media_type == e1000_media_type_internal_serdes || in igb_clear_hw_cntrs_82575()
1932 igb_sgmii_active_82575(hw)) in igb_clear_hw_cntrs_82575()
1937 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1938 * @hw: pointer to the HW structure
1945 void igb_rx_fifo_flush_82575(struct e1000_hw *hw) in igb_rx_fifo_flush_82575() argument
1955 if (hw->mac.type != e1000_82575 || in igb_rx_fifo_flush_82575()
2014 * igb_set_pcie_completion_timeout - set pci-e completion timeout
2015 * @hw: pointer to the HW structure
2019 * than the 10ms recommended by the pci-e spec. To address this we need to
2023 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) in igb_set_pcie_completion_timeout() argument
2045 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, in igb_set_pcie_completion_timeout()
2052 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, in igb_set_pcie_completion_timeout()
2063 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2064 * @hw: pointer to the hardware struct
2066 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2068 * enables/disables L2 switch anti-spoofing functionality.
2070 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) in igb_vmdq_set_anti_spoofing_pf() argument
2074 switch (hw->mac.type) { in igb_vmdq_set_anti_spoofing_pf()
2090 /* The PF can spoof - it has to in order to in igb_vmdq_set_anti_spoofing_pf()
2102 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2103 * @hw: pointer to the hardware struct
2108 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) in igb_vmdq_set_loopback_pf() argument
2112 switch (hw->mac.type) { in igb_vmdq_set_loopback_pf()
2138 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2139 * @hw: pointer to the hardware struct
2144 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) in igb_vmdq_set_replication_pf() argument
2157 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2158 * @hw: pointer to the HW structure
2165 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) in igb_read_phy_reg_82580() argument
2169 ret_val = hw->phy.ops.acquire(hw); in igb_read_phy_reg_82580()
2173 ret_val = igb_read_phy_reg_mdic(hw, offset, data); in igb_read_phy_reg_82580()
2175 hw->phy.ops.release(hw); in igb_read_phy_reg_82580()
2182 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2183 * @hw: pointer to the HW structure
2189 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) in igb_write_phy_reg_82580() argument
2194 ret_val = hw->phy.ops.acquire(hw); in igb_write_phy_reg_82580()
2198 ret_val = igb_write_phy_reg_mdic(hw, offset, data); in igb_write_phy_reg_82580()
2200 hw->phy.ops.release(hw); in igb_write_phy_reg_82580()
2207 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2208 * @hw: pointer to the HW structure
2214 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) in igb_reset_mdicnfg_82580() argument
2220 if (hw->mac.type != e1000_82580) in igb_reset_mdicnfg_82580()
2222 if (!igb_sgmii_active_82575(hw)) in igb_reset_mdicnfg_82580()
2225 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + in igb_reset_mdicnfg_82580()
2226 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, in igb_reset_mdicnfg_82580()
2244 * igb_reset_hw_82580 - Reset hardware
2245 * @hw: pointer to the HW structure
2250 static s32 igb_reset_hw_82580(struct e1000_hw *hw) in igb_reset_hw_82580() argument
2255 u32 ctrl; in igb_reset_hw_82580() local
2256 bool global_device_reset = hw->dev_spec._82575.global_device_reset; in igb_reset_hw_82580()
2258 hw->dev_spec._82575.global_device_reset = false; in igb_reset_hw_82580()
2260 /* due to hw errata, global device reset doesn't always in igb_reset_hw_82580()
2263 if (hw->mac.type == e1000_82580) in igb_reset_hw_82580()
2267 ctrl = rd32(E1000_CTRL); in igb_reset_hw_82580()
2269 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igb_reset_hw_82580()
2272 ret_val = igb_disable_pcie_master(hw); in igb_reset_hw_82580()
2274 hw_dbg("PCI-E Master disable polling has failed.\n"); in igb_reset_hw_82580()
2286 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) in igb_reset_hw_82580()
2291 ctrl |= E1000_CTRL_DEV_RST; in igb_reset_hw_82580()
2293 ctrl |= E1000_CTRL_RST; in igb_reset_hw_82580()
2295 wr32(E1000_CTRL, ctrl); in igb_reset_hw_82580()
2302 ret_val = igb_get_auto_rd_done(hw); in igb_reset_hw_82580()
2318 ret_val = igb_reset_mdicnfg_82580(hw); in igb_reset_hw_82580()
2323 ret_val = igb_check_alt_mac_addr(hw); in igb_reset_hw_82580()
2327 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); in igb_reset_hw_82580()
2333 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2353 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2355 * @hw: pointer to the HW structure
2361 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, in igb_validate_nvm_checksum_with_offset() argument
2369 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in igb_validate_nvm_checksum_with_offset()
2379 ret_val = -E1000_ERR_NVM; in igb_validate_nvm_checksum_with_offset()
2388 * igb_update_nvm_checksum_with_offset - Update EEPROM
2390 * @hw: pointer to the HW structure
2397 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) in igb_update_nvm_checksum_with_offset() argument
2404 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); in igb_update_nvm_checksum_with_offset()
2411 checksum = (u16) NVM_SUM - checksum; in igb_update_nvm_checksum_with_offset()
2412 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, in igb_update_nvm_checksum_with_offset()
2422 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2423 * @hw: pointer to the HW structure
2429 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) in igb_validate_nvm_checksum_82580() argument
2436 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); in igb_validate_nvm_checksum_82580()
2451 ret_val = igb_validate_nvm_checksum_with_offset(hw, in igb_validate_nvm_checksum_82580()
2462 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2463 * @hw: pointer to the HW structure
2469 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) in igb_update_nvm_checksum_82580() argument
2475 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); in igb_update_nvm_checksum_82580()
2484 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, in igb_update_nvm_checksum_82580()
2494 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); in igb_update_nvm_checksum_82580()
2504 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2505 * @hw: pointer to the HW structure
2511 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) in igb_validate_nvm_checksum_i350() argument
2519 ret_val = igb_validate_nvm_checksum_with_offset(hw, in igb_validate_nvm_checksum_i350()
2530 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2531 * @hw: pointer to the HW structure
2537 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) in igb_update_nvm_checksum_i350() argument
2545 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); in igb_update_nvm_checksum_i350()
2555 * __igb_access_emi_reg - Read/write EMI register
2556 * @hw: pointer to the HW structure
2561 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, in __igb_access_emi_reg() argument
2566 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); in __igb_access_emi_reg()
2571 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); in __igb_access_emi_reg()
2573 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); in __igb_access_emi_reg()
2579 * igb_read_emi_reg - Read Extended Management Interface register
2580 * @hw: pointer to the HW structure
2584 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) in igb_read_emi_reg() argument
2586 return __igb_access_emi_reg(hw, addr, data, true); in igb_read_emi_reg()
2590 * igb_set_eee_i350 - Enable/disable EEE support
2591 * @hw: pointer to the HW structure
2598 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) in igb_set_eee_i350() argument
2602 if ((hw->mac.type < e1000_i350) || in igb_set_eee_i350()
2603 (hw->phy.media_type != e1000_media_type_copper)) in igb_set_eee_i350()
2609 if (!(hw->dev_spec._82575.eee_disable)) { in igb_set_eee_i350()
2646 * igb_set_eee_i354 - Enable/disable EEE support
2647 * @hw: pointer to the HW structure
2654 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) in igb_set_eee_i354() argument
2656 struct e1000_phy_info *phy = &hw->phy; in igb_set_eee_i354()
2660 if ((hw->phy.media_type != e1000_media_type_copper) || in igb_set_eee_i354()
2661 ((phy->id != M88E1543_E_PHY_ID) && in igb_set_eee_i354()
2662 (phy->id != M88E1512_E_PHY_ID))) in igb_set_eee_i354()
2665 if (!hw->dev_spec._82575.eee_disable) { in igb_set_eee_i354()
2667 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); in igb_set_eee_i354()
2671 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, in igb_set_eee_i354()
2677 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, in igb_set_eee_i354()
2683 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); in igb_set_eee_i354()
2688 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, in igb_set_eee_i354()
2704 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, in igb_set_eee_i354()
2709 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, in igb_set_eee_i354()
2717 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, in igb_set_eee_i354()
2727 * igb_get_eee_status_i354 - Get EEE status
2728 * @hw: pointer to the HW structure
2734 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) in igb_get_eee_status_i354() argument
2736 struct e1000_phy_info *phy = &hw->phy; in igb_get_eee_status_i354()
2741 if ((hw->phy.media_type != e1000_media_type_copper) || in igb_get_eee_status_i354()
2742 ((phy->id != M88E1543_E_PHY_ID) && in igb_get_eee_status_i354()
2743 (phy->id != M88E1512_E_PHY_ID))) in igb_get_eee_status_i354()
2746 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, in igb_get_eee_status_i354()
2774 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2775 * @hw: pointer to hardware structure
2779 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) in igb_get_thermal_sensor_data_generic() argument
2788 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in igb_get_thermal_sensor_data_generic()
2790 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) in igb_get_thermal_sensor_data_generic()
2793 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); in igb_get_thermal_sensor_data_generic()
2796 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); in igb_get_thermal_sensor_data_generic()
2800 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); in igb_get_thermal_sensor_data_generic()
2810 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); in igb_get_thermal_sensor_data_generic()
2817 hw->phy.ops.read_i2c_byte(hw, in igb_get_thermal_sensor_data_generic()
2820 &data->sensor[i].temp); in igb_get_thermal_sensor_data_generic()
2826 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2827 * @hw: pointer to hardware structure
2832 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) in igb_init_thermal_sensor_thresh_generic() argument
2843 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in igb_init_thermal_sensor_thresh_generic()
2845 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) in igb_init_thermal_sensor_thresh_generic()
2850 data->sensor[0].location = 0x1; in igb_init_thermal_sensor_thresh_generic()
2851 data->sensor[0].caution_thresh = in igb_init_thermal_sensor_thresh_generic()
2853 data->sensor[0].max_op_thresh = in igb_init_thermal_sensor_thresh_generic()
2857 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); in igb_init_thermal_sensor_thresh_generic()
2861 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); in igb_init_thermal_sensor_thresh_generic()
2871 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); in igb_init_thermal_sensor_thresh_generic()
2878 hw->phy.ops.write_i2c_byte(hw, in igb_init_thermal_sensor_thresh_generic()
2884 data->sensor[i].location = sensor_location; in igb_init_thermal_sensor_thresh_generic()
2885 data->sensor[i].caution_thresh = therm_limit; in igb_init_thermal_sensor_thresh_generic()
2886 data->sensor[i].max_op_thresh = therm_limit - in igb_init_thermal_sensor_thresh_generic()