1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5  * 82562G-2 10/100 Network Connection
7  * 82562GT-2 10/100 Network Connection
9  * 82562V-2 10/100 Network Connection
10  * 82566DC-2 Gigabit Network Connection
12  * 82566DM-2 Gigabit Network Connection
19  * 82567LM-2 Gigabit Network Connection
20  * 82567LF-2 Gigabit Network Connection
21  * 82567V-2 Gigabit Network Connection
22  * 82567LF-3 Gigabit Network Connection
23  * 82567LM-3 Gigabit Network Connection
24  * 82567LM-4 Gigabit Network Connection
31  * Ethernet Connection I217-LM
32  * Ethernet Connection I217-V
33  * Ethernet Connection I218-V
34  * Ethernet Connection I218-LM
35  * Ethernet Connection (2) I218-LM
36  * Ethernet Connection (2) I218-V
37  * Ethernet Connection (3) I218-LM
38  * Ethernet Connection (3) I218-V
55 		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)  in __er16flash()  argument
143 	return readw(hw->flash_address + reg);  in __er16flash()
146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)  in __er32flash()  argument
148 	return readl(hw->flash_address + reg);  in __er32flash()
151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)  in __ew16flash()  argument
153 	writew(val, hw->flash_address + reg);  in __ew16flash()
156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)  in __ew32flash()  argument
158 	writel(val, hw->flash_address + reg);  in __ew32flash()
161 #define er16flash(reg)		__er16flash(hw, (reg))
162 #define er32flash(reg)		__er32flash(hw, (reg))
163 #define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))
167  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168  *  @hw: pointer to the HW structure
174  *  Assumes the sw/fw/hw semaphore is already acquired.
176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)  in e1000_phy_is_accessible_pchlan()  argument
185 		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);  in e1000_phy_is_accessible_pchlan()
190 		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);  in e1000_phy_is_accessible_pchlan()
199 	if (hw->phy.id) {  in e1000_phy_is_accessible_pchlan()
200 		if (hw->phy.id == phy_id)  in e1000_phy_is_accessible_pchlan()
203 		hw->phy.id = phy_id;  in e1000_phy_is_accessible_pchlan()
204 		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);  in e1000_phy_is_accessible_pchlan()
211 	if (hw->mac.type < e1000_pch_lpt) {  in e1000_phy_is_accessible_pchlan()
212 		hw->phy.ops.release(hw);  in e1000_phy_is_accessible_pchlan()
213 		ret_val = e1000_set_mdio_slow_mode_hv(hw);  in e1000_phy_is_accessible_pchlan()
215 			ret_val = e1000e_get_phy_id(hw);  in e1000_phy_is_accessible_pchlan()
216 		hw->phy.ops.acquire(hw);  in e1000_phy_is_accessible_pchlan()
222 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_phy_is_accessible_pchlan()
226 			e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);  in e1000_phy_is_accessible_pchlan()
228 			e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);  in e1000_phy_is_accessible_pchlan()
241  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242  *  @hw: pointer to the HW structure
244  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)  in e1000_toggle_lanphypc_pch_lpt()  argument
258 	mac_reg = er32(CTRL);  in e1000_toggle_lanphypc_pch_lpt()
261 	ew32(CTRL, mac_reg);  in e1000_toggle_lanphypc_pch_lpt()
265 	ew32(CTRL, mac_reg);  in e1000_toggle_lanphypc_pch_lpt()
268 	if (hw->mac.type < e1000_pch_lpt) {  in e1000_toggle_lanphypc_pch_lpt()
275 		} while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);  in e1000_toggle_lanphypc_pch_lpt()
282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283  *  @hw: pointer to the HW structure
285  *  Workarounds/flow necessary for PHY initialization during driver load
288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)  in e1000_init_phy_workarounds_pchlan()  argument
290 	struct e1000_adapter *adapter = hw->adapter;  in e1000_init_phy_workarounds_pchlan()
295 	 * non-managed 82579 and newer adapters.  in e1000_init_phy_workarounds_pchlan()
297 	e1000_gate_hw_phy_config_ich8lan(hw, true);  in e1000_init_phy_workarounds_pchlan()
302 	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;  in e1000_init_phy_workarounds_pchlan()
303 	ret_val = e1000_disable_ulp_lpt_lp(hw, true);  in e1000_init_phy_workarounds_pchlan()
307 	ret_val = hw->phy.ops.acquire(hw);  in e1000_init_phy_workarounds_pchlan()
309 		e_dbg("Failed to initialize PHY flow\n");  in e1000_init_phy_workarounds_pchlan()
313 	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is  in e1000_init_phy_workarounds_pchlan()
317 	switch (hw->mac.type) {  in e1000_init_phy_workarounds_pchlan()
324 		if (e1000_phy_is_accessible_pchlan(hw))  in e1000_init_phy_workarounds_pchlan()
342 		if (e1000_phy_is_accessible_pchlan(hw))  in e1000_init_phy_workarounds_pchlan()
347 		if ((hw->mac.type == e1000_pchlan) &&  in e1000_init_phy_workarounds_pchlan()
351 		if (hw->phy.ops.check_reset_block(hw)) {  in e1000_init_phy_workarounds_pchlan()
353 			ret_val = -E1000_ERR_PHY;  in e1000_init_phy_workarounds_pchlan()
358 		e1000_toggle_lanphypc_pch_lpt(hw);  in e1000_init_phy_workarounds_pchlan()
359 		if (hw->mac.type >= e1000_pch_lpt) {  in e1000_init_phy_workarounds_pchlan()
360 			if (e1000_phy_is_accessible_pchlan(hw))  in e1000_init_phy_workarounds_pchlan()
370 			if (e1000_phy_is_accessible_pchlan(hw))  in e1000_init_phy_workarounds_pchlan()
373 			ret_val = -E1000_ERR_PHY;  in e1000_init_phy_workarounds_pchlan()
380 	hw->phy.ops.release(hw);  in e1000_init_phy_workarounds_pchlan()
384 		if (hw->phy.ops.check_reset_block(hw)) {  in e1000_init_phy_workarounds_pchlan()
394 		ret_val = e1000e_phy_hw_reset_generic(hw);  in e1000_init_phy_workarounds_pchlan()
404 		ret_val = hw->phy.ops.check_reset_block(hw);  in e1000_init_phy_workarounds_pchlan()
410 	/* Ungate automatic PHY configuration on non-managed 82579 */  in e1000_init_phy_workarounds_pchlan()
411 	if ((hw->mac.type == e1000_pch2lan) &&  in e1000_init_phy_workarounds_pchlan()
414 		e1000_gate_hw_phy_config_ich8lan(hw, false);  in e1000_init_phy_workarounds_pchlan()
421  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
422  *  @hw: pointer to the HW structure
424  *  Initialize family-specific PHY parameters and function pointers.
426 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)  in e1000_init_phy_params_pchlan()  argument
428 	struct e1000_phy_info *phy = &hw->phy;  in e1000_init_phy_params_pchlan()
431 	phy->addr = 1;  in e1000_init_phy_params_pchlan()
432 	phy->reset_delay_us = 100;  in e1000_init_phy_params_pchlan()
434 	phy->ops.set_page = e1000_set_page_igp;  in e1000_init_phy_params_pchlan()
435 	phy->ops.read_reg = e1000_read_phy_reg_hv;  in e1000_init_phy_params_pchlan()
436 	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;  in e1000_init_phy_params_pchlan()
437 	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;  in e1000_init_phy_params_pchlan()
438 	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;  in e1000_init_phy_params_pchlan()
439 	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;  in e1000_init_phy_params_pchlan()
440 	phy->ops.write_reg = e1000_write_phy_reg_hv;  in e1000_init_phy_params_pchlan()
441 	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;  in e1000_init_phy_params_pchlan()
442 	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;  in e1000_init_phy_params_pchlan()
443 	phy->ops.power_up = e1000_power_up_phy_copper;  in e1000_init_phy_params_pchlan()
444 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;  in e1000_init_phy_params_pchlan()
445 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;  in e1000_init_phy_params_pchlan()
447 	phy->id = e1000_phy_unknown;  in e1000_init_phy_params_pchlan()
449 	ret_val = e1000_init_phy_workarounds_pchlan(hw);  in e1000_init_phy_params_pchlan()
453 	if (phy->id == e1000_phy_unknown)  in e1000_init_phy_params_pchlan()
454 		switch (hw->mac.type) {  in e1000_init_phy_params_pchlan()
456 			ret_val = e1000e_get_phy_id(hw);  in e1000_init_phy_params_pchlan()
459 			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))  in e1000_init_phy_params_pchlan()
472 			ret_val = e1000_set_mdio_slow_mode_hv(hw);  in e1000_init_phy_params_pchlan()
475 			ret_val = e1000e_get_phy_id(hw);  in e1000_init_phy_params_pchlan()
480 	phy->type = e1000e_get_phy_type_from_id(phy->id);  in e1000_init_phy_params_pchlan()
482 	switch (phy->type) {  in e1000_init_phy_params_pchlan()
486 		phy->ops.check_polarity = e1000_check_polarity_82577;  in e1000_init_phy_params_pchlan()
487 		phy->ops.force_speed_duplex =  in e1000_init_phy_params_pchlan()
489 		phy->ops.get_cable_length = e1000_get_cable_length_82577;  in e1000_init_phy_params_pchlan()
490 		phy->ops.get_info = e1000_get_phy_info_82577;  in e1000_init_phy_params_pchlan()
491 		phy->ops.commit = e1000e_phy_sw_reset;  in e1000_init_phy_params_pchlan()
494 		phy->ops.check_polarity = e1000_check_polarity_m88;  in e1000_init_phy_params_pchlan()
495 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;  in e1000_init_phy_params_pchlan()
496 		phy->ops.get_cable_length = e1000e_get_cable_length_m88;  in e1000_init_phy_params_pchlan()
497 		phy->ops.get_info = e1000e_get_phy_info_m88;  in e1000_init_phy_params_pchlan()
500 		ret_val = -E1000_ERR_PHY;  in e1000_init_phy_params_pchlan()
508  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
509  *  @hw: pointer to the HW structure
511  *  Initialize family-specific PHY parameters and function pointers.
513 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)  in e1000_init_phy_params_ich8lan()  argument
515 	struct e1000_phy_info *phy = &hw->phy;  in e1000_init_phy_params_ich8lan()
519 	phy->addr = 1;  in e1000_init_phy_params_ich8lan()
520 	phy->reset_delay_us = 100;  in e1000_init_phy_params_ich8lan()
522 	phy->ops.power_up = e1000_power_up_phy_copper;  in e1000_init_phy_params_ich8lan()
523 	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;  in e1000_init_phy_params_ich8lan()
525 	/* We may need to do this twice - once for IGP and if that fails,  in e1000_init_phy_params_ich8lan()
528 	ret_val = e1000e_determine_phy_address(hw);  in e1000_init_phy_params_ich8lan()
530 		phy->ops.write_reg = e1000e_write_phy_reg_bm;  in e1000_init_phy_params_ich8lan()
531 		phy->ops.read_reg = e1000e_read_phy_reg_bm;  in e1000_init_phy_params_ich8lan()
532 		ret_val = e1000e_determine_phy_address(hw);  in e1000_init_phy_params_ich8lan()
539 	phy->id = 0;  in e1000_init_phy_params_ich8lan()
540 	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&  in e1000_init_phy_params_ich8lan()
543 		ret_val = e1000e_get_phy_id(hw);  in e1000_init_phy_params_ich8lan()
549 	switch (phy->id) {  in e1000_init_phy_params_ich8lan()
551 		phy->type = e1000_phy_igp_3;  in e1000_init_phy_params_ich8lan()
552 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;  in e1000_init_phy_params_ich8lan()
553 		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;  in e1000_init_phy_params_ich8lan()
554 		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;  in e1000_init_phy_params_ich8lan()
555 		phy->ops.get_info = e1000e_get_phy_info_igp;  in e1000_init_phy_params_ich8lan()
556 		phy->ops.check_polarity = e1000_check_polarity_igp;  in e1000_init_phy_params_ich8lan()
557 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;  in e1000_init_phy_params_ich8lan()
562 		phy->type = e1000_phy_ife;  in e1000_init_phy_params_ich8lan()
563 		phy->autoneg_mask = E1000_ALL_NOT_GIG;  in e1000_init_phy_params_ich8lan()
564 		phy->ops.get_info = e1000_get_phy_info_ife;  in e1000_init_phy_params_ich8lan()
565 		phy->ops.check_polarity = e1000_check_polarity_ife;  in e1000_init_phy_params_ich8lan()
566 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;  in e1000_init_phy_params_ich8lan()
569 		phy->type = e1000_phy_bm;  in e1000_init_phy_params_ich8lan()
570 		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;  in e1000_init_phy_params_ich8lan()
571 		phy->ops.read_reg = e1000e_read_phy_reg_bm;  in e1000_init_phy_params_ich8lan()
572 		phy->ops.write_reg = e1000e_write_phy_reg_bm;  in e1000_init_phy_params_ich8lan()
573 		phy->ops.commit = e1000e_phy_sw_reset;  in e1000_init_phy_params_ich8lan()
574 		phy->ops.get_info = e1000e_get_phy_info_m88;  in e1000_init_phy_params_ich8lan()
575 		phy->ops.check_polarity = e1000_check_polarity_m88;  in e1000_init_phy_params_ich8lan()
576 		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;  in e1000_init_phy_params_ich8lan()
579 		return -E1000_ERR_PHY;  in e1000_init_phy_params_ich8lan()
586  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
587  *  @hw: pointer to the HW structure
589  *  Initialize family-specific NVM parameters and function
592 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)  in e1000_init_nvm_params_ich8lan()  argument
594 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_init_nvm_params_ich8lan()
595 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_init_nvm_params_ich8lan()
600 	nvm->type = e1000_nvm_flash_sw;  in e1000_init_nvm_params_ich8lan()
602 	if (hw->mac.type >= e1000_pch_spt) {  in e1000_init_nvm_params_ich8lan()
609 		nvm->flash_base_addr = 0;  in e1000_init_nvm_params_ich8lan()
612 		nvm->flash_bank_size = nvm_size / 2;  in e1000_init_nvm_params_ich8lan()
614 		nvm->flash_bank_size /= sizeof(u16);  in e1000_init_nvm_params_ich8lan()
616 		hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;  in e1000_init_nvm_params_ich8lan()
619 		if (!hw->flash_address) {  in e1000_init_nvm_params_ich8lan()
621 			return -E1000_ERR_CONFIG;  in e1000_init_nvm_params_ich8lan()
626 		/* sector_X_addr is a "sector"-aligned address (4096 bytes)  in e1000_init_nvm_params_ich8lan()
633 		/* flash_base_addr is byte-aligned */  in e1000_init_nvm_params_ich8lan()
634 		nvm->flash_base_addr = sector_base_addr  in e1000_init_nvm_params_ich8lan()
640 		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)  in e1000_init_nvm_params_ich8lan()
642 		nvm->flash_bank_size /= 2;  in e1000_init_nvm_params_ich8lan()
644 		nvm->flash_bank_size /= sizeof(u16);  in e1000_init_nvm_params_ich8lan()
647 	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;  in e1000_init_nvm_params_ich8lan()
650 	for (i = 0; i < nvm->word_size; i++) {  in e1000_init_nvm_params_ich8lan()
651 		dev_spec->shadow_ram[i].modified = false;  in e1000_init_nvm_params_ich8lan()
652 		dev_spec->shadow_ram[i].value = 0xFFFF;  in e1000_init_nvm_params_ich8lan()
659  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
660  *  @hw: pointer to the HW structure
662  *  Initialize family-specific MAC parameters and function
665 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)  in e1000_init_mac_params_ich8lan()  argument
667 	struct e1000_mac_info *mac = &hw->mac;  in e1000_init_mac_params_ich8lan()
670 	hw->phy.media_type = e1000_media_type_copper;  in e1000_init_mac_params_ich8lan()
673 	mac->mta_reg_count = 32;  in e1000_init_mac_params_ich8lan()
675 	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;  in e1000_init_mac_params_ich8lan()
676 	if (mac->type == e1000_ich8lan)  in e1000_init_mac_params_ich8lan()
677 		mac->rar_entry_count--;  in e1000_init_mac_params_ich8lan()
679 	mac->has_fwsm = true;  in e1000_init_mac_params_ich8lan()
681 	mac->arc_subsystem_valid = false;  in e1000_init_mac_params_ich8lan()
683 	mac->adaptive_ifs = true;  in e1000_init_mac_params_ich8lan()
686 	switch (mac->type) {  in e1000_init_mac_params_ich8lan()
691 		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;  in e1000_init_mac_params_ich8lan()
693 		mac->ops.id_led_init = e1000e_id_led_init_generic;  in e1000_init_mac_params_ich8lan()
695 		mac->ops.blink_led = e1000e_blink_led_generic;  in e1000_init_mac_params_ich8lan()
697 		mac->ops.setup_led = e1000e_setup_led_generic;  in e1000_init_mac_params_ich8lan()
699 		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;  in e1000_init_mac_params_ich8lan()
701 		mac->ops.led_on = e1000_led_on_ich8lan;  in e1000_init_mac_params_ich8lan()
702 		mac->ops.led_off = e1000_led_off_ich8lan;  in e1000_init_mac_params_ich8lan()
705 		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;  in e1000_init_mac_params_ich8lan()
706 		mac->ops.rar_set = e1000_rar_set_pch2lan;  in e1000_init_mac_params_ich8lan()
716 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;  in e1000_init_mac_params_ich8lan()
718 		mac->ops.id_led_init = e1000_id_led_init_pchlan;  in e1000_init_mac_params_ich8lan()
720 		mac->ops.setup_led = e1000_setup_led_pchlan;  in e1000_init_mac_params_ich8lan()
722 		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;  in e1000_init_mac_params_ich8lan()
724 		mac->ops.led_on = e1000_led_on_pchlan;  in e1000_init_mac_params_ich8lan()
725 		mac->ops.led_off = e1000_led_off_pchlan;  in e1000_init_mac_params_ich8lan()
731 	if (mac->type >= e1000_pch_lpt) {  in e1000_init_mac_params_ich8lan()
732 		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;  in e1000_init_mac_params_ich8lan()
733 		mac->ops.rar_set = e1000_rar_set_pch_lpt;  in e1000_init_mac_params_ich8lan()
734 		mac->ops.setup_physical_interface =  in e1000_init_mac_params_ich8lan()
736 		mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;  in e1000_init_mac_params_ich8lan()
739 	/* Enable PCS Lock-loss workaround for ICH8 */  in e1000_init_mac_params_ich8lan()
740 	if (mac->type == e1000_ich8lan)  in e1000_init_mac_params_ich8lan()
741 		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);  in e1000_init_mac_params_ich8lan()
747  *  __e1000_access_emi_reg_locked - Read/write EMI register
748  *  @hw: pointer to the HW structure
753  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
755 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,  in __e1000_access_emi_reg_locked()  argument
760 	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);  in __e1000_access_emi_reg_locked()
765 		ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);  in __e1000_access_emi_reg_locked()
767 		ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);  in __e1000_access_emi_reg_locked()
773  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
774  *  @hw: pointer to the HW structure
778  *  Assumes the SW/FW/HW Semaphore is already acquired.
780 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)  in e1000_read_emi_reg_locked()  argument
782 	return __e1000_access_emi_reg_locked(hw, addr, data, true);  in e1000_read_emi_reg_locked()
786  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
787  *  @hw: pointer to the HW structure
791  *  Assumes the SW/FW/HW Semaphore is already acquired.
793 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)  in e1000_write_emi_reg_locked()  argument
795 	return __e1000_access_emi_reg_locked(hw, addr, &data, false);  in e1000_write_emi_reg_locked()
799  *  e1000_set_eee_pchlan - Enable/disable EEE support
800  *  @hw: pointer to the HW structure
812 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)  in e1000_set_eee_pchlan()  argument
814 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_set_eee_pchlan()
818 	switch (hw->phy.type) {  in e1000_set_eee_pchlan()
833 	ret_val = hw->phy.ops.acquire(hw);  in e1000_set_eee_pchlan()
837 	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);  in e1000_set_eee_pchlan()
845 	if (!dev_spec->eee_disable) {  in e1000_set_eee_pchlan()
847 		ret_val = e1000_read_emi_reg_locked(hw, lpa,  in e1000_set_eee_pchlan()
848 						    &dev_spec->eee_lp_ability);  in e1000_set_eee_pchlan()
853 		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);  in e1000_set_eee_pchlan()
860 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)  in e1000_set_eee_pchlan()
863 		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {  in e1000_set_eee_pchlan()
864 			e1e_rphy_locked(hw, MII_LPA, &data);  in e1000_set_eee_pchlan()
869 				 * partner's EEE in 100 ability if full-duplex  in e1000_set_eee_pchlan()
872 				dev_spec->eee_lp_ability &=  in e1000_set_eee_pchlan()
877 	if (hw->phy.type == e1000_phy_82579) {  in e1000_set_eee_pchlan()
878 		ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,  in e1000_set_eee_pchlan()
884 		ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,  in e1000_set_eee_pchlan()
888 	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */  in e1000_set_eee_pchlan()
889 	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);  in e1000_set_eee_pchlan()
893 	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);  in e1000_set_eee_pchlan()
895 	hw->phy.ops.release(hw);  in e1000_set_eee_pchlan()
901  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
902  *  @hw:   pointer to the HW structure
907  *  the de-assertion of the clock request when in 1Gpbs mode.
908  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
911 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)  in e1000_k1_workaround_lpt_lp()  argument
919 		ret_val = hw->phy.ops.acquire(hw);  in e1000_k1_workaround_lpt_lp()
924 		    e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,  in e1000_k1_workaround_lpt_lp()
930 		    e1000e_write_kmrn_reg_locked(hw,  in e1000_k1_workaround_lpt_lp()
942 		    e1000e_write_kmrn_reg_locked(hw,  in e1000_k1_workaround_lpt_lp()
946 		hw->phy.ops.release(hw);  in e1000_k1_workaround_lpt_lp()
951 		if ((hw->phy.revision > 5) || !link ||  in e1000_k1_workaround_lpt_lp()
956 		ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);  in e1000_k1_workaround_lpt_lp()
978 		ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);  in e1000_k1_workaround_lpt_lp()
990  *  e1000_platform_pm_pch_lpt - Set platform power management values
991  *  @hw: pointer to the HW structure
994  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
998  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1001  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1002  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1005 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)  in e1000_platform_pm_pch_lpt()  argument
1018 		if (!hw->adapter->max_frame_size) {  in e1000_platform_pm_pch_lpt()
1020 			return -E1000_ERR_CONFIG;  in e1000_platform_pm_pch_lpt()
1023 		hw->mac.ops.get_link_up_info(hw, &speed, &duplex);  in e1000_platform_pm_pch_lpt()
1026 			return -E1000_ERR_CONFIG;  in e1000_platform_pm_pch_lpt()
1035 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by  in e1000_platform_pm_pch_lpt()
1036 		 * a 10-bit value (0-1023) to provide a range from 1 ns to  in e1000_platform_pm_pch_lpt()
1037 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,  in e1000_platform_pm_pch_lpt()
1041 		value = (rxa > hw->adapter->max_frame_size) ?  in e1000_platform_pm_pch_lpt()
1042 			(rxa - hw->adapter->max_frame_size) * (16000 / speed) :  in e1000_platform_pm_pch_lpt()
1051 			return -E1000_ERR_CONFIG;  in e1000_platform_pm_pch_lpt()
1056 		pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,  in e1000_platform_pm_pch_lpt()
1058 		pci_read_config_word(hw->adapter->pdev,  in e1000_platform_pm_pch_lpt()
1066 	/* Set Snoop and No-Snoop latencies the same */  in e1000_platform_pm_pch_lpt()
1074  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1075  *  @hw: pointer to the HW structure
1083 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)  in e1000_enable_ulp_lpt_lp()  argument
1090 	if ((hw->mac.type < e1000_pch_lpt) ||  in e1000_enable_ulp_lpt_lp()
1091 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||  in e1000_enable_ulp_lpt_lp()
1092 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||  in e1000_enable_ulp_lpt_lp()
1093 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||  in e1000_enable_ulp_lpt_lp()
1094 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||  in e1000_enable_ulp_lpt_lp()
1095 	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))  in e1000_enable_ulp_lpt_lp()
1112 			/* Bail if link is re-acquired */  in e1000_enable_ulp_lpt_lp()
1114 				return -E1000_ERR_PHY;  in e1000_enable_ulp_lpt_lp()
1126 	ret_val = hw->phy.ops.acquire(hw);  in e1000_enable_ulp_lpt_lp()
1131 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);  in e1000_enable_ulp_lpt_lp()
1135 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);  in e1000_enable_ulp_lpt_lp()
1142 	/* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable  in e1000_enable_ulp_lpt_lp()
1145 	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {  in e1000_enable_ulp_lpt_lp()
1146 		ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,  in e1000_enable_ulp_lpt_lp()
1154 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,  in e1000_enable_ulp_lpt_lp()
1164 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);  in e1000_enable_ulp_lpt_lp()
1182 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);  in e1000_enable_ulp_lpt_lp()
1191 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);  in e1000_enable_ulp_lpt_lp()
1193 	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&  in e1000_enable_ulp_lpt_lp()
1195 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,  in e1000_enable_ulp_lpt_lp()
1202 	hw->phy.ops.release(hw);  in e1000_enable_ulp_lpt_lp()
1205 		e_dbg("Error in ULP enable flow: %d\n", ret_val);  in e1000_enable_ulp_lpt_lp()
1207 		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;  in e1000_enable_ulp_lpt_lp()
1213  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1214  *  @hw: pointer to the HW structure
1217  *  Un-configure ULP mode when link is up, the system is transitioned from
1219  *  system, poll for an indication from ME that ULP has been un-configured.
1220  *  If not on an ME enabled system, un-configure the ULP mode by software.
1224  *  the driver or during Sx->S0 transitions, this is called with force=true
1227 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)  in e1000_disable_ulp_lpt_lp()  argument
1234 	if ((hw->mac.type < e1000_pch_lpt) ||  in e1000_disable_ulp_lpt_lp()
1235 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||  in e1000_disable_ulp_lpt_lp()
1236 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||  in e1000_disable_ulp_lpt_lp()
1237 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||  in e1000_disable_ulp_lpt_lp()
1238 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||  in e1000_disable_ulp_lpt_lp()
1239 	    (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))  in e1000_disable_ulp_lpt_lp()
1244 			/* Request ME un-configure ULP mode in the PHY */  in e1000_disable_ulp_lpt_lp()
1254 				ret_val = -E1000_ERR_PHY;  in e1000_disable_ulp_lpt_lp()
1276 	ret_val = hw->phy.ops.acquire(hw);  in e1000_disable_ulp_lpt_lp()
1282 		e1000_toggle_lanphypc_pch_lpt(hw);  in e1000_disable_ulp_lpt_lp()
1285 	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);  in e1000_disable_ulp_lpt_lp()
1296 		ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,  in e1000_disable_ulp_lpt_lp()
1302 	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);  in e1000_disable_ulp_lpt_lp()
1310 	 * hardware.  Re-Enable K1 in the PHY when exiting ULP.  in e1000_disable_ulp_lpt_lp()
1312 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);  in e1000_disable_ulp_lpt_lp()
1316 	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);  in e1000_disable_ulp_lpt_lp()
1319 	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);  in e1000_disable_ulp_lpt_lp()
1330 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);  in e1000_disable_ulp_lpt_lp()
1334 	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);  in e1000_disable_ulp_lpt_lp()
1342 	hw->phy.ops.release(hw);  in e1000_disable_ulp_lpt_lp()
1344 		e1000_phy_hw_reset(hw);  in e1000_disable_ulp_lpt_lp()
1349 		e_dbg("Error in ULP disable flow: %d\n", ret_val);  in e1000_disable_ulp_lpt_lp()
1351 		hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;  in e1000_disable_ulp_lpt_lp()
1357  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1358  *  @hw: pointer to the HW structure
1364 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)  in e1000_check_for_copper_link_ich8lan()  argument
1366 	struct e1000_mac_info *mac = &hw->mac;  in e1000_check_for_copper_link_ich8lan()
1372 	/* We only want to go out to the PHY registers to see if Auto-Neg  in e1000_check_for_copper_link_ich8lan()
1377 	if (!mac->get_link_status)  in e1000_check_for_copper_link_ich8lan()
1379 	mac->get_link_status = false;  in e1000_check_for_copper_link_ich8lan()
1385 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);  in e1000_check_for_copper_link_ich8lan()
1389 	if (hw->mac.type == e1000_pchlan) {  in e1000_check_for_copper_link_ich8lan()
1390 		ret_val = e1000_k1_gig_workaround_hv(hw, link);  in e1000_check_for_copper_link_ich8lan()
1395 	/* When connected at 10Mbps half-duplex, some parts are excessively  in e1000_check_for_copper_link_ich8lan()
1399 	if ((hw->mac.type >= e1000_pch2lan) && link) {  in e1000_check_for_copper_link_ich8lan()
1402 		e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);  in e1000_check_for_copper_link_ich8lan()
1410 		} else if (hw->mac.type >= e1000_pch_spt &&  in e1000_check_for_copper_link_ich8lan()
1423 		ret_val = hw->phy.ops.acquire(hw);  in e1000_check_for_copper_link_ich8lan()
1427 		if (hw->mac.type == e1000_pch2lan)  in e1000_check_for_copper_link_ich8lan()
1431 		ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);  in e1000_check_for_copper_link_ich8lan()
1433 		if (hw->mac.type >= e1000_pch_lpt) {  in e1000_check_for_copper_link_ich8lan()
1436 			e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);  in e1000_check_for_copper_link_ich8lan()
1442 			e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);  in e1000_check_for_copper_link_ich8lan()
1445 				hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,  in e1000_check_for_copper_link_ich8lan()
1450 				hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,  in e1000_check_for_copper_link_ich8lan()
1454 		hw->phy.ops.release(hw);  in e1000_check_for_copper_link_ich8lan()
1459 		if (hw->mac.type >= e1000_pch_spt) {  in e1000_check_for_copper_link_ich8lan()
1464 				ret_val = hw->phy.ops.acquire(hw);  in e1000_check_for_copper_link_ich8lan()
1468 				ret_val = e1e_rphy_locked(hw,  in e1000_check_for_copper_link_ich8lan()
1472 					hw->phy.ops.release(hw);  in e1000_check_for_copper_link_ich8lan()
1481 					    e1e_wphy_locked(hw,  in e1000_check_for_copper_link_ich8lan()
1485 				hw->phy.ops.release(hw);  in e1000_check_for_copper_link_ich8lan()
1489 				ret_val = hw->phy.ops.acquire(hw);  in e1000_check_for_copper_link_ich8lan()
1493 				ret_val = e1e_wphy_locked(hw,  in e1000_check_for_copper_link_ich8lan()
1496 				hw->phy.ops.release(hw);  in e1000_check_for_copper_link_ich8lan()
1509 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_check_for_copper_link_ich8lan()
1518 	/* Work-around I218 hang issue */  in e1000_check_for_copper_link_ich8lan()
1519 	if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||  in e1000_check_for_copper_link_ich8lan()
1520 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||  in e1000_check_for_copper_link_ich8lan()
1521 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||  in e1000_check_for_copper_link_ich8lan()
1522 	    (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {  in e1000_check_for_copper_link_ich8lan()
1523 		ret_val = e1000_k1_workaround_lpt_lp(hw, link);  in e1000_check_for_copper_link_ich8lan()
1527 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_check_for_copper_link_ich8lan()
1531 		ret_val = e1000_platform_pm_pch_lpt(hw, link);  in e1000_check_for_copper_link_ich8lan()
1537 	hw->dev_spec.ich8lan.eee_lp_ability = 0;  in e1000_check_for_copper_link_ich8lan()
1539 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_check_for_copper_link_ich8lan()
1542 		if (hw->mac.type == e1000_pch_spt) {  in e1000_check_for_copper_link_ich8lan()
1543 			/* FEXTNVM6 K1-off workaround - for SPT only */  in e1000_check_for_copper_link_ich8lan()
1558 	switch (hw->mac.type) {  in e1000_check_for_copper_link_ich8lan()
1560 		ret_val = e1000_k1_workaround_lv(hw);  in e1000_check_for_copper_link_ich8lan()
1565 		if (hw->phy.type == e1000_phy_82578) {  in e1000_check_for_copper_link_ich8lan()
1566 			ret_val = e1000_link_stall_workaround_hv(hw);  in e1000_check_for_copper_link_ich8lan()
1571 		/* Workaround for PCHx parts in half-duplex:  in e1000_check_for_copper_link_ich8lan()
1576 		e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);  in e1000_check_for_copper_link_ich8lan()
1582 		e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);  in e1000_check_for_copper_link_ich8lan()
1589 	 * immediately after link-up  in e1000_check_for_copper_link_ich8lan()
1591 	e1000e_check_downshift(hw);  in e1000_check_for_copper_link_ich8lan()
1594 	if (hw->phy.type > e1000_phy_82579) {  in e1000_check_for_copper_link_ich8lan()
1595 		ret_val = e1000_set_eee_pchlan(hw);  in e1000_check_for_copper_link_ich8lan()
1603 	if (!mac->autoneg)  in e1000_check_for_copper_link_ich8lan()
1604 		return -E1000_ERR_CONFIG;  in e1000_check_for_copper_link_ich8lan()
1606 	/* Auto-Neg is enabled.  Auto Speed Detection takes care  in e1000_check_for_copper_link_ich8lan()
1610 	mac->ops.config_collision_dist(hw);  in e1000_check_for_copper_link_ich8lan()
1612 	/* Configure Flow Control now that Auto-Neg has completed.  in e1000_check_for_copper_link_ich8lan()
1613 	 * First, we need to restore the desired flow control  in e1000_check_for_copper_link_ich8lan()
1614 	 * settings because we may have had to re-autoneg with a  in e1000_check_for_copper_link_ich8lan()
1617 	ret_val = e1000e_config_fc_after_link_up(hw);  in e1000_check_for_copper_link_ich8lan()
1619 		e_dbg("Error configuring flow control\n");  in e1000_check_for_copper_link_ich8lan()
1624 	mac->get_link_status = true;  in e1000_check_for_copper_link_ich8lan()
1630 	struct e1000_hw *hw = &adapter->hw;  in e1000_get_variants_ich8lan()  local
1633 	rc = e1000_init_mac_params_ich8lan(hw);  in e1000_get_variants_ich8lan()
1637 	rc = e1000_init_nvm_params_ich8lan(hw);  in e1000_get_variants_ich8lan()
1641 	switch (hw->mac.type) {  in e1000_get_variants_ich8lan()
1645 		rc = e1000_init_phy_params_ich8lan(hw);  in e1000_get_variants_ich8lan()
1655 		rc = e1000_init_phy_params_pchlan(hw);  in e1000_get_variants_ich8lan()
1666 	if ((adapter->hw.phy.type == e1000_phy_ife) ||  in e1000_get_variants_ich8lan()
1667 	    ((adapter->hw.mac.type >= e1000_pch2lan) &&  in e1000_get_variants_ich8lan()
1669 		adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;  in e1000_get_variants_ich8lan()
1670 		adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;  in e1000_get_variants_ich8lan()
1672 		hw->mac.ops.blink_led = NULL;  in e1000_get_variants_ich8lan()
1675 	if ((adapter->hw.mac.type == e1000_ich8lan) &&  in e1000_get_variants_ich8lan()
1676 	    (adapter->hw.phy.type != e1000_phy_ife))  in e1000_get_variants_ich8lan()
1677 		adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;  in e1000_get_variants_ich8lan()
1680 	if ((adapter->hw.mac.type == e1000_pch2lan) &&  in e1000_get_variants_ich8lan()
1682 		adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;  in e1000_get_variants_ich8lan()
1690  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1691  *  @hw: pointer to the HW structure
1695 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)  in e1000_acquire_nvm_ich8lan()  argument
1703  *  e1000_release_nvm_ich8lan - Release NVM mutex
1704  *  @hw: pointer to the HW structure
1708 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)  in e1000_release_nvm_ich8lan()  argument
1714  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1715  *  @hw: pointer to the HW structure
1720 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)  in e1000_acquire_swflag_ich8lan()  argument
1726 			     &hw->adapter->state)) {  in e1000_acquire_swflag_ich8lan()
1728 		return -E1000_ERR_PHY;  in e1000_acquire_swflag_ich8lan()
1737 		timeout--;  in e1000_acquire_swflag_ich8lan()
1742 		ret_val = -E1000_ERR_CONFIG;  in e1000_acquire_swflag_ich8lan()
1757 		timeout--;  in e1000_acquire_swflag_ich8lan()
1761 		e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",  in e1000_acquire_swflag_ich8lan()
1765 		ret_val = -E1000_ERR_CONFIG;  in e1000_acquire_swflag_ich8lan()
1771 		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);  in e1000_acquire_swflag_ich8lan()
1777  *  e1000_release_swflag_ich8lan - Release software control flag
1778  *  @hw: pointer to the HW structure
1783 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)  in e1000_release_swflag_ich8lan()  argument
1793 		e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");  in e1000_release_swflag_ich8lan()
1796 	clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);  in e1000_release_swflag_ich8lan()
1800  *  e1000_check_mng_mode_ich8lan - Checks management mode
1801  *  @hw: pointer to the HW structure
1807 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)  in e1000_check_mng_mode_ich8lan()  argument
1818  *  e1000_check_mng_mode_pchlan - Checks management mode
1819  *  @hw: pointer to the HW structure
1825 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)  in e1000_check_mng_mode_pchlan()  argument
1835  *  e1000_rar_set_pch2lan - Set receive address register
1836  *  @hw: pointer to the HW structure
1842  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1843  *  Use SHRA[0-3] in place of those reserved for ME.
1845 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)  in e1000_rar_set_pch2lan()  argument
1849 	/* HW expects these in little endian so we reverse the byte order  in e1000_rar_set_pch2lan()
1870 	/* RAR[1-6] are owned by manageability.  Skip those and program the  in e1000_rar_set_pch2lan()
1873 	if (index < (u32)(hw->mac.rar_entry_count)) {  in e1000_rar_set_pch2lan()
1876 		ret_val = e1000_acquire_swflag_ich8lan(hw);  in e1000_rar_set_pch2lan()
1880 		ew32(SHRAL(index - 1), rar_low);  in e1000_rar_set_pch2lan()
1882 		ew32(SHRAH(index - 1), rar_high);  in e1000_rar_set_pch2lan()
1885 		e1000_release_swflag_ich8lan(hw);  in e1000_rar_set_pch2lan()
1888 		if ((er32(SHRAL(index - 1)) == rar_low) &&  in e1000_rar_set_pch2lan()
1889 		    (er32(SHRAH(index - 1)) == rar_high))  in e1000_rar_set_pch2lan()
1892 		e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",  in e1000_rar_set_pch2lan()
1893 		      (index - 1), er32(FWSM));  in e1000_rar_set_pch2lan()
1898 	return -E1000_ERR_CONFIG;  in e1000_rar_set_pch2lan()
1902  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1903  *  @hw: pointer to the HW structure
1906  *  program. SHRA[0-10] are the shared receive address registers
1911 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)  in e1000_rar_get_count_pch_lpt()  argument
1922 		num_entries = hw->mac.rar_entry_count;  in e1000_rar_get_count_pch_lpt()
1929 		/* SHRA[0..(wlock_mac - 1)] available + RAR[0] */  in e1000_rar_get_count_pch_lpt()
1938  *  e1000_rar_set_pch_lpt - Set receive address registers
1939  *  @hw: pointer to the HW structure
1945  *  contain the MAC address. SHRA[0-10] are the shared receive address
1948 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)  in e1000_rar_set_pch_lpt()  argument
1953 	/* HW expects these in little endian so we reverse the byte order  in e1000_rar_set_pch_lpt()
1974 	 * it is using - those registers are unavailable for use.  in e1000_rar_set_pch_lpt()
1976 	if (index < hw->mac.rar_entry_count) {  in e1000_rar_set_pch_lpt()
1987 			ret_val = e1000_acquire_swflag_ich8lan(hw);  in e1000_rar_set_pch_lpt()
1992 			ew32(SHRAL_PCH_LPT(index - 1), rar_low);  in e1000_rar_set_pch_lpt()
1994 			ew32(SHRAH_PCH_LPT(index - 1), rar_high);  in e1000_rar_set_pch_lpt()
1997 			e1000_release_swflag_ich8lan(hw);  in e1000_rar_set_pch_lpt()
2000 			if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&  in e1000_rar_set_pch_lpt()
2001 			    (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))  in e1000_rar_set_pch_lpt()
2008 	return -E1000_ERR_CONFIG;  in e1000_rar_set_pch_lpt()
2012  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2013  *  @hw: pointer to the HW structure
2019 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)  in e1000_check_reset_block_ich8lan()  argument
2031  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2032  *  @hw: pointer to the HW structure
2037 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)  in e1000_write_smbus_addr()  argument
2047 	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);  in e1000_write_smbus_addr()
2055 	if (hw->phy.type == e1000_phy_i217) {  in e1000_write_smbus_addr()
2057 		if (freq--) {  in e1000_write_smbus_addr()
2062 			    (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);  in e1000_write_smbus_addr()
2068 	return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);  in e1000_write_smbus_addr()
2072  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2073  *  @hw:   pointer to the HW structure
2078 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)  in e1000_sw_lcd_config_ich8lan()  argument
2080 	struct e1000_phy_info *phy = &hw->phy;  in e1000_sw_lcd_config_ich8lan()
2091 	switch (hw->mac.type) {  in e1000_sw_lcd_config_ich8lan()
2093 		if (phy->type != e1000_phy_igp_3)  in e1000_sw_lcd_config_ich8lan()
2096 		if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||  in e1000_sw_lcd_config_ich8lan()
2097 		    (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {  in e1000_sw_lcd_config_ich8lan()
2116 	ret_val = hw->phy.ops.acquire(hw);  in e1000_sw_lcd_config_ich8lan()
2124 	/* Make sure HW does not configure LCD from PHY  in e1000_sw_lcd_config_ich8lan()
2128 	if ((hw->mac.type < e1000_pch2lan) &&  in e1000_sw_lcd_config_ich8lan()
2141 	if (((hw->mac.type == e1000_pchlan) &&  in e1000_sw_lcd_config_ich8lan()
2143 	    (hw->mac.type > e1000_pchlan)) {  in e1000_sw_lcd_config_ich8lan()
2144 		/* HW configures the SMBus address and LEDs when the  in e1000_sw_lcd_config_ich8lan()
2149 		ret_val = e1000_write_smbus_addr(hw);  in e1000_sw_lcd_config_ich8lan()
2154 		ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,  in e1000_sw_lcd_config_ich8lan()
2166 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);  in e1000_sw_lcd_config_ich8lan()
2170 		ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),  in e1000_sw_lcd_config_ich8lan()
2184 		ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);  in e1000_sw_lcd_config_ich8lan()
2190 	hw->phy.ops.release(hw);  in e1000_sw_lcd_config_ich8lan()
2195  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2196  *  @hw:   pointer to the HW structure
2204 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)  in e1000_k1_gig_workaround_hv()  argument
2208 	bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;  in e1000_k1_gig_workaround_hv()
2210 	if (hw->mac.type != e1000_pchlan)  in e1000_k1_gig_workaround_hv()
2213 	/* Wrap the whole flow with the sw flag */  in e1000_k1_gig_workaround_hv()
2214 	ret_val = hw->phy.ops.acquire(hw);  in e1000_k1_gig_workaround_hv()
2220 		if (hw->phy.type == e1000_phy_82578) {  in e1000_k1_gig_workaround_hv()
2221 			ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,  in e1000_k1_gig_workaround_hv()
2236 		if (hw->phy.type == e1000_phy_82577) {  in e1000_k1_gig_workaround_hv()
2237 			ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);  in e1000_k1_gig_workaround_hv()
2252 		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);  in e1000_k1_gig_workaround_hv()
2258 		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);  in e1000_k1_gig_workaround_hv()
2263 	ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);  in e1000_k1_gig_workaround_hv()
2266 	hw->phy.ops.release(hw);  in e1000_k1_gig_workaround_hv()
2272  *  e1000_configure_k1_ich8lan - Configure K1 power state
2273  *  @hw: pointer to the HW structure
2279  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2281 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)  in e1000_configure_k1_ich8lan()  argument
2289 	ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,  in e1000_configure_k1_ich8lan()
2299 	ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,  in e1000_configure_k1_ich8lan()
2306 	ctrl_reg = er32(CTRL);  in e1000_configure_k1_ich8lan()
2310 	ew32(CTRL, reg);  in e1000_configure_k1_ich8lan()
2315 	ew32(CTRL, ctrl_reg);  in e1000_configure_k1_ich8lan()
2324  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2325  *  @hw:       pointer to the HW structure
2330  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2332 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)  in e1000_oem_bits_config_ich8lan()  argument
2338 	if (hw->mac.type < e1000_pchlan)  in e1000_oem_bits_config_ich8lan()
2341 	ret_val = hw->phy.ops.acquire(hw);  in e1000_oem_bits_config_ich8lan()
2345 	if (hw->mac.type == e1000_pchlan) {  in e1000_oem_bits_config_ich8lan()
2357 	ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);  in e1000_oem_bits_config_ich8lan()
2379 	/* Set Restart auto-neg to activate the bits */  in e1000_oem_bits_config_ich8lan()
2380 	if ((d0_state || (hw->mac.type != e1000_pchlan)) &&  in e1000_oem_bits_config_ich8lan()
2381 	    !hw->phy.ops.check_reset_block(hw))  in e1000_oem_bits_config_ich8lan()
2384 	ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);  in e1000_oem_bits_config_ich8lan()
2387 	hw->phy.ops.release(hw);  in e1000_oem_bits_config_ich8lan()
2393  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2394  *  @hw:   pointer to the HW structure
2396 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)  in e1000_set_mdio_slow_mode_hv()  argument
2401 	ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);  in e1000_set_mdio_slow_mode_hv()
2407 	ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);  in e1000_set_mdio_slow_mode_hv()
2413  *  e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2414  *  @hw: pointer to the HW structure
2418 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)  in e1000_hv_phy_workarounds_ich8lan()  argument
2423 	if (hw->mac.type != e1000_pchlan)  in e1000_hv_phy_workarounds_ich8lan()
2427 	if (hw->phy.type == e1000_phy_82577) {  in e1000_hv_phy_workarounds_ich8lan()
2428 		ret_val = e1000_set_mdio_slow_mode_hv(hw);  in e1000_hv_phy_workarounds_ich8lan()
2433 	if (((hw->phy.type == e1000_phy_82577) &&  in e1000_hv_phy_workarounds_ich8lan()
2434 	     ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||  in e1000_hv_phy_workarounds_ich8lan()
2435 	    ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {  in e1000_hv_phy_workarounds_ich8lan()
2437 		ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);  in e1000_hv_phy_workarounds_ich8lan()
2442 		ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);  in e1000_hv_phy_workarounds_ich8lan()
2447 	if (hw->phy.type == e1000_phy_82578) {  in e1000_hv_phy_workarounds_ich8lan()
2451 		if (hw->phy.revision < 2) {  in e1000_hv_phy_workarounds_ich8lan()
2452 			e1000e_phy_sw_reset(hw);  in e1000_hv_phy_workarounds_ich8lan()
2453 			ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);  in e1000_hv_phy_workarounds_ich8lan()
2460 	ret_val = hw->phy.ops.acquire(hw);  in e1000_hv_phy_workarounds_ich8lan()
2464 	hw->phy.addr = 1;  in e1000_hv_phy_workarounds_ich8lan()
2465 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);  in e1000_hv_phy_workarounds_ich8lan()
2466 	hw->phy.ops.release(hw);  in e1000_hv_phy_workarounds_ich8lan()
2473 	ret_val = e1000_k1_gig_workaround_hv(hw, true);  in e1000_hv_phy_workarounds_ich8lan()
2478 	ret_val = hw->phy.ops.acquire(hw);  in e1000_hv_phy_workarounds_ich8lan()
2481 	ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);  in e1000_hv_phy_workarounds_ich8lan()
2484 	ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);  in e1000_hv_phy_workarounds_ich8lan()
2489 	ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);  in e1000_hv_phy_workarounds_ich8lan()
2491 	hw->phy.ops.release(hw);  in e1000_hv_phy_workarounds_ich8lan()
2497  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2498  *  @hw:   pointer to the HW structure
2500 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)  in e1000_copy_rx_addrs_to_phy_ich8lan()  argument
2506 	ret_val = hw->phy.ops.acquire(hw);  in e1000_copy_rx_addrs_to_phy_ich8lan()
2509 	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);  in e1000_copy_rx_addrs_to_phy_ich8lan()
2514 	for (i = 0; i < (hw->mac.rar_entry_count); i++) {  in e1000_copy_rx_addrs_to_phy_ich8lan()
2516 		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),  in e1000_copy_rx_addrs_to_phy_ich8lan()
2518 		hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),  in e1000_copy_rx_addrs_to_phy_ich8lan()
2522 		hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),  in e1000_copy_rx_addrs_to_phy_ich8lan()
2524 		hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),  in e1000_copy_rx_addrs_to_phy_ich8lan()
2529 	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);  in e1000_copy_rx_addrs_to_phy_ich8lan()
2532 	hw->phy.ops.release(hw);  in e1000_copy_rx_addrs_to_phy_ich8lan()
2536  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2538  *  @hw: pointer to the HW structure
2541 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)  in e1000_lv_jumbo_workaround_ich8lan()  argument
2548 	if (hw->mac.type < e1000_pch2lan)  in e1000_lv_jumbo_workaround_ich8lan()
2552 	e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);  in e1000_lv_jumbo_workaround_ich8lan()
2553 	ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));  in e1000_lv_jumbo_workaround_ich8lan()
2561 		for (i = 0; i < hw->mac.rar_entry_count; i++) {  in e1000_lv_jumbo_workaround_ich8lan()
2580 		e1000_copy_rx_addrs_to_phy_ich8lan(hw);  in e1000_lv_jumbo_workaround_ich8lan()
2592 		ret_val = e1000e_read_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2597 		ret_val = e1000e_write_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2602 		ret_val = e1000e_read_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2609 		ret_val = e1000e_write_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2616 		e1e_rphy(hw, PHY_REG(769, 23), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2619 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);  in e1000_lv_jumbo_workaround_ich8lan()
2622 		e1e_rphy(hw, PHY_REG(769, 16), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2624 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);  in e1000_lv_jumbo_workaround_ich8lan()
2627 		e1e_rphy(hw, PHY_REG(776, 20), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2630 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);  in e1000_lv_jumbo_workaround_ich8lan()
2633 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);  in e1000_lv_jumbo_workaround_ich8lan()
2636 		e1e_rphy(hw, HV_PM_CTRL, &data);  in e1000_lv_jumbo_workaround_ich8lan()
2637 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));  in e1000_lv_jumbo_workaround_ich8lan()
2650 		ret_val = e1000e_read_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2655 		ret_val = e1000e_write_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2660 		ret_val = e1000e_read_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2667 		ret_val = e1000e_write_kmrn_reg(hw,  in e1000_lv_jumbo_workaround_ich8lan()
2674 		e1e_rphy(hw, PHY_REG(769, 23), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2676 		ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);  in e1000_lv_jumbo_workaround_ich8lan()
2679 		e1e_rphy(hw, PHY_REG(769, 16), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2681 		ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);  in e1000_lv_jumbo_workaround_ich8lan()
2684 		e1e_rphy(hw, PHY_REG(776, 20), &data);  in e1000_lv_jumbo_workaround_ich8lan()
2687 		ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);  in e1000_lv_jumbo_workaround_ich8lan()
2690 		ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);  in e1000_lv_jumbo_workaround_ich8lan()
2693 		e1e_rphy(hw, HV_PM_CTRL, &data);  in e1000_lv_jumbo_workaround_ich8lan()
2694 		ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));  in e1000_lv_jumbo_workaround_ich8lan()
2699 	/* re-enable Rx path after enabling/disabling workaround */  in e1000_lv_jumbo_workaround_ich8lan()
2700 	return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));  in e1000_lv_jumbo_workaround_ich8lan()
2704  *  e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2705  *  @hw: pointer to the HW structure
2709 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)  in e1000_lv_phy_workarounds_ich8lan()  argument
2713 	if (hw->mac.type != e1000_pch2lan)  in e1000_lv_phy_workarounds_ich8lan()
2717 	ret_val = e1000_set_mdio_slow_mode_hv(hw);  in e1000_lv_phy_workarounds_ich8lan()
2721 	ret_val = hw->phy.ops.acquire(hw);  in e1000_lv_phy_workarounds_ich8lan()
2725 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);  in e1000_lv_phy_workarounds_ich8lan()
2729 	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);  in e1000_lv_phy_workarounds_ich8lan()
2731 	hw->phy.ops.release(hw);  in e1000_lv_phy_workarounds_ich8lan()
2737  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2738  *  @hw:   pointer to the HW structure
2743 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)  in e1000_k1_workaround_lv()  argument
2748 	if (hw->mac.type != e1000_pch2lan)  in e1000_k1_workaround_lv()
2752 	ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);  in e1000_k1_workaround_lv()
2763 			ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);  in e1000_k1_workaround_lv()
2767 			ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);  in e1000_k1_workaround_lv()
2784  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2785  *  @hw:   pointer to the HW structure
2791 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)  in e1000_gate_hw_phy_config_ich8lan()  argument
2795 	if (hw->mac.type < e1000_pch2lan)  in e1000_gate_hw_phy_config_ich8lan()
2809  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2810  *  @hw: pointer to the HW structure
2815 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)  in e1000_lan_init_done_ich8lan()  argument
2824 	} while ((!data) && --loop);  in e1000_lan_init_done_ich8lan()
2840  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2841  *  @hw: pointer to the HW structure
2843 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)  in e1000_post_phy_reset_ich8lan()  argument
2848 	if (hw->phy.ops.check_reset_block(hw))  in e1000_post_phy_reset_ich8lan()
2854 	/* Perform any necessary post-reset workarounds */  in e1000_post_phy_reset_ich8lan()
2855 	switch (hw->mac.type) {  in e1000_post_phy_reset_ich8lan()
2857 		ret_val = e1000_hv_phy_workarounds_ich8lan(hw);  in e1000_post_phy_reset_ich8lan()
2862 		ret_val = e1000_lv_phy_workarounds_ich8lan(hw);  in e1000_post_phy_reset_ich8lan()
2871 	if (hw->mac.type >= e1000_pchlan) {  in e1000_post_phy_reset_ich8lan()
2872 		e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);  in e1000_post_phy_reset_ich8lan()
2874 		e1e_wphy(hw, BM_PORT_GEN_CFG, reg);  in e1000_post_phy_reset_ich8lan()
2878 	ret_val = e1000_sw_lcd_config_ich8lan(hw);  in e1000_post_phy_reset_ich8lan()
2883 	ret_val = e1000_oem_bits_config_ich8lan(hw, true);  in e1000_post_phy_reset_ich8lan()
2885 	if (hw->mac.type == e1000_pch2lan) {  in e1000_post_phy_reset_ich8lan()
2886 		/* Ungate automatic PHY configuration on non-managed 82579 */  in e1000_post_phy_reset_ich8lan()
2889 			e1000_gate_hw_phy_config_ich8lan(hw, false);  in e1000_post_phy_reset_ich8lan()
2893 		ret_val = hw->phy.ops.acquire(hw);  in e1000_post_phy_reset_ich8lan()
2896 		ret_val = e1000_write_emi_reg_locked(hw,  in e1000_post_phy_reset_ich8lan()
2899 		hw->phy.ops.release(hw);  in e1000_post_phy_reset_ich8lan()
2906  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2907  *  @hw: pointer to the HW structure
2913 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)  in e1000_phy_hw_reset_ich8lan()  argument
2917 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */  in e1000_phy_hw_reset_ich8lan()
2918 	if ((hw->mac.type == e1000_pch2lan) &&  in e1000_phy_hw_reset_ich8lan()
2920 		e1000_gate_hw_phy_config_ich8lan(hw, true);  in e1000_phy_hw_reset_ich8lan()
2922 	ret_val = e1000e_phy_hw_reset_generic(hw);  in e1000_phy_hw_reset_ich8lan()
2926 	return e1000_post_phy_reset_ich8lan(hw);  in e1000_phy_hw_reset_ich8lan()
2930  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2931  *  @hw: pointer to the HW structure
2937  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2940 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)  in e1000_set_lplu_state_pchlan()  argument
2945 	ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);  in e1000_set_lplu_state_pchlan()
2954 	if (!hw->phy.ops.check_reset_block(hw))  in e1000_set_lplu_state_pchlan()
2957 	return e1e_wphy(hw, HV_OEM_BITS, oem_reg);  in e1000_set_lplu_state_pchlan()
2961  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2962  *  @hw: pointer to the HW structure
2973 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)  in e1000_set_d0_lplu_state_ich8lan()  argument
2975 	struct e1000_phy_info *phy = &hw->phy;  in e1000_set_d0_lplu_state_ich8lan()
2980 	if (phy->type == e1000_phy_ife)  in e1000_set_d0_lplu_state_ich8lan()
2989 		if (phy->type != e1000_phy_igp_3)  in e1000_set_d0_lplu_state_ich8lan()
2995 		if (hw->mac.type == e1000_ich8lan)  in e1000_set_d0_lplu_state_ich8lan()
2996 			e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000_set_d0_lplu_state_ich8lan()
2999 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);  in e1000_set_d0_lplu_state_ich8lan()
3003 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);  in e1000_set_d0_lplu_state_ich8lan()
3010 		if (phy->type != e1000_phy_igp_3)  in e1000_set_d0_lplu_state_ich8lan()
3018 		if (phy->smart_speed == e1000_smart_speed_on) {  in e1000_set_d0_lplu_state_ich8lan()
3019 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d0_lplu_state_ich8lan()
3025 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d0_lplu_state_ich8lan()
3029 		} else if (phy->smart_speed == e1000_smart_speed_off) {  in e1000_set_d0_lplu_state_ich8lan()
3030 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d0_lplu_state_ich8lan()
3036 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d0_lplu_state_ich8lan()
3047  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3048  *  @hw: pointer to the HW structure
3059 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)  in e1000_set_d3_lplu_state_ich8lan()  argument
3061 	struct e1000_phy_info *phy = &hw->phy;  in e1000_set_d3_lplu_state_ich8lan()
3072 		if (phy->type != e1000_phy_igp_3)  in e1000_set_d3_lplu_state_ich8lan()
3080 		if (phy->smart_speed == e1000_smart_speed_on) {  in e1000_set_d3_lplu_state_ich8lan()
3081 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d3_lplu_state_ich8lan()
3087 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d3_lplu_state_ich8lan()
3091 		} else if (phy->smart_speed == e1000_smart_speed_off) {  in e1000_set_d3_lplu_state_ich8lan()
3092 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d3_lplu_state_ich8lan()
3098 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,  in e1000_set_d3_lplu_state_ich8lan()
3103 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||  in e1000_set_d3_lplu_state_ich8lan()
3104 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||  in e1000_set_d3_lplu_state_ich8lan()
3105 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {  in e1000_set_d3_lplu_state_ich8lan()
3109 		if (phy->type != e1000_phy_igp_3)  in e1000_set_d3_lplu_state_ich8lan()
3115 		if (hw->mac.type == e1000_ich8lan)  in e1000_set_d3_lplu_state_ich8lan()
3116 			e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000_set_d3_lplu_state_ich8lan()
3119 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);  in e1000_set_d3_lplu_state_ich8lan()
3124 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);  in e1000_set_d3_lplu_state_ich8lan()
3131  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3132  *  @hw: pointer to the HW structure
3138 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)  in e1000_valid_nvm_bank_detect_ich8lan()  argument
3141 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_valid_nvm_bank_detect_ich8lan()
3142 	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);  in e1000_valid_nvm_bank_detect_ich8lan()
3148 	switch (hw->mac.type) {  in e1000_valid_nvm_bank_detect_ich8lan()
3154 		bank1_offset = nvm->flash_bank_size;  in e1000_valid_nvm_bank_detect_ich8lan()
3161 		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,  in e1000_valid_nvm_bank_detect_ich8lan()
3173 		ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +  in e1000_valid_nvm_bank_detect_ich8lan()
3186 		return -E1000_ERR_NVM;  in e1000_valid_nvm_bank_detect_ich8lan()
3199 		e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");  in e1000_valid_nvm_bank_detect_ich8lan()
3206 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,  in e1000_valid_nvm_bank_detect_ich8lan()
3217 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +  in e1000_valid_nvm_bank_detect_ich8lan()
3229 		return -E1000_ERR_NVM;  in e1000_valid_nvm_bank_detect_ich8lan()
3234  *  e1000_read_nvm_spt - NVM access for SPT
3235  *  @hw: pointer to the HW structure
3242 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,  in e1000_read_nvm_spt()  argument
3245 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_read_nvm_spt()
3246 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_read_nvm_spt()
3254 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_read_nvm_spt()
3257 		ret_val = -E1000_ERR_NVM;  in e1000_read_nvm_spt()
3261 	nvm->ops.acquire(hw);  in e1000_read_nvm_spt()
3263 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);  in e1000_read_nvm_spt()
3269 	act_offset = (bank) ? nvm->flash_bank_size : 0;  in e1000_read_nvm_spt()
3275 		if (words - i == 1) {  in e1000_read_nvm_spt()
3276 			if (dev_spec->shadow_ram[offset + i].modified) {  in e1000_read_nvm_spt()
3278 				    dev_spec->shadow_ram[offset + i].value;  in e1000_read_nvm_spt()
3280 				offset_to_read = act_offset + i -  in e1000_read_nvm_spt()
3283 				  e1000_read_flash_dword_ich8lan(hw,  in e1000_read_nvm_spt()
3295 			if (!(dev_spec->shadow_ram[offset + i].modified) ||  in e1000_read_nvm_spt()
3296 			    !(dev_spec->shadow_ram[offset + i + 1].modified)) {  in e1000_read_nvm_spt()
3298 				  e1000_read_flash_dword_ich8lan(hw,  in e1000_read_nvm_spt()
3304 			if (dev_spec->shadow_ram[offset + i].modified)  in e1000_read_nvm_spt()
3306 				    dev_spec->shadow_ram[offset + i].value;  in e1000_read_nvm_spt()
3309 			if (dev_spec->shadow_ram[offset + i].modified)  in e1000_read_nvm_spt()
3311 				    dev_spec->shadow_ram[offset + i + 1].value;  in e1000_read_nvm_spt()
3317 	nvm->ops.release(hw);  in e1000_read_nvm_spt()
3327  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3328  *  @hw: pointer to the HW structure
3335 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,  in e1000_read_nvm_ich8lan()  argument
3338 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_read_nvm_ich8lan()
3339 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_read_nvm_ich8lan()
3345 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_read_nvm_ich8lan()
3348 		ret_val = -E1000_ERR_NVM;  in e1000_read_nvm_ich8lan()
3352 	nvm->ops.acquire(hw);  in e1000_read_nvm_ich8lan()
3354 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);  in e1000_read_nvm_ich8lan()
3360 	act_offset = (bank) ? nvm->flash_bank_size : 0;  in e1000_read_nvm_ich8lan()
3365 		if (dev_spec->shadow_ram[offset + i].modified) {  in e1000_read_nvm_ich8lan()
3366 			data[i] = dev_spec->shadow_ram[offset + i].value;  in e1000_read_nvm_ich8lan()
3368 			ret_val = e1000_read_flash_word_ich8lan(hw,  in e1000_read_nvm_ich8lan()
3377 	nvm->ops.release(hw);  in e1000_read_nvm_ich8lan()
3387  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3388  *  @hw: pointer to the HW structure
3393 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)  in e1000_flash_cycle_init_ich8lan()  argument
3396 	s32 ret_val = -E1000_ERR_NVM;  in e1000_flash_cycle_init_ich8lan()
3403 		return -E1000_ERR_NVM;  in e1000_flash_cycle_init_ich8lan()
3406 	/* Clear FCERR and DAEL in hw status by writing 1 */  in e1000_flash_cycle_init_ich8lan()
3409 	if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_init_ich8lan()
3428 		if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_init_ich8lan()
3452 			if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_init_ich8lan()
3466  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3467  *  @hw: pointer to the HW structure
3472 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)  in e1000_flash_cycle_ich8lan()  argument
3478 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */  in e1000_flash_cycle_ich8lan()
3479 	if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_ich8lan()
3485 	if (hw->mac.type >= e1000_pch_spt)  in e1000_flash_cycle_ich8lan()
3501 	return -E1000_ERR_NVM;  in e1000_flash_cycle_ich8lan()
3505  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3506  *  @hw: pointer to the HW structure
3513 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_dword_ich8lan()  argument
3518 	return e1000_read_flash_data32_ich8lan(hw, offset, data);  in e1000_read_flash_dword_ich8lan()
3522  *  e1000_read_flash_word_ich8lan - Read word from flash
3523  *  @hw: pointer to the HW structure
3530 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_word_ich8lan()  argument
3536 	return e1000_read_flash_data_ich8lan(hw, offset, 2, data);  in e1000_read_flash_word_ich8lan()
3540  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3541  *  @hw: pointer to the HW structure
3547 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_byte_ich8lan()  argument
3556 	if (hw->mac.type >= e1000_pch_spt)  in e1000_read_flash_byte_ich8lan()
3557 		return -E1000_ERR_NVM;  in e1000_read_flash_byte_ich8lan()
3559 		ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);  in e1000_read_flash_byte_ich8lan()
3570  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3571  *  @hw: pointer to the HW structure
3578 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_data_ich8lan()  argument
3585 	s32 ret_val = -E1000_ERR_NVM;  in e1000_read_flash_data_ich8lan()
3589 		return -E1000_ERR_NVM;  in e1000_read_flash_data_ich8lan()
3592 			     hw->nvm.flash_base_addr);  in e1000_read_flash_data_ich8lan()
3597 		ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_read_flash_data_ich8lan()
3603 		hsflctl.hsf_ctrl.fldbcount = size - 1;  in e1000_read_flash_data_ich8lan()
3610 		    e1000_flash_cycle_ich8lan(hw,  in e1000_read_flash_data_ich8lan()
3636 				e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_read_flash_data_ich8lan()
3646  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3647  *  @hw: pointer to the HW structure
3654 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_read_flash_data32_ich8lan()  argument
3660 	s32 ret_val = -E1000_ERR_NVM;  in e1000_read_flash_data32_ich8lan()
3663 	if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)  in e1000_read_flash_data32_ich8lan()
3664 		return -E1000_ERR_NVM;  in e1000_read_flash_data32_ich8lan()
3666 			     hw->nvm.flash_base_addr);  in e1000_read_flash_data32_ich8lan()
3671 		ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_read_flash_data32_ich8lan()
3680 		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;  in e1000_read_flash_data32_ich8lan()
3689 		   e1000_flash_cycle_ich8lan(hw,  in e1000_read_flash_data32_ich8lan()
3711 				e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_read_flash_data32_ich8lan()
3721  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3722  *  @hw: pointer to the HW structure
3729 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,  in e1000_write_nvm_ich8lan()  argument
3732 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_write_nvm_ich8lan()
3733 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_write_nvm_ich8lan()
3736 	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||  in e1000_write_nvm_ich8lan()
3739 		return -E1000_ERR_NVM;  in e1000_write_nvm_ich8lan()
3742 	nvm->ops.acquire(hw);  in e1000_write_nvm_ich8lan()
3745 		dev_spec->shadow_ram[offset + i].modified = true;  in e1000_write_nvm_ich8lan()
3746 		dev_spec->shadow_ram[offset + i].value = data[i];  in e1000_write_nvm_ich8lan()
3749 	nvm->ops.release(hw);  in e1000_write_nvm_ich8lan()
3755  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3756  *  @hw: pointer to the HW structure
3765 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)  in e1000_update_nvm_checksum_spt()  argument
3767 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_update_nvm_checksum_spt()
3768 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_update_nvm_checksum_spt()
3773 	ret_val = e1000e_update_nvm_checksum_generic(hw);  in e1000_update_nvm_checksum_spt()
3777 	if (nvm->type != e1000_nvm_flash_sw)  in e1000_update_nvm_checksum_spt()
3780 	nvm->ops.acquire(hw);  in e1000_update_nvm_checksum_spt()
3786 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);  in e1000_update_nvm_checksum_spt()
3793 		new_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_spt()
3795 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);  in e1000_update_nvm_checksum_spt()
3799 		old_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_spt()
3801 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);  in e1000_update_nvm_checksum_spt()
3810 		ret_val = e1000_read_flash_dword_ich8lan(hw,  in e1000_update_nvm_checksum_spt()
3814 		if (dev_spec->shadow_ram[i].modified) {  in e1000_update_nvm_checksum_spt()
3816 			dword |= (dev_spec->shadow_ram[i].value & 0xffff);  in e1000_update_nvm_checksum_spt()
3818 		if (dev_spec->shadow_ram[i + 1].modified) {  in e1000_update_nvm_checksum_spt()
3820 			dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)  in e1000_update_nvm_checksum_spt()
3833 		if (i == E1000_ICH_NVM_SIG_WORD - 1)  in e1000_update_nvm_checksum_spt()
3843 		ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,  in e1000_update_nvm_checksum_spt()
3853 		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */  in e1000_update_nvm_checksum_spt()
3866 	--act_offset;  in e1000_update_nvm_checksum_spt()
3867 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);  in e1000_update_nvm_checksum_spt()
3873 	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);  in e1000_update_nvm_checksum_spt()
3886 	act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;  in e1000_update_nvm_checksum_spt()
3887 	ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);  in e1000_update_nvm_checksum_spt()
3893 	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);  in e1000_update_nvm_checksum_spt()
3900 		dev_spec->shadow_ram[i].modified = false;  in e1000_update_nvm_checksum_spt()
3901 		dev_spec->shadow_ram[i].value = 0xFFFF;  in e1000_update_nvm_checksum_spt()
3905 	nvm->ops.release(hw);  in e1000_update_nvm_checksum_spt()
3911 		nvm->ops.reload(hw);  in e1000_update_nvm_checksum_spt()
3923  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3924  *  @hw: pointer to the HW structure
3933 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)  in e1000_update_nvm_checksum_ich8lan()  argument
3935 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_update_nvm_checksum_ich8lan()
3936 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_update_nvm_checksum_ich8lan()
3941 	ret_val = e1000e_update_nvm_checksum_generic(hw);  in e1000_update_nvm_checksum_ich8lan()
3945 	if (nvm->type != e1000_nvm_flash_sw)  in e1000_update_nvm_checksum_ich8lan()
3948 	nvm->ops.acquire(hw);  in e1000_update_nvm_checksum_ich8lan()
3954 	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);  in e1000_update_nvm_checksum_ich8lan()
3961 		new_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_ich8lan()
3963 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);  in e1000_update_nvm_checksum_ich8lan()
3967 		old_bank_offset = nvm->flash_bank_size;  in e1000_update_nvm_checksum_ich8lan()
3969 		ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);  in e1000_update_nvm_checksum_ich8lan()
3974 		if (dev_spec->shadow_ram[i].modified) {  in e1000_update_nvm_checksum_ich8lan()
3975 			data = dev_spec->shadow_ram[i].value;  in e1000_update_nvm_checksum_ich8lan()
3977 			ret_val = e1000_read_flash_word_ich8lan(hw, i +  in e1000_update_nvm_checksum_ich8lan()
3999 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,  in e1000_update_nvm_checksum_ich8lan()
4006 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,  in e1000_update_nvm_checksum_ich8lan()
4017 		/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */  in e1000_update_nvm_checksum_ich8lan()
4028 	ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);  in e1000_update_nvm_checksum_ich8lan()
4033 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,  in e1000_update_nvm_checksum_ich8lan()
4045 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);  in e1000_update_nvm_checksum_ich8lan()
4051 		dev_spec->shadow_ram[i].modified = false;  in e1000_update_nvm_checksum_ich8lan()
4052 		dev_spec->shadow_ram[i].value = 0xFFFF;  in e1000_update_nvm_checksum_ich8lan()
4056 	nvm->ops.release(hw);  in e1000_update_nvm_checksum_ich8lan()
4062 		nvm->ops.reload(hw);  in e1000_update_nvm_checksum_ich8lan()
4074  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4075  *  @hw: pointer to the HW structure
4081 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)  in e1000_validate_nvm_checksum_ich8lan()  argument
4093 	switch (hw->mac.type) {  in e1000_validate_nvm_checksum_ich8lan()
4109 	ret_val = e1000_read_nvm(hw, word, 1, &data);  in e1000_validate_nvm_checksum_ich8lan()
4115 		ret_val = e1000_write_nvm(hw, word, 1, &data);  in e1000_validate_nvm_checksum_ich8lan()
4118 		ret_val = e1000e_update_nvm_checksum(hw);  in e1000_validate_nvm_checksum_ich8lan()
4123 	return e1000e_validate_nvm_checksum_generic(hw);  in e1000_validate_nvm_checksum_ich8lan()
4127  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4128  *  @hw: pointer to the HW structure
4130  *  To prevent malicious write/erase of the NVM, set it to be read-only
4132  *  the flash control registers.  The shadow-ram copy of the NVM will
4136 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)  in e1000e_write_protect_nvm_ich8lan()  argument
4138 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000e_write_protect_nvm_ich8lan()
4143 	nvm->ops.acquire(hw);  in e1000e_write_protect_nvm_ich8lan()
4147 	/* Write-protect GbE Sector of NVM */  in e1000e_write_protect_nvm_ich8lan()
4155 	 * PR0 to prevent the write-protection from being lifted.  in e1000e_write_protect_nvm_ich8lan()
4163 	nvm->ops.release(hw);  in e1000e_write_protect_nvm_ich8lan()
4167  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4168  *  @hw: pointer to the HW structure
4175 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_write_flash_data_ich8lan()  argument
4185 	if (hw->mac.type >= e1000_pch_spt) {  in e1000_write_flash_data_ich8lan()
4187 			return -E1000_ERR_NVM;  in e1000_write_flash_data_ich8lan()
4190 			return -E1000_ERR_NVM;  in e1000_write_flash_data_ich8lan()
4194 			     hw->nvm.flash_base_addr);  in e1000_write_flash_data_ich8lan()
4199 		ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_write_flash_data_ich8lan()
4205 		if (hw->mac.type >= e1000_pch_spt)  in e1000_write_flash_data_ich8lan()
4211 		hsflctl.hsf_ctrl.fldbcount = size - 1;  in e1000_write_flash_data_ich8lan()
4217 		if (hw->mac.type >= e1000_pch_spt)  in e1000_write_flash_data_ich8lan()
4235 		    e1000_flash_cycle_ich8lan(hw,  in e1000_write_flash_data_ich8lan()
4250 			e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_write_flash_data_ich8lan()
4259 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4260 *  @hw: pointer to the HW structure
4266 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_write_flash_data32_ich8lan()  argument
4275 	if (hw->mac.type >= e1000_pch_spt) {  in e1000_write_flash_data32_ich8lan()
4277 			return -E1000_ERR_NVM;  in e1000_write_flash_data32_ich8lan()
4280 			     hw->nvm.flash_base_addr);  in e1000_write_flash_data32_ich8lan()
4284 		ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_write_flash_data32_ich8lan()
4291 		if (hw->mac.type >= e1000_pch_spt)  in e1000_write_flash_data32_ich8lan()
4297 		hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;  in e1000_write_flash_data32_ich8lan()
4304 		if (hw->mac.type >= e1000_pch_spt)  in e1000_write_flash_data32_ich8lan()
4317 		   e1000_flash_cycle_ich8lan(hw,  in e1000_write_flash_data32_ich8lan()
4334 			e_dbg("Timeout error - flash cycle did not complete.\n");  in e1000_write_flash_data32_ich8lan()
4343  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4344  *  @hw: pointer to the HW structure
4350 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,  in e1000_write_flash_byte_ich8lan()  argument
4355 	return e1000_write_flash_data_ich8lan(hw, offset, 1, word);  in e1000_write_flash_byte_ich8lan()
4359 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4360 *  @hw: pointer to the HW structure
4367 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,  in e1000_retry_write_flash_dword_ich8lan()  argument
4375 	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);  in e1000_retry_write_flash_dword_ich8lan()
4382 		ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);  in e1000_retry_write_flash_dword_ich8lan()
4387 		return -E1000_ERR_NVM;  in e1000_retry_write_flash_dword_ich8lan()
4393  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4394  *  @hw: pointer to the HW structure
4401 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,  in e1000_retry_write_flash_byte_ich8lan()  argument
4407 	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);  in e1000_retry_write_flash_byte_ich8lan()
4414 		ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);  in e1000_retry_write_flash_byte_ich8lan()
4419 		return -E1000_ERR_NVM;  in e1000_retry_write_flash_byte_ich8lan()
4425  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4426  *  @hw: pointer to the HW structure
4432 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)  in e1000_erase_flash_bank_ich8lan()  argument
4434 	struct e1000_nvm_info *nvm = &hw->nvm;  in e1000_erase_flash_bank_ich8lan()
4438 	/* bank size is in 16bit words - adjust to bytes */  in e1000_erase_flash_bank_ich8lan()
4439 	u32 flash_bank_size = nvm->flash_bank_size * 2;  in e1000_erase_flash_bank_ich8lan()
4446 	/* Determine HW Sector size: Read BERASE bits of hw flash status  in e1000_erase_flash_bank_ich8lan()
4448 	 * 00: The Hw sector is 256 bytes, hence we need to erase 16  in e1000_erase_flash_bank_ich8lan()
4449 	 *     consecutive sectors.  The start index for the nth Hw sector  in e1000_erase_flash_bank_ich8lan()
4451 	 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.  in e1000_erase_flash_bank_ich8lan()
4452 	 *     The start index for the nth Hw sector can be calculated  in e1000_erase_flash_bank_ich8lan()
4454 	 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192  in e1000_erase_flash_bank_ich8lan()
4456 	 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536  in e1000_erase_flash_bank_ich8lan()
4460 		/* Hw sector size 256 */  in e1000_erase_flash_bank_ich8lan()
4477 		return -E1000_ERR_NVM;  in e1000_erase_flash_bank_ich8lan()
4481 	flash_linear_addr = hw->nvm.flash_base_addr;  in e1000_erase_flash_bank_ich8lan()
4489 			ret_val = e1000_flash_cycle_init_ich8lan(hw);  in e1000_erase_flash_bank_ich8lan()
4494 			 * Cycle field in hw flash control  in e1000_erase_flash_bank_ich8lan()
4496 			if (hw->mac.type >= e1000_pch_spt)  in e1000_erase_flash_bank_ich8lan()
4503 			if (hw->mac.type >= e1000_pch_spt)  in e1000_erase_flash_bank_ich8lan()
4516 			ret_val = e1000_flash_cycle_ich8lan(hw, timeout);  in e1000_erase_flash_bank_ich8lan()
4537  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4538  *  @hw: pointer to the HW structure
4545 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)  in e1000_valid_led_default_ich8lan()  argument
4549 	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);  in e1000_valid_led_default_ich8lan()
4562  *  e1000_id_led_init_pchlan - store LED configurations
4563  *  @hw: pointer to the HW structure
4574 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)  in e1000_id_led_init_pchlan()  argument
4576 	struct e1000_mac_info *mac = &hw->mac;  in e1000_id_led_init_pchlan()
4583 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);  in e1000_id_led_init_pchlan()
4587 	mac->ledctl_default = er32(LEDCTL);  in e1000_id_led_init_pchlan()
4588 	mac->ledctl_mode1 = mac->ledctl_default;  in e1000_id_led_init_pchlan()
4589 	mac->ledctl_mode2 = mac->ledctl_default;  in e1000_id_led_init_pchlan()
4598 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);  in e1000_id_led_init_pchlan()
4599 			mac->ledctl_mode1 |= (ledctl_on << shift);  in e1000_id_led_init_pchlan()
4604 			mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);  in e1000_id_led_init_pchlan()
4605 			mac->ledctl_mode1 |= (ledctl_off << shift);  in e1000_id_led_init_pchlan()
4615 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);  in e1000_id_led_init_pchlan()
4616 			mac->ledctl_mode2 |= (ledctl_on << shift);  in e1000_id_led_init_pchlan()
4621 			mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);  in e1000_id_led_init_pchlan()
4622 			mac->ledctl_mode2 |= (ledctl_off << shift);  in e1000_id_led_init_pchlan()
4634  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4635  *  @hw: pointer to the HW structure
4640 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)  in e1000_get_bus_info_ich8lan()  argument
4642 	struct e1000_bus_info *bus = &hw->bus;  in e1000_get_bus_info_ich8lan()
4645 	ret_val = e1000e_get_bus_info_pcie(hw);  in e1000_get_bus_info_ich8lan()
4647 	/* ICH devices are "PCI Express"-ish.  They have  in e1000_get_bus_info_ich8lan()
4652 	if (bus->width == e1000_bus_width_unknown)  in e1000_get_bus_info_ich8lan()
4653 		bus->width = e1000_bus_width_pcie_x1;  in e1000_get_bus_info_ich8lan()
4659  *  e1000_reset_hw_ich8lan - Reset the hardware
4660  *  @hw: pointer to the HW structure
4665 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)  in e1000_reset_hw_ich8lan()  argument
4667 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_reset_hw_ich8lan()
4669 	u32 ctrl, reg;  in e1000_reset_hw_ich8lan()  local
4672 	/* Prevent the PCI-E bus from sticking if there is no TLP connection  in e1000_reset_hw_ich8lan()
4675 	ret_val = e1000e_disable_pcie_master(hw);  in e1000_reset_hw_ich8lan()
4677 		e_dbg("PCI-E Master disable polling has failed.\n");  in e1000_reset_hw_ich8lan()
4693 	if (hw->mac.type == e1000_ich8lan) {  in e1000_reset_hw_ich8lan()
4700 	if (hw->mac.type == e1000_pchlan) {  in e1000_reset_hw_ich8lan()
4702 		ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);  in e1000_reset_hw_ich8lan()
4707 			dev_spec->nvm_k1_enabled = true;  in e1000_reset_hw_ich8lan()
4709 			dev_spec->nvm_k1_enabled = false;  in e1000_reset_hw_ich8lan()
4712 	ctrl = er32(CTRL);  in e1000_reset_hw_ich8lan()
4714 	if (!hw->phy.ops.check_reset_block(hw)) {  in e1000_reset_hw_ich8lan()
4715 		/* Full-chip reset requires MAC and PHY reset at the same  in e1000_reset_hw_ich8lan()
4719 		ctrl |= E1000_CTRL_PHY_RST;  in e1000_reset_hw_ich8lan()
4722 		 * non-managed 82579  in e1000_reset_hw_ich8lan()
4724 		if ((hw->mac.type == e1000_pch2lan) &&  in e1000_reset_hw_ich8lan()
4726 			e1000_gate_hw_phy_config_ich8lan(hw, true);  in e1000_reset_hw_ich8lan()
4728 	ret_val = e1000_acquire_swflag_ich8lan(hw);  in e1000_reset_hw_ich8lan()
4730 	ew32(CTRL, (ctrl | E1000_CTRL_RST));  in e1000_reset_hw_ich8lan()
4735 	if (hw->mac.type == e1000_pch2lan) {  in e1000_reset_hw_ich8lan()
4743 		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);  in e1000_reset_hw_ich8lan()
4745 	if (ctrl & E1000_CTRL_PHY_RST) {  in e1000_reset_hw_ich8lan()
4746 		ret_val = hw->phy.ops.get_cfg_done(hw);  in e1000_reset_hw_ich8lan()
4750 		ret_val = e1000_post_phy_reset_ich8lan(hw);  in e1000_reset_hw_ich8lan()
4759 	if (hw->mac.type == e1000_pchlan)  in e1000_reset_hw_ich8lan()
4773  *  e1000_init_hw_ich8lan - Initialize the hardware
4774  *  @hw: pointer to the HW structure
4777  *   - initialize hardware bits
4778  *   - initialize LED identification
4779  *   - setup receive address registers
4780  *   - setup flow control
4781  *   - setup transmit descriptors
4782  *   - clear statistics
4784 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)  in e1000_init_hw_ich8lan()  argument
4786 	struct e1000_mac_info *mac = &hw->mac;  in e1000_init_hw_ich8lan()
4791 	e1000_initialize_hw_bits_ich8lan(hw);  in e1000_init_hw_ich8lan()
4794 	ret_val = mac->ops.id_led_init(hw);  in e1000_init_hw_ich8lan()
4800 	e1000e_init_rx_addrs(hw, mac->rar_entry_count);  in e1000_init_hw_ich8lan()
4804 	for (i = 0; i < mac->mta_reg_count; i++)  in e1000_init_hw_ich8lan()
4805 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);  in e1000_init_hw_ich8lan()
4811 	if (hw->phy.type == e1000_phy_82578) {  in e1000_init_hw_ich8lan()
4812 		e1e_rphy(hw, BM_PORT_GEN_CFG, &i);  in e1000_init_hw_ich8lan()
4814 		e1e_wphy(hw, BM_PORT_GEN_CFG, i);  in e1000_init_hw_ich8lan()
4815 		ret_val = e1000_phy_hw_reset_ich8lan(hw);  in e1000_init_hw_ich8lan()
4820 	/* Setup link and flow control */  in e1000_init_hw_ich8lan()
4821 	ret_val = mac->ops.setup_link(hw);  in e1000_init_hw_ich8lan()
4823 	/* Set the transmit descriptor write-back policy for both queues */  in e1000_init_hw_ich8lan()
4840 	if (mac->type == e1000_ich8lan)  in e1000_init_hw_ich8lan()
4844 	e1000e_set_pcie_no_snoop(hw, snoop);  in e1000_init_hw_ich8lan()
4855 	e1000_clear_hw_cntrs_ich8lan(hw);  in e1000_init_hw_ich8lan()
4861  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4862  *  @hw: pointer to the HW structure
4867 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)  in e1000_initialize_hw_bits_ich8lan()  argument
4874 	/* Enable PHY low-power state when MAC is at D3 w/o WoL */  in e1000_initialize_hw_bits_ich8lan()
4875 	if (hw->mac.type >= e1000_pchlan)  in e1000_initialize_hw_bits_ich8lan()
4891 	if (hw->mac.type == e1000_ich8lan)  in e1000_initialize_hw_bits_ich8lan()
4906 	if (hw->mac.type == e1000_ich8lan) {  in e1000_initialize_hw_bits_ich8lan()
4912 	/* work-around descriptor data corruption issue during nfs v2 udp  in e1000_initialize_hw_bits_ich8lan()
4921 	if (hw->mac.type == e1000_ich8lan)  in e1000_initialize_hw_bits_ich8lan()
4926 	if (hw->mac.type >= e1000_pch_lpt) {  in e1000_initialize_hw_bits_ich8lan()
4931 		reg = er32(CTRL);  in e1000_initialize_hw_bits_ich8lan()
4933 		ew32(CTRL, reg);  in e1000_initialize_hw_bits_ich8lan()
4938  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4939  *  @hw: pointer to the HW structure
4941  *  Determines which flow control settings to use, then configures flow
4942  *  control.  Calls the appropriate media-specific link configuration
4947 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)  in e1000_setup_link_ich8lan()  argument
4951 	if (hw->phy.ops.check_reset_block(hw))  in e1000_setup_link_ich8lan()
4955 	 * the default flow control setting, so we explicitly  in e1000_setup_link_ich8lan()
4958 	if (hw->fc.requested_mode == e1000_fc_default) {  in e1000_setup_link_ich8lan()
4959 		/* Workaround h/w hang when Tx flow control enabled */  in e1000_setup_link_ich8lan()
4960 		if (hw->mac.type == e1000_pchlan)  in e1000_setup_link_ich8lan()
4961 			hw->fc.requested_mode = e1000_fc_rx_pause;  in e1000_setup_link_ich8lan()
4963 			hw->fc.requested_mode = e1000_fc_full;  in e1000_setup_link_ich8lan()
4966 	/* Save off the requested flow control mode for use later.  Depending  in e1000_setup_link_ich8lan()
4969 	hw->fc.current_mode = hw->fc.requested_mode;  in e1000_setup_link_ich8lan()
4971 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);  in e1000_setup_link_ich8lan()
4974 	ret_val = hw->mac.ops.setup_physical_interface(hw);  in e1000_setup_link_ich8lan()
4978 	ew32(FCTTV, hw->fc.pause_time);  in e1000_setup_link_ich8lan()
4979 	if ((hw->phy.type == e1000_phy_82578) ||  in e1000_setup_link_ich8lan()
4980 	    (hw->phy.type == e1000_phy_82579) ||  in e1000_setup_link_ich8lan()
4981 	    (hw->phy.type == e1000_phy_i217) ||  in e1000_setup_link_ich8lan()
4982 	    (hw->phy.type == e1000_phy_82577)) {  in e1000_setup_link_ich8lan()
4983 		ew32(FCRTV_PCH, hw->fc.refresh_time);  in e1000_setup_link_ich8lan()
4985 		ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),  in e1000_setup_link_ich8lan()
4986 				   hw->fc.pause_time);  in e1000_setup_link_ich8lan()
4991 	return e1000e_set_fc_watermarks(hw);  in e1000_setup_link_ich8lan()
4995  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4996  *  @hw: pointer to the HW structure
5002 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)  in e1000_setup_copper_link_ich8lan()  argument
5004 	u32 ctrl;  in e1000_setup_copper_link_ich8lan()  local
5008 	ctrl = er32(CTRL);  in e1000_setup_copper_link_ich8lan()
5009 	ctrl |= E1000_CTRL_SLU;  in e1000_setup_copper_link_ich8lan()
5010 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);  in e1000_setup_copper_link_ich8lan()
5011 	ew32(CTRL, ctrl);  in e1000_setup_copper_link_ich8lan()
5017 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);  in e1000_setup_copper_link_ich8lan()
5020 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,  in e1000_setup_copper_link_ich8lan()
5025 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,  in e1000_setup_copper_link_ich8lan()
5030 	switch (hw->phy.type) {  in e1000_setup_copper_link_ich8lan()
5032 		ret_val = e1000e_copper_link_setup_igp(hw);  in e1000_setup_copper_link_ich8lan()
5038 		ret_val = e1000e_copper_link_setup_m88(hw);  in e1000_setup_copper_link_ich8lan()
5044 		ret_val = e1000_copper_link_setup_82577(hw);  in e1000_setup_copper_link_ich8lan()
5049 		ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);  in e1000_setup_copper_link_ich8lan()
5055 		switch (hw->phy.mdix) {  in e1000_setup_copper_link_ich8lan()
5067 		ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);  in e1000_setup_copper_link_ich8lan()
5075 	return e1000e_setup_copper_link(hw);  in e1000_setup_copper_link_ich8lan()
5079  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5080  *  @hw: pointer to the HW structure
5086 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)  in e1000_setup_copper_link_pch_lpt()  argument
5088 	u32 ctrl;  in e1000_setup_copper_link_pch_lpt()  local
5091 	ctrl = er32(CTRL);  in e1000_setup_copper_link_pch_lpt()
5092 	ctrl |= E1000_CTRL_SLU;  in e1000_setup_copper_link_pch_lpt()
5093 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);  in e1000_setup_copper_link_pch_lpt()
5094 	ew32(CTRL, ctrl);  in e1000_setup_copper_link_pch_lpt()
5096 	ret_val = e1000_copper_link_setup_82577(hw);  in e1000_setup_copper_link_pch_lpt()
5100 	return e1000e_setup_copper_link(hw);  in e1000_setup_copper_link_pch_lpt()
5104  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5105  *  @hw: pointer to the HW structure
5113 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,  in e1000_get_link_up_info_ich8lan()  argument
5118 	ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);  in e1000_get_link_up_info_ich8lan()
5122 	if ((hw->mac.type == e1000_ich8lan) &&  in e1000_get_link_up_info_ich8lan()
5123 	    (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {  in e1000_get_link_up_info_ich8lan()
5124 		ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);  in e1000_get_link_up_info_ich8lan()
5131  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5132  *  @hw: pointer to the HW structure
5134  *  Work-around for 82566 Kumeran PCS lock loss:
5136  *  speed is gigabit-
5145 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)  in e1000_kmrn_lock_loss_workaround_ich8lan()  argument
5147 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_kmrn_lock_loss_workaround_ich8lan()
5153 	if (!dev_spec->kmrn_lock_loss_workaround_enabled)  in e1000_kmrn_lock_loss_workaround_ich8lan()
5160 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5166 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5170 		ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5179 		e1000_phy_hw_reset(hw);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5191 	e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000_kmrn_lock_loss_workaround_ich8lan()
5194 	return -E1000_ERR_PHY;  in e1000_kmrn_lock_loss_workaround_ich8lan()
5198  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5199  *  @hw: pointer to the HW structure
5202  *  If ICH8, set the current Kumeran workaround state (enabled - true
5203  *  /disabled - false).
5205 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()  argument
5208 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5210 	if (hw->mac.type != e1000_ich8lan) {  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5215 	dev_spec->kmrn_lock_loss_workaround_enabled = state;  in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5219  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5220  *  @hw: pointer to the HW structure
5222  *  Workaround for 82566 power-down on D3 entry:
5224  *    2) write VR power-down enable
5228 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)  in e1000e_igp3_phy_powerdown_workaround_ich8lan()  argument
5234 	if (hw->phy.type != e1000_phy_igp_3)  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5248 		if (hw->mac.type == e1000_ich8lan)  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5249 			e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5251 		/* Write VR power-down enable */  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5252 		e1e_rphy(hw, IGP3_VR_CTRL, &data);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5254 		e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5257 		e1e_rphy(hw, IGP3_VR_CTRL, &data);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5263 		reg = er32(CTRL);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5264 		ew32(CTRL, reg | E1000_CTRL_PHY_RST);  in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5270  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5271  *  @hw: pointer to the HW structure
5275  *    1) Set Kumeran Near-end loopback
5276  *    2) Clear Kumeran Near-end loopback
5279 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)  in e1000e_gig_downshift_workaround_ich8lan()  argument
5284 	if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))  in e1000e_gig_downshift_workaround_ich8lan()
5287 	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,  in e1000e_gig_downshift_workaround_ich8lan()
5292 	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,  in e1000e_gig_downshift_workaround_ich8lan()
5297 	e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);  in e1000e_gig_downshift_workaround_ich8lan()
5301  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5302  *  @hw: pointer to the HW structure
5314 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)  in e1000_suspend_workarounds_ich8lan()  argument
5316 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;  in e1000_suspend_workarounds_ich8lan()
5323 	if (hw->phy.type == e1000_phy_i217) {  in e1000_suspend_workarounds_ich8lan()
5324 		u16 phy_reg, device_id = hw->adapter->pdev->device;  in e1000_suspend_workarounds_ich8lan()
5330 		    (hw->mac.type >= e1000_pch_spt)) {  in e1000_suspend_workarounds_ich8lan()
5336 		ret_val = hw->phy.ops.acquire(hw);  in e1000_suspend_workarounds_ich8lan()
5340 		if (!dev_spec->eee_disable) {  in e1000_suspend_workarounds_ich8lan()
5344 			    e1000_read_emi_reg_locked(hw,  in e1000_suspend_workarounds_ich8lan()
5356 			    (dev_spec->eee_lp_ability &  in e1000_suspend_workarounds_ich8lan()
5358 			    (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {  in e1000_suspend_workarounds_ich8lan()
5363 				e1e_rphy_locked(hw,  in e1000_suspend_workarounds_ich8lan()
5366 				e1e_wphy_locked(hw,  in e1000_suspend_workarounds_ich8lan()
5380 			e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);  in e1000_suspend_workarounds_ich8lan()
5382 			e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);  in e1000_suspend_workarounds_ich8lan()
5387 			e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);  in e1000_suspend_workarounds_ich8lan()
5389 			e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);  in e1000_suspend_workarounds_ich8lan()
5392 			e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);  in e1000_suspend_workarounds_ich8lan()
5394 			e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);  in e1000_suspend_workarounds_ich8lan()
5400 		e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);  in e1000_suspend_workarounds_ich8lan()
5402 		e1e_wphy_locked(hw, I217_CGFREG, phy_reg);  in e1000_suspend_workarounds_ich8lan()
5405 		hw->phy.ops.release(hw);  in e1000_suspend_workarounds_ich8lan()
5410 	if (hw->mac.type == e1000_ich8lan)  in e1000_suspend_workarounds_ich8lan()
5411 		e1000e_gig_downshift_workaround_ich8lan(hw);  in e1000_suspend_workarounds_ich8lan()
5413 	if (hw->mac.type >= e1000_pchlan) {  in e1000_suspend_workarounds_ich8lan()
5414 		e1000_oem_bits_config_ich8lan(hw, false);  in e1000_suspend_workarounds_ich8lan()
5417 		if (hw->mac.type == e1000_pchlan)  in e1000_suspend_workarounds_ich8lan()
5418 			e1000e_phy_hw_reset_generic(hw);  in e1000_suspend_workarounds_ich8lan()
5420 		ret_val = hw->phy.ops.acquire(hw);  in e1000_suspend_workarounds_ich8lan()
5423 		e1000_write_smbus_addr(hw);  in e1000_suspend_workarounds_ich8lan()
5424 		hw->phy.ops.release(hw);  in e1000_suspend_workarounds_ich8lan()
5429  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5430  *  @hw: pointer to the HW structure
5432  *  During Sx to S0 transitions on non-managed devices or managed devices
5438 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)  in e1000_resume_workarounds_pchlan()  argument
5442 	if (hw->mac.type < e1000_pch2lan)  in e1000_resume_workarounds_pchlan()
5445 	ret_val = e1000_init_phy_workarounds_pchlan(hw);  in e1000_resume_workarounds_pchlan()
5447 		e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);  in e1000_resume_workarounds_pchlan()
5456 	if (hw->phy.type == e1000_phy_i217) {  in e1000_resume_workarounds_pchlan()
5459 		ret_val = hw->phy.ops.acquire(hw);  in e1000_resume_workarounds_pchlan()
5466 		e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);  in e1000_resume_workarounds_pchlan()
5468 		e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);  in e1000_resume_workarounds_pchlan()
5474 			ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);  in e1000_resume_workarounds_pchlan()
5478 			e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);  in e1000_resume_workarounds_pchlan()
5481 			e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);  in e1000_resume_workarounds_pchlan()
5484 		ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);  in e1000_resume_workarounds_pchlan()
5488 		e1e_wphy_locked(hw, I217_CGFREG, phy_reg);  in e1000_resume_workarounds_pchlan()
5492 		hw->phy.ops.release(hw);  in e1000_resume_workarounds_pchlan()
5497  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5498  *  @hw: pointer to the HW structure
5502 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)  in e1000_cleanup_led_ich8lan()  argument
5504 	if (hw->phy.type == e1000_phy_ife)  in e1000_cleanup_led_ich8lan()
5505 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);  in e1000_cleanup_led_ich8lan()
5507 	ew32(LEDCTL, hw->mac.ledctl_default);  in e1000_cleanup_led_ich8lan()
5512  *  e1000_led_on_ich8lan - Turn LEDs on
5513  *  @hw: pointer to the HW structure
5517 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)  in e1000_led_on_ich8lan()  argument
5519 	if (hw->phy.type == e1000_phy_ife)  in e1000_led_on_ich8lan()
5520 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,  in e1000_led_on_ich8lan()
5523 	ew32(LEDCTL, hw->mac.ledctl_mode2);  in e1000_led_on_ich8lan()
5528  *  e1000_led_off_ich8lan - Turn LEDs off
5529  *  @hw: pointer to the HW structure
5533 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)  in e1000_led_off_ich8lan()  argument
5535 	if (hw->phy.type == e1000_phy_ife)  in e1000_led_off_ich8lan()
5536 		return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,  in e1000_led_off_ich8lan()
5540 	ew32(LEDCTL, hw->mac.ledctl_mode1);  in e1000_led_off_ich8lan()
5545  *  e1000_setup_led_pchlan - Configures SW controllable LED
5546  *  @hw: pointer to the HW structure
5550 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)  in e1000_setup_led_pchlan()  argument
5552 	return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);  in e1000_setup_led_pchlan()
5556  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5557  *  @hw: pointer to the HW structure
5561 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)  in e1000_cleanup_led_pchlan()  argument
5563 	return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);  in e1000_cleanup_led_pchlan()
5567  *  e1000_led_on_pchlan - Turn LEDs on
5568  *  @hw: pointer to the HW structure
5572 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)  in e1000_led_on_pchlan()  argument
5574 	u16 data = (u16)hw->mac.ledctl_mode2;  in e1000_led_on_pchlan()
5593 	return e1e_wphy(hw, HV_LED_CONFIG, data);  in e1000_led_on_pchlan()
5597  *  e1000_led_off_pchlan - Turn LEDs off
5598  *  @hw: pointer to the HW structure
5602 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)  in e1000_led_off_pchlan()  argument
5604 	u16 data = (u16)hw->mac.ledctl_mode1;  in e1000_led_off_pchlan()
5623 	return e1e_wphy(hw, HV_LED_CONFIG, data);  in e1000_led_off_pchlan()
5627  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5628  *  @hw: pointer to the HW structure
5631  *  and configure the PHY through s/w for EEPROM-less parts.
5633  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5635  *  to return with error, EEPROM-less silicon would not be able to be reset
5638 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)  in e1000_get_cfg_done_ich8lan()  argument
5644 	e1000e_get_cfg_done_generic(hw);  in e1000_get_cfg_done_ich8lan()
5647 	if (hw->mac.type >= e1000_ich10lan) {  in e1000_get_cfg_done_ich8lan()
5648 		e1000_lan_init_done_ich8lan(hw);  in e1000_get_cfg_done_ich8lan()
5650 		ret_val = e1000e_get_auto_rd_done(hw);  in e1000_get_cfg_done_ich8lan()
5666 		e_dbg("PHY Reset Asserted not set - needs delay\n");  in e1000_get_cfg_done_ich8lan()
5669 	if (hw->mac.type <= e1000_ich9lan) {  in e1000_get_cfg_done_ich8lan()
5671 		    (hw->phy.type == e1000_phy_igp_3)) {  in e1000_get_cfg_done_ich8lan()
5672 			e1000e_phy_init_script_igp3(hw);  in e1000_get_cfg_done_ich8lan()
5675 		if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {  in e1000_get_cfg_done_ich8lan()
5678 			ret_val = -E1000_ERR_CONFIG;  in e1000_get_cfg_done_ich8lan()
5686  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5687  * @hw: pointer to the HW structure
5692 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)  in e1000_power_down_phy_copper_ich8lan()  argument
5695 	if (!(hw->mac.ops.check_mng_mode(hw) ||  in e1000_power_down_phy_copper_ich8lan()
5696 	      hw->phy.ops.check_reset_block(hw)))  in e1000_power_down_phy_copper_ich8lan()
5697 		e1000_power_down_phy_copper(hw);  in e1000_power_down_phy_copper_ich8lan()
5701  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5702  *  @hw: pointer to the HW structure
5707 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)  in e1000_clear_hw_cntrs_ich8lan()  argument
5712 	e1000e_clear_hw_cntrs_base(hw);  in e1000_clear_hw_cntrs_ich8lan()
5729 	if ((hw->phy.type == e1000_phy_82578) ||  in e1000_clear_hw_cntrs_ich8lan()
5730 	    (hw->phy.type == e1000_phy_82579) ||  in e1000_clear_hw_cntrs_ich8lan()
5731 	    (hw->phy.type == e1000_phy_i217) ||  in e1000_clear_hw_cntrs_ich8lan()
5732 	    (hw->phy.type == e1000_phy_82577)) {  in e1000_clear_hw_cntrs_ich8lan()
5733 		ret_val = hw->phy.ops.acquire(hw);  in e1000_clear_hw_cntrs_ich8lan()
5736 		ret_val = hw->phy.ops.set_page(hw,  in e1000_clear_hw_cntrs_ich8lan()
5740 		hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5741 		hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5742 		hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5743 		hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5744 		hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5745 		hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5746 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5747 		hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5748 		hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5749 		hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5750 		hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5751 		hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5752 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5753 		hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);  in e1000_clear_hw_cntrs_ich8lan()
5755 		hw->phy.ops.release(hw);  in e1000_clear_hw_cntrs_ich8lan()