19 #define SC_PPE_RESET_DREQ		0x026C
21 #define PPE_CFG_RX_ADDR			0x100
22 #define PPE_CFG_POOL_GRP		0x300
23 #define PPE_CFG_RX_BUF_SIZE		0x400
24 #define PPE_CFG_RX_FIFO_SIZE		0x500
25 #define PPE_CURR_BUF_CNT		0xa200
27 #define GE_DUPLEX_TYPE			0x08
28 #define GE_MAX_FRM_SIZE_REG		0x3c
29 #define GE_PORT_MODE			0x40
30 #define GE_PORT_EN			0x44
31 #define GE_SHORT_RUNTS_THR_REG		0x50
32 #define GE_TX_LOCAL_PAGE_REG		0x5c
33 #define GE_TRANSMIT_CONTROL_REG		0x60
34 #define GE_CF_CRC_STRIP_REG		0x1b0
35 #define GE_MODE_CHANGE_REG		0x1b4
36 #define GE_RECV_CONTROL_REG		0x1e0
37 #define GE_STATION_MAC_ADDRESS		0x210
39 #define PPE_CFG_BUS_CTRL_REG		0x424
40 #define PPE_CFG_RX_CTRL_REG		0x428
43 #define PPE_CFG_CPU_ADD_ADDR		0x6D0
44 #define PPE_CFG_MAX_FRAME_LEN_REG	0x500
45 #define PPE_CFG_RX_PKT_MODE_REG		0x504
46 #define PPE_CFG_QOS_VMID_GEN		0x520
47 #define PPE_CFG_RX_PKT_INT		0x740
48 #define PPE_INTEN			0x700
49 #define PPE_INTSTS			0x708
50 #define PPE_RINT			0x704
51 #define PPE_CFG_STS_MODE		0x880
53 #define PPE_CFG_CPU_ADD_ADDR		0x580
54 #define PPE_CFG_MAX_FRAME_LEN_REG	0x408
55 #define PPE_CFG_RX_PKT_MODE_REG		0x438
56 #define PPE_CFG_QOS_VMID_GEN		0x500
57 #define PPE_CFG_RX_PKT_INT		0x538
58 #define PPE_INTEN			0x600
59 #define PPE_INTSTS			0x608
60 #define PPE_RINT			0x604
61 #define PPE_CFG_STS_MODE		0x700
64 #define PPE_HIS_RX_PKT_CNT		0x804
66 #define RESET_DREQ_ALL			0xffffffff
77 #define TX_FREE_MEM			BIT(0)
92 #define RX_PKT_DROP			BIT(0)
96 #define SGMII_SPEED_1000		0x08
97 #define SGMII_SPEED_100			0x07
98 #define SGMII_SPEED_10			0x06
99 #define MII_SPEED_100			0x01
100 #define MII_SPEED_10			0x00
102 #define GE_DUPLEX_FULL			BIT(0)
103 #define GE_DUPLEX_HALF			0x00
104 #define GE_MODE_CHANGE_EN		BIT(0)
110 #define GE_RX_STRIP_CRC			BIT(0)
114 #define GE_AUTO_NEG_CTL			BIT(0)
117 #define GE_RX_TIMEOUT			0x04
127 #define PPE_CFG_STS_RX_PKT_CNT_RC	BIT(0)
134 #define CACHE_LINE_MASK			0x3F
143 #define PPE_BUF_SIZE_SHIFT		0
144 #define PPE_TX_BUF_HOLD			0
149 #define PPE_CFG_RX_START_SHIFT		0
151 #define PPE_CFG_BUS_BIG_ENDIEN		BIT(0)
166 #define DRV_VERSION			"v1.0"
302 	u32 val, tmp, timeout = 0;  in hip04_reset_ppe()
309 	} while (val & 0xfff);  in hip04_reset_ppe()
433 	writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),  in hip04_update_mac_address()
444 	return 0;  in hip04_set_mac_address()
452 	unsigned int bytes_compl = 0, pkts_compl = 0;  in hip04_tx_reclaim()
457 	if (count == 0)  in hip04_tx_reclaim()
462 		if (desc->send_addr != 0) {  in hip04_tx_reclaim()
464 				desc->send_addr = 0;  in hip04_tx_reclaim()
473 			priv->tx_phys[tx_tail] = 0;  in hip04_tx_reclaim()
584 	int rx = 0;  in hip04_rx_poll()
602 		priv->rx_phys[priv->rx_head] = 0;  in hip04_rx_poll()
608 		if (0 == len) {  in hip04_rx_poll()
643 		if (--priv->rx_cnt_remaining == 0)  in hip04_rx_poll()
728 	priv->rx_head = 0;  in hip04_mac_open()
729 	priv->rx_cnt_remaining = 0;  in hip04_mac_open()
730 	priv->tx_head = 0;  in hip04_mac_open()
731 	priv->tx_tail = 0;  in hip04_mac_open()
734 	for (i = 0; i < RX_DESC_NUM; i++) {  in hip04_mac_open()
754 	return 0;  in hip04_mac_open()
771 	for (i = 0; i < RX_DESC_NUM; i++) {  in hip04_mac_stop()
775 			priv->rx_phys[i] = 0;  in hip04_mac_stop()
779 	return 0;  in hip04_mac_stop()
806 	return 0;  in hip04_get_coalesce()
823 	return 0;  in hip04_set_coalesce()
863 	for (i = 0; i < RX_DESC_NUM; i++) {  in hip04_alloc_ring()
869 	return 0;  in hip04_alloc_ring()
877 	for (i = 0; i < RX_DESC_NUM; i++)  in hip04_free_ring()
881 	for (i = 0; i < TX_DESC_NUM; i++)  in hip04_free_ring()
909 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in hip04_mac_probe()
923 	ret = of_parse_phandle_with_fixed_args(node, "port-handle", 3, 0, &arg);  in hip04_mac_probe()
924 	if (ret < 0) {  in hip04_mac_probe()
929 	priv->port = arg.args[0];  in hip04_mac_probe()
958 	irq = platform_get_irq(pdev, 0);  in hip04_mac_probe()
959 	if (irq <= 0) {  in hip04_mac_probe()
965 			       0, pdev->name, ndev);  in hip04_mac_probe()
971 	priv->phy_node = of_parse_phandle(node, "phy-handle", 0);  in hip04_mac_probe()
975 					   0, priv->phy_mode);  in hip04_mac_probe()
1010 	return 0;  in hip04_mac_probe()
1035 	return 0;  in hip04_remove()