Lines Matching defs:gfar
635 struct gfar { struct
636 u32 tsec_id; /* 0x.000 - Controller ID register */
637 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
638 u8 res1[8];
639 u32 ievent; /* 0x.010 - Interrupt Event Register */
640 u32 imask; /* 0x.014 - Interrupt Mask Register */
641 u32 edis; /* 0x.018 - Error Disabled Register */
642 u32 emapg; /* 0x.01c - Group Error mapping register */
643 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
644 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
645 u32 ptv; /* 0x.028 - Pause Time Value Register */
646 u32 dmactrl; /* 0x.02c - DMA Control Register */
647 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
648 u8 res2[28];
649 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
651 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
653 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
655 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
657 u8 res3[44];
658 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
659 u8 res4[8];
660 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
661 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
662 u8 res5[96];
663 u32 tctrl; /* 0x.100 - Transmit Control Register */
664 u32 tstat; /* 0x.104 - Transmit Status Register */
665 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
666 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
667 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
668 u32 tqueue; /* 0x.114 - Transmit queue control register */
669 u8 res7[40];
670 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
671 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
672 u8 res8[52];
673 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
674 u8 res9a[4];
675 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
676 u8 res9b[4];
677 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
678 u8 res9c[4];
679 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
680 u8 res9d[4];
681 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
682 u8 res9e[4];
683 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
684 u8 res9f[4];
685 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
686 u8 res9g[4];
687 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
688 u8 res9h[4];
689 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
690 u8 res9[64];
691 u32 tbaseh; /* 0x.200 - TxBD base address high */
692 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
693 u8 res10a[4];
694 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
695 u8 res10b[4];
696 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
697 u8 res10c[4];
698 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
699 u8 res10d[4];
700 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
701 u8 res10e[4];
702 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
703 u8 res10f[4];
704 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
705 u8 res10g[4];
706 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
707 u8 res10[192];
708 u32 rctrl; /* 0x.300 - Receive Control Register */
709 u32 rstat; /* 0x.304 - Receive Status Register */
710 u8 res12[8];
711 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
712 u32 rqueue; /* 0x.314 - Receive queue control register */
713 u32 rir0; /* 0x.318 - Ring mapping register 0 */
714 u32 rir1; /* 0x.31c - Ring mapping register 1 */
715 u32 rir2; /* 0x.320 - Ring mapping register 2 */
716 u32 rir3; /* 0x.324 - Ring mapping register 3 */
717 u8 res13[8];
718 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
719 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
720 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
721 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
722 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
723 u8 res14[56];
724 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
725 u8 res15a[4];
726 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
727 u8 res15b[4];
728 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
729 u8 res15c[4];
730 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
731 u8 res15d[4];
732 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
733 u8 res15e[4];
734 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
735 u8 res15f[4];
736 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
737 u8 res15g[4];
738 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
739 u8 res15h[4];
740 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
741 u8 res16[64];
765 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ argument
766 u32 ifctrl; /* 0x.538 - Interface control register */
767 u32 ifstat; /* 0x.53c - Interface Status Register */
768 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
769 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
770 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
771 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
772 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
773 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
774 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
775 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
776 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
777 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
778 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
779 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
780 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
781 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
782 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
783 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
784 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
785 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
786 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
787 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
788 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
789 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
790 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
791 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
792 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
793 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
794 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
795 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
796 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
797 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
798 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
799 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
800 u8 res20[192];
801 struct rmon_mib rmon; /* 0x.680-0x.73c */
802 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
803 u8 res21[188];
804 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
805 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
806 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
807 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
808 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
809 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
810 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
811 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
812 u8 res22[96];
813 u32 gaddr0; /* 0x.880 - Group address register 0 */
814 u32 gaddr1; /* 0x.884 - Group address register 1 */
815 u32 gaddr2; /* 0x.888 - Group address register 2 */
816 u32 gaddr3; /* 0x.88c - Group address register 3 */
817 u32 gaddr4; /* 0x.890 - Group address register 4 */
818 u32 gaddr5; /* 0x.894 - Group address register 5 */
819 u32 gaddr6; /* 0x.898 - Group address register 6 */
820 u32 gaddr7; /* 0x.89c - Group address register 7 */
821 u8 res23a[352];
822 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
823 u8 res23b[252];
824 u8 res23c[248];
825 u32 attr; /* 0x.bf8 - Attributes Register */
826 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
827 u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
828 u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
829 u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
830 u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
831 u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
832 u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
833 u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
834 u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
835 u8 res24[36];
836 u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
837 u8 res24a[4];
838 u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
839 u8 res24b[4];
840 u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
841 u8 res24c[4];
842 u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
843 u8 res24d[4];
844 u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
845 u8 res24e[4];
846 u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
847 u8 res24f[4];
848 u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
849 u8 res24g[4];
850 u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
851 u8 res24h[4];
852 u8 res24x[556];
853 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
854 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
855 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
856 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
857 u8 res25[16];
858 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
859 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
860 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
861 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
862 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
863 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
864 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
865 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
866 u8 res26[32];
867 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
868 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
869 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
870 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
871 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
872 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
873 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
874 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
875 u8 res27[208];