Lines Matching +full:0 +full:x00580000
50 #define DFLT_FQ_ID 0x00FFFFFF
53 #define PORT_BMI_FIFO_UNITS 0x100
60 #define PORT_IC_OFFSET_UNITS 0x10
64 #define BMI_PORT_REGS_OFFSET 0
65 #define QMI_PORT_REGS_OFFSET 0x400
66 #define HWP_PORT_REGS_OFFSET 0x800
85 #define DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS 0
88 #define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f
90 #define QMI_PORT_CFG_EN 0x80000000
91 #define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000
93 #define QMI_DEQ_CFG_PRI 0x80000000
94 #define QMI_DEQ_CFG_TYPE1 0x10000000
95 #define QMI_DEQ_CFG_TYPE2 0x20000000
96 #define QMI_DEQ_CFG_TYPE3 0x30000000
97 #define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000
98 #define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000
99 #define QMI_DEQ_CFG_SP_MASK 0xf
103 (_type == FMAN_PORT_TYPE_TX ? 0x1400 : 0x400)
106 #define BMI_EBD_EN 0x80000000
108 #define BMI_PORT_CFG_EN 0x80000000
110 #define BMI_PORT_STATUS_BSY 0x80000000
116 #define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000
119 #define BMI_FRAME_END_CS_IGNORE_MASK 0x0000001f
122 #define BMI_RX_FRAME_END_CUT_MASK 0x0000001f
125 #define BMI_IC_TO_EXT_MASK 0x0000001f
127 #define BMI_IC_FROM_INT_MASK 0x0000000f
128 #define BMI_IC_SIZE_MASK 0x0000001f
131 #define BMI_INT_BUF_MARG_MASK 0x0000000f
133 #define BMI_EXT_BUF_MARG_START_MASK 0x000001ff
134 #define BMI_EXT_BUF_MARG_END_MASK 0x000001ff
136 #define BMI_CMD_MR_LEAC 0x00200000
137 #define BMI_CMD_MR_SLEAC 0x00100000
138 #define BMI_CMD_MR_MA 0x00080000
139 #define BMI_CMD_MR_DEAS 0x00040000
144 #define BMI_CMD_TX_MR_DEF 0
146 #define BMI_CMD_ATTR_ORDER 0x80000000
147 #define BMI_CMD_ATTR_SYNC 0x02000000
151 #define BMI_FIFO_PIPELINE_DEPTH_MASK 0x0000000f
158 #define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000
163 #define BMI_PRIORITY_ELEVATION_LEVEL ((0x3FF + 1) * PORT_BMI_FIFO_UNITS)
164 #define BMI_FIFO_THRESHOLD ((0x3FF + 1) * PORT_BMI_FIFO_UNITS)
183 #define NIA_ORDER_RESTOR 0x00800000
184 #define NIA_ENG_BMI 0x00500000
185 #define NIA_ENG_QMI_ENQ 0x00540000
186 #define NIA_ENG_QMI_DEQ 0x00580000
187 #define NIA_ENG_HWP 0x00440000
188 #define NIA_ENG_HWK 0x00480000
189 #define NIA_BMI_AC_ENQ_FRAME 0x00000002
190 #define NIA_BMI_AC_TX_RELEASE 0x000002C0
191 #define NIA_BMI_AC_RELEASE 0x000000C0
192 #define NIA_BMI_AC_TX 0x00000274
193 #define NIA_BMI_AC_FETCH_ALL_FRAME 0x0000020c
196 #define TX_10G_PORT_BASE 0x30
197 #define RX_10G_PORT_BASE 0x10
216 u32 reserved003c[1]; /* (0x03C 0x03F) */
224 u32 reserved0074[0x2]; /* (0x074-0x07C) */
226 u32 reserved0080[0x20]; /* (0x080 0x0FF) */
230 u32 reserved0130[8]; /* 0x130/0x140 - 0x15F reserved - */
233 u32 reserved0184[0x1F]; /* (0x184 0x1FF) */
244 u32 reserved0224[0x16]; /* (0x224 0x27F) */
253 u32 reserved02a0[0x18]; /* (0x2A0 0x2FF) */
254 u32 fmbm_rdcfg[0x3]; /* Rx Debug Configuration */
256 u32 reserved0310[0x3a];
274 u32 reserved0034[0x0e]; /* (0x034-0x6c) */
277 u32 fmbm_tpfcm[0x02];
280 u32 reserved0080[0x60]; /* (0x080-0x200) */
287 u32 reserved0218[0x1A]; /* (0x218-0x280) */
295 u32 reserved029c[16]; /* (0x29C-0x2FF) */
296 u32 fmbm_tdcfg[0x3]; /* Tx Debug Configuration */
298 u32 reserved0310[0x3a]; /* (0x310-0x3FF) */
312 u32 reserved00c[4]; /* 0xn00C - 0xn01B */
315 u32 reserved024[2]; /* 0xn024 - 0x02B */
324 #define HWP_HXS_PHE_REPORT 0x00000800
325 #define HWP_HXS_PCAC_PSTAT 0x00000100
326 #define HWP_HXS_PCAC_PSTOP 0x00000001
327 #define HWP_HXS_TCP_OFFSET 0xA
328 #define HWP_HXS_UDP_OFFSET 0xB
329 #define HWP_HXS_SH_PAD_REM 0x80000000
336 u32 reserved080[(0x3f8 - 0x080) / 4]; /* (0x080-0x3f7) */
511 tmp &= 0xffe0ffff; in init_bmi_rx()
563 return 0; in init_bmi_rx()
573 tmp = 0; in init_bmi_tx()
629 return 0; in init_bmi_tx()
642 return 0; in init_qmi()
655 tmp = 0; in init_qmi()
690 return 0; in init_qmi()
700 while (cnt-- > 0 && in stop_port_hwp()
712 iowrite32be(0, ®s->fmpr_pcac); in start_port_hwp()
714 while (cnt-- > 0 && in start_port_hwp()
728 for (i = 0; i < HWP_HXS_COUNT; i++) { in init_hwp()
730 iowrite32be(0x00000000, ®s->pmda[i].ssa); in init_hwp()
731 iowrite32be(0xffffffff, ®s->pmda[i].lcv); in init_hwp()
767 return 0; in init()
791 for (i = 0; (i < (bp->count - 1) && in set_bpools()
799 for (i = 0; i < bp->count; i++) { in set_bpools()
819 iowrite32be(0, &bp_reg[i]); in set_bpools()
822 tmp = 0; in set_bpools()
823 for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) { in set_bpools()
826 tmp |= 0x80000000 >> i; in set_bpools()
830 tmp |= 0x80 >> i; in set_bpools()
838 return 0; in set_bpools()
852 u32 min_fifo_size_required = 0, opt_fifo_size_for_b2b = 0; in verify_size_of_fifo()
883 /* 4 according to spec + 1 for FOF>0 */ in verify_size_of_fifo()
903 WARN_ON(min_fifo_size_required <= 0); in verify_size_of_fifo()
914 return 0; in verify_size_of_fifo()
924 int i = 0, j = 0, err; in set_ext_buffer_pools()
927 memset(&ordered_array, 0, sizeof(u8) * FMAN_PORT_MAX_EXT_POOLS_NUM); in set_ext_buffer_pools()
928 memset(&sizes_array, 0, sizeof(u16) * BM_MAX_NUM_OF_POOLS); in set_ext_buffer_pools()
936 memset(&bpools, 0, sizeof(struct fman_port_bpools)); in set_ext_buffer_pools()
939 for (i = 0; i < ext_buf_pools->num_of_pools_used; i++) { in set_ext_buffer_pools()
952 for (i = 0; i < port->bm_max_num_of_pools; i++) { in set_ext_buffer_pools()
954 for (j = 0; j < ext_buf_pools-> in set_ext_buffer_pools()
967 for (i = 0; i < port->bm_max_num_of_pools; i++) { in set_ext_buffer_pools()
970 for (j = 0; j < ext_buf_pools-> in set_ext_buffer_pools()
983 if (err != 0) { in set_ext_buffer_pools()
988 return 0; in set_ext_buffer_pools()
1010 if (init(port) != 0) { in init_low_level_driver()
1021 /* override fmbm_tcfqid 0 with a false non-0 value. in init_low_level_driver()
1023 * Otherwise, if fmbm_tcfqid is 0 the FM will release in init_low_level_driver()
1026 iowrite32be(0xFFFFFF, &port->bmi_regs->tx.fmbm_tcfqid); in init_low_level_driver()
1032 return 0; in init_low_level_driver()
1064 return 0; in fill_soc_specific_params()
1082 return 0; in get_dflt_fifo_deq_pipeline_depth()
1085 return 0; in get_dflt_fifo_deq_pipeline_depth()
1104 return 0; in get_dflt_num_of_tasks()
1107 return 0; in get_dflt_num_of_tasks()
1118 return 0; in get_dflt_extra_num_of_tasks()
1127 return 0; in get_dflt_extra_num_of_tasks()
1151 return 0; in get_dflt_num_of_open_dmas()
1163 val = 0; in get_dflt_num_of_open_dmas()
1175 return 0; in get_dflt_extra_num_of_open_dmas()
1186 return 0; in get_dflt_extra_num_of_open_dmas()
1210 val = 0; in get_dflt_num_of_fifo_bufs()
1227 val = 0; in get_dflt_num_of_fifo_bufs()
1258 ((port->rev_info.minor == 0) || (port->rev_info.minor == 3))) in set_dflt_cfg()
1318 * Return: 0 on success; Error code otherwise.
1386 if ((port->rev_info.major == 6) && (port->rev_info.minor == 0) && in fman_port_config()
1390 port->open_dmas.extra = 0; in fman_port_config()
1401 reg = 0x00001013; in fman_port_config()
1405 return 0; in fman_port_config()
1440 * Return: 0 on success; Error code otherwise.
1483 memset(¶ms, 0, sizeof(params)); in fman_port_init()
1524 return 0; in fman_port_init()
1551 * Return: 0 on success; Error code otherwise.
1570 return 0; in fman_port_cfg_buf_prefix_content()
1586 * Return: 0 on success; Error code otherwise.
1625 if (count == 0) { in fman_port_disable()
1642 if (count == 0) { in fman_port_disable()
1651 return 0; in fman_port_disable()
1663 * Return: 0 on success; Error code otherwise.
1697 return 0; in fman_port_enable()
1752 return 0; in fman_port_get_hash_result_offset()
1764 return 0; in fman_port_get_tstamp()
1777 int err = 0, lenp; in fman_port_probe()
1860 if (qman_channel_id == 0) { in fman_port_probe()
1869 err = of_address_to_resource(port_node, 0, &res); in fman_port_probe()
1870 if (err < 0) { in fman_port_probe()
1897 return 0; in fman_port_probe()
1931 if (err < 0) in fman_port_load()