Lines Matching +full:reg +full:- +full:names
2 * Copyright 2008-2015 Freescale Semiconductor Inc.
12 * names of its contributors may be used to endorse or promote products
112 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
113 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
114 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
117 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
118 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
119 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
126 /* 26-31 Hash table address code */
145 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */
172 /* Lower 32 bits of 48-bit MAC address */
174 /* Upper 16 bits of 48-bit MAC address */
182 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */
185 u32 rx_fifo_sections; /* Receive FIFO configuration reg */
186 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */
191 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */
199 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */
365 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l); in add_addr_in_paddr()
366 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u); in add_addr_in_paddr()
368 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l); in add_addr_in_paddr()
369 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u); in add_addr_in_paddr()
378 tmp = ioread32be(®s->command_config); in reset()
382 iowrite32be(tmp, ®s->command_config); in reset()
387 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) && in reset()
388 --count); in reset()
391 return -EBUSY; in reset()
401 tmp = ioread32be(®s->imask); in set_exception()
407 iowrite32be(tmp, ®s->imask); in set_exception()
418 if (cfg->promiscuous_mode_enable) in init()
420 if (cfg->pause_ignore) in init()
430 iowrite32be(tmp, ®s->command_config); in init()
433 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm); in init()
436 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]); in init()
437 iowrite32be((u32)0, ®s->pause_thresh[0]); in init()
453 iowrite32be(tmp, ®s->if_mode); in init()
469 iowrite32be(tmp, ®s->tx_fifo_sections); in init()
471 /* clear all pending events and set-up interrupts */ in init()
472 iowrite32be(0xffffffff, ®s->ievent); in init()
480 cfg->reset_on_init = false; in set_dflts()
481 cfg->promiscuous_mode_enable = false; in set_dflts()
482 cfg->pause_ignore = false; in set_dflts()
483 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH; in set_dflts()
484 cfg->max_frame_length = DEFAULT_FRAME_LENGTH; in set_dflts()
485 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA; in set_dflts()
504 xor_val |= (mask1 << (5 - i)); in get_mac_addr_hash_code()
515 if (WARN_ON(!memac->pcsphy)) in setup_sgmii_internal_phy()
524 switch (fixed_link->speed) { in setup_sgmii_internal_phy()
536 if (!fixed_link->duplex) in setup_sgmii_internal_phy()
539 phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16); in setup_sgmii_internal_phy()
543 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); in setup_sgmii_internal_phy()
545 /* Adjust link timer for SGMII - in setup_sgmii_internal_phy()
548 * - When running as 1G SGMII, Serdes clock is 125 MHz, so in setup_sgmii_internal_phy()
551 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so in setup_sgmii_internal_phy()
557 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H); in setup_sgmii_internal_phy()
558 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L); in setup_sgmii_internal_phy()
566 phy_write(memac->pcsphy, 0x0, tmp_reg16); in setup_sgmii_internal_phy()
575 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16); in setup_sgmii_internal_phy_base_x()
577 /* Adjust link timer for SGMII - in setup_sgmii_internal_phy_base_x()
578 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms. in setup_sgmii_internal_phy_base_x()
580 * - When running as 1G SGMII, Serdes clock is 125 MHz, so in setup_sgmii_internal_phy_base_x()
583 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so in setup_sgmii_internal_phy_base_x()
589 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX); in setup_sgmii_internal_phy_base_x()
590 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX); in setup_sgmii_internal_phy_base_x()
594 phy_write(memac->pcsphy, 0x0, tmp_reg16); in setup_sgmii_internal_phy_base_x()
599 if (!memac->exception_cb) { in check_init_parameters()
601 return -EINVAL; in check_init_parameters()
603 if (!memac->event_cb) { in check_init_parameters()
605 return -EINVAL; in check_init_parameters()
639 struct memac_regs __iomem *regs = memac->regs; in memac_err_exception()
642 event = ioread32be(®s->ievent); in memac_err_exception()
643 imask = ioread32be(®s->imask); in memac_err_exception()
648 * their corresponding location in the ievent - hence the >> 16 in memac_err_exception()
652 iowrite32be(event, ®s->ievent); in memac_err_exception()
655 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR); in memac_err_exception()
657 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER); in memac_err_exception()
659 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER); in memac_err_exception()
665 struct memac_regs __iomem *regs = memac->regs; in memac_exception()
668 event = ioread32be(®s->ievent); in memac_exception()
669 imask = ioread32be(®s->imask); in memac_exception()
674 * their corresponding location in the ievent - hence the >> 16 in memac_exception()
678 iowrite32be(event, ®s->ievent); in memac_exception()
681 memac->exception_cb(memac->dev_id, in memac_exception()
687 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, in free_init_resources()
690 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, in free_init_resources()
694 free_hash_table(memac->multicast_addr_hash); in free_init_resources()
695 memac->multicast_addr_hash = NULL; in free_init_resources()
698 free_hash_table(memac->unicast_addr_hash); in free_init_resources()
699 memac->unicast_addr_hash = NULL; in free_init_resources()
713 struct memac_regs __iomem *regs = memac->regs; in memac_enable()
716 if (!is_init_done(memac->memac_drv_param)) in memac_enable()
717 return -EINVAL; in memac_enable()
719 tmp = ioread32be(®s->command_config); in memac_enable()
725 iowrite32be(tmp, ®s->command_config); in memac_enable()
732 struct memac_regs __iomem *regs = memac->regs; in memac_disable()
735 if (!is_init_done(memac->memac_drv_param)) in memac_disable()
736 return -EINVAL; in memac_disable()
738 tmp = ioread32be(®s->command_config); in memac_disable()
744 iowrite32be(tmp, ®s->command_config); in memac_disable()
751 struct memac_regs __iomem *regs = memac->regs; in memac_set_promiscuous()
754 if (!is_init_done(memac->memac_drv_param)) in memac_set_promiscuous()
755 return -EINVAL; in memac_set_promiscuous()
757 tmp = ioread32be(®s->command_config); in memac_set_promiscuous()
763 iowrite32be(tmp, ®s->command_config); in memac_set_promiscuous()
770 struct memac_regs __iomem *regs = memac->regs; in memac_adjust_link()
773 if (!is_init_done(memac->memac_drv_param)) in memac_adjust_link()
774 return -EINVAL; in memac_adjust_link()
776 tmp = ioread32be(®s->if_mode); in memac_adjust_link()
781 if (phy_interface_mode_is_rgmii(memac->phy_if)) { in memac_adjust_link()
803 iowrite32be(tmp, ®s->if_mode); in memac_adjust_link()
810 if (is_init_done(memac->memac_drv_param)) in memac_cfg_max_frame_len()
811 return -EINVAL; in memac_cfg_max_frame_len()
813 memac->memac_drv_param->max_frame_length = new_val; in memac_cfg_max_frame_len()
820 if (is_init_done(memac->memac_drv_param)) in memac_cfg_reset_on_init()
821 return -EINVAL; in memac_cfg_reset_on_init()
823 memac->memac_drv_param->reset_on_init = enable; in memac_cfg_reset_on_init()
831 if (is_init_done(memac->memac_drv_param)) in memac_cfg_fixed_link()
832 return -EINVAL; in memac_cfg_fixed_link()
834 memac->memac_drv_param->fixed_link = fixed_link; in memac_cfg_fixed_link()
842 struct memac_regs __iomem *regs = memac->regs; in memac_set_tx_pause_frames()
845 if (!is_init_done(memac->memac_drv_param)) in memac_set_tx_pause_frames()
846 return -EINVAL; in memac_set_tx_pause_frames()
848 tmp = ioread32be(®s->tx_fifo_sections); in memac_set_tx_pause_frames()
851 iowrite32be(tmp, ®s->tx_fifo_sections); in memac_set_tx_pause_frames()
853 tmp = ioread32be(®s->command_config); in memac_set_tx_pause_frames()
856 iowrite32be(tmp, ®s->command_config); in memac_set_tx_pause_frames()
858 tmp = ioread32be(®s->pause_quanta[priority / 2]); in memac_set_tx_pause_frames()
864 iowrite32be(tmp, ®s->pause_quanta[priority / 2]); in memac_set_tx_pause_frames()
866 tmp = ioread32be(®s->pause_thresh[priority / 2]); in memac_set_tx_pause_frames()
872 iowrite32be(tmp, ®s->pause_thresh[priority / 2]); in memac_set_tx_pause_frames()
879 struct memac_regs __iomem *regs = memac->regs; in memac_accept_rx_pause_frames()
882 if (!is_init_done(memac->memac_drv_param)) in memac_accept_rx_pause_frames()
883 return -EINVAL; in memac_accept_rx_pause_frames()
885 tmp = ioread32be(®s->command_config); in memac_accept_rx_pause_frames()
891 iowrite32be(tmp, ®s->command_config); in memac_accept_rx_pause_frames()
898 if (!is_init_done(memac->memac_drv_param)) in memac_modify_mac_address()
899 return -EINVAL; in memac_modify_mac_address()
901 add_addr_in_paddr(memac->regs, (u8 *)(*enet_addr), 0); in memac_modify_mac_address()
908 struct memac_regs __iomem *regs = memac->regs; in memac_add_hash_mac_address()
913 if (!is_init_done(memac->memac_drv_param)) in memac_add_hash_mac_address()
914 return -EINVAL; in memac_add_hash_mac_address()
921 return -EINVAL; in memac_add_hash_mac_address()
928 return -ENOMEM; in memac_add_hash_mac_address()
929 hash_entry->addr = addr; in memac_add_hash_mac_address()
930 INIT_LIST_HEAD(&hash_entry->node); in memac_add_hash_mac_address()
932 list_add_tail(&hash_entry->node, in memac_add_hash_mac_address()
933 &memac->multicast_addr_hash->lsts[hash]); in memac_add_hash_mac_address()
934 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl); in memac_add_hash_mac_address()
942 struct memac_regs __iomem *regs = memac->regs; in memac_set_allmulti()
944 if (!is_init_done(memac->memac_drv_param)) in memac_set_allmulti()
945 return -EINVAL; in memac_set_allmulti()
950 ®s->hashtable_ctrl); in memac_set_allmulti()
954 ®s->hashtable_ctrl); in memac_set_allmulti()
957 memac->allmulti_enabled = enable; in memac_set_allmulti()
969 struct memac_regs __iomem *regs = memac->regs; in memac_del_hash_mac_address()
975 if (!is_init_done(memac->memac_drv_param)) in memac_del_hash_mac_address()
976 return -EINVAL; in memac_del_hash_mac_address()
982 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) { in memac_del_hash_mac_address()
984 if (hash_entry && hash_entry->addr == addr) { in memac_del_hash_mac_address()
985 list_del_init(&hash_entry->node); in memac_del_hash_mac_address()
991 if (!memac->allmulti_enabled) { in memac_del_hash_mac_address()
992 if (list_empty(&memac->multicast_addr_hash->lsts[hash])) in memac_del_hash_mac_address()
994 ®s->hashtable_ctrl); in memac_del_hash_mac_address()
1005 if (!is_init_done(memac->memac_drv_param)) in memac_set_exception()
1006 return -EINVAL; in memac_set_exception()
1011 memac->exceptions |= bit_mask; in memac_set_exception()
1013 memac->exceptions &= ~bit_mask; in memac_set_exception()
1016 return -EINVAL; in memac_set_exception()
1018 set_exception(memac->regs, bit_mask, enable); in memac_set_exception()
1033 if (is_init_done(memac->memac_drv_param)) in memac_init()
1034 return -EINVAL; in memac_init()
1040 memac_drv_param = memac->memac_drv_param; in memac_init()
1042 if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4) in memac_init()
1046 if (memac_drv_param->reset_on_init) { in memac_init()
1047 err = reset(memac->regs); in memac_init()
1055 if (memac->addr != 0) { in memac_init()
1056 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr); in memac_init()
1057 add_addr_in_paddr(memac->regs, (u8 *)eth_addr, 0); in memac_init()
1060 fixed_link = memac_drv_param->fixed_link; in memac_init()
1062 init(memac->regs, memac->memac_drv_param, memac->phy_if, in memac_init()
1063 memac->max_speed, slow_10g_if, memac->exceptions); in memac_init()
1068 if ((memac->fm_rev_info.major == 6) && in memac_init()
1069 ((memac->fm_rev_info.minor == 0) || in memac_init()
1070 (memac->fm_rev_info.minor == 3))) { in memac_init()
1071 /* MAC strips CRC from received frames - this workaround in memac_init()
1074 reg32 = ioread32be(&memac->regs->command_config); in memac_init()
1076 iowrite32be(reg32, &memac->regs->command_config); in memac_init()
1079 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) { in memac_init()
1081 if (memac->basex_if) in memac_init()
1085 } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { in memac_init()
1089 /* QSGMII PHY address occupies 3 upper bits of 5-bit in memac_init()
1094 phy_addr = memac->pcsphy->mdio.addr; in memac_init()
1096 memac->pcsphy->mdio.addr = qsmgii_phy_addr; in memac_init()
1097 if (memac->basex_if) in memac_init()
1102 memac->pcsphy->mdio.addr = phy_addr; in memac_init()
1107 err = fman_set_mac_max_frame(memac->fm, memac->mac_id, in memac_init()
1108 memac_drv_param->max_frame_length); in memac_init()
1114 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); in memac_init()
1115 if (!memac->multicast_addr_hash) { in memac_init()
1118 return -ENOMEM; in memac_init()
1121 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE); in memac_init()
1122 if (!memac->unicast_addr_hash) { in memac_init()
1125 return -ENOMEM; in memac_init()
1128 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, in memac_init()
1131 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id, in memac_init()
1135 memac->memac_drv_param = NULL; in memac_init()
1144 if (memac->pcsphy) in memac_free()
1145 put_device(&memac->pcsphy->mdio.dev); in memac_free()
1147 kfree(memac->memac_drv_param); in memac_free()
1159 base_addr = params->base_addr; in memac_config()
1173 memac->memac_drv_param = memac_drv_param; in memac_config()
1177 memac->addr = ENET_ADDR_TO_UINT64(params->addr); in memac_config()
1179 memac->regs = base_addr; in memac_config()
1180 memac->max_speed = params->max_speed; in memac_config()
1181 memac->phy_if = params->phy_if; in memac_config()
1182 memac->mac_id = params->mac_id; in memac_config()
1183 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | in memac_config()
1185 memac->exception_cb = params->exception_cb; in memac_config()
1186 memac->event_cb = params->event_cb; in memac_config()
1187 memac->dev_id = params->dev_id; in memac_config()
1188 memac->fm = params->fm; in memac_config()
1189 memac->basex_if = params->basex_if; in memac_config()
1192 fman_get_revision(memac->fm, &memac->fm_rev_info); in memac_config()
1194 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII || in memac_config()
1195 memac->phy_if == PHY_INTERFACE_MODE_QSGMII) { in memac_config()
1196 if (!params->internal_phy_node) { in memac_config()
1202 memac->pcsphy = of_phy_find_device(params->internal_phy_node); in memac_config()
1203 if (!memac->pcsphy) { in memac_config()