Lines Matching +full:reg +full:- +full:names
2 * Copyright 2008-2015 Freescale Semiconductor Inc.
13 * names of its contributors may be used to endorse or promote products
348 u32 fmfp_fcev[4]; /* FPM FMan-Controller Event 1-4 0x20-0x2f */
349 u32 res0030[4]; /* res 0x30 - 0x3f */
350 u32 fmfp_cee[4]; /* PM FMan-Controller Event 1-4 0x40-0x4f */
351 u32 res0050[4]; /* res 0x50-0x5f */
360 u32 fmfp_drd[16]; /* FPM Data_Ram Data 0-15 0x80 - 0xbf */
369 u32 fmfp_cev[4]; /* FPM CPU Event 1-4 0xe0-0xef */
370 u32 res00f0[4]; /* res 0xf0-0xff */
371 u32 fmfp_ps[50]; /* FPM Port Status 0x100-0x1c7 */
372 u32 res01c8[14]; /* res 0x1c8-0x1ff */
385 u32 res0230[116]; /* res 0x230 - 0x3ff */
386 u32 fmfp_ts[128]; /* 0x400: FPM Task Status 0x400 - 0x5ff */
387 u32 res0600[0x400 - 384];
394 u32 res000c[5]; /* 0x0c - 0x1f */
398 u32 res002c[5]; /* 0x2c - 0x3f */
399 u32 fmbm_arb[8]; /* BMI Arbitration 0x40 - 0x5f */
400 u32 res0060[12]; /* 0x60 - 0x8f */
401 u32 fmbm_dtc[3]; /* Debug Trap Counter 0x90 - 0x9b */
403 u32 fmbm_dcv[3][4]; /* Debug Compare val 0xa0-0xcf */
404 u32 fmbm_dcm[3][4]; /* Debug Compare Mask 0xd0-0xff */
406 u32 fmbm_pp[63]; /* BMI Port Parameters 0x104 - 0x1ff */
408 u32 fmbm_pfs[63]; /* BMI Port FIFO Size 0x204 - 0x2ff */
410 u32 fmbm_spliodn[63]; /* Port Partition ID 0x304 - 0x3ff */
434 u32 res0050[7]; /* 0x50 - 0x6b */
442 u32 res0088[2]; /* 0x88 - 0x8f */
452 } dbg_traps[3]; /* 0x90 - 0xef */
453 u8 res00f0[0x400 - 0xf0]; /* 0xf0 - 0x3ff */
462 u32 fmdmtah; /* FM DMA transfer bus address high reg 0x14 */
463 u32 fmdmtal; /* FM DMA transfer bus address low reg 0x18 */
464 u32 fmdmtcid; /* FM DMA transfer bus communication ID reg 0x1c */
469 u32 fmdmccqdr; /* FM DMA CAM and CMD Queue Debug reg 0x30 */
470 u32 fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */
471 u32 fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */
481 u32 fmdmplr[FMAN_LIODN_TBL / 2]; /* DMA LIODN regs 0x60-0xdf */
482 u32 res00e0[0x400 - 56];
488 u32 res[(0x1000 - 0x848) / 4]; /* 0x848..0xFFF */
577 dev_dbg(fman->dev, "%s: FMan[%d] exception %d\n", in fman_exceptions()
578 __func__, fman->state->fm_id, exception); in fman_exceptions()
588 dev_dbg(fman->dev, "%s: FMan[%d] bus error: port_id[%d]\n", in fman_bus_error()
589 __func__, fman->state->fm_id, port_id); in fman_bus_error()
596 if (fman->intr_mng[id].isr_cb) { in call_mac_isr()
597 fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle); in call_mac_isr()
610 sw_port_id = hw_port_id - BASE_TX_PORTID; in hw_port_id_to_sw_port_id()
612 sw_port_id = hw_port_id - BASE_RX_PORTID; in hw_port_id_to_sw_port_id()
634 iowrite32be(tmp, &fpm_rg->fmfp_prc); in set_port_order_restoration()
642 iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]); in set_port_liodn()
646 tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]); in set_port_liodn()
654 iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]); in set_port_liodn()
661 tmp = ioread32be(&fpm_rg->fm_rcr); in enable_rams_ecc()
663 iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); in enable_rams_ecc()
666 FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); in enable_rams_ecc()
673 tmp = ioread32be(&fpm_rg->fm_rcr); in disable_rams_ecc()
675 iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr); in disable_rams_ecc()
678 &fpm_rg->fm_rcr); in disable_rams_ecc()
685 cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR; in fman_defconfig()
686 cfg->dma_err = DEFAULT_DMA_ERR; in fman_defconfig()
687 cfg->dma_aid_mode = DEFAULT_AID_MODE; in fman_defconfig()
688 cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW; in fman_defconfig()
689 cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH; in fman_defconfig()
690 cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE; in fman_defconfig()
691 cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES; in fman_defconfig()
692 cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE; in fman_defconfig()
693 cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY; in fman_defconfig()
694 cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG; in fman_defconfig()
695 cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT; in fman_defconfig()
696 cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH; in fman_defconfig()
697 cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH; in fman_defconfig()
698 cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH; in fman_defconfig()
699 cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH; in fman_defconfig()
700 cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH; in fman_defconfig()
701 cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH; in fman_defconfig()
702 cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH; in fman_defconfig()
703 cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH; in fman_defconfig()
708 struct fman_dma_regs __iomem *dma_rg = fman->dma_regs; in dma_init()
709 struct fman_cfg *cfg = fman->cfg; in dma_init()
714 /* clear status reg events */ in dma_init()
717 iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr); in dma_init()
721 tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT; in dma_init()
722 if (cfg->exceptions & EX_DMA_BUS_ERROR) in dma_init()
724 if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) | in dma_init()
725 (cfg->exceptions & EX_DMA_READ_ECC) | in dma_init()
726 (cfg->exceptions & EX_DMA_FM_WRITE_ECC)) in dma_init()
728 if (cfg->dma_axi_dbg_num_of_beats) in dma_init()
730 ((cfg->dma_axi_dbg_num_of_beats - 1) in dma_init()
733 tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) & in dma_init()
736 tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT; in dma_init()
737 tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT; in dma_init()
739 iowrite32be(tmp_reg, &dma_rg->fmdmmr); in dma_init()
742 tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer << in dma_init()
744 tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer & in dma_init()
746 tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer & in dma_init()
749 iowrite32be(tmp_reg, &dma_rg->fmdmtr); in dma_init()
752 tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer << in dma_init()
754 tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer & in dma_init()
756 tmp_reg |= cfg->dma_write_buf_tsh_clr_emer & in dma_init()
759 iowrite32be(tmp_reg, &dma_rg->fmdmhy); in dma_init()
762 iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr); in dma_init()
765 iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr); in dma_init()
767 iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr); in dma_init()
770 fman->cam_size = in dma_init()
771 (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY); in dma_init()
772 fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size); in dma_init()
773 if (IS_ERR_VALUE(fman->cam_offset)) { in dma_init()
774 dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n", in dma_init()
776 return -ENOMEM; in dma_init()
779 if (fman->state->rev_info.major == 2) { in dma_init()
782 fman_muram_free_mem(fman->muram, fman->cam_offset, in dma_init()
783 fman->cam_size); in dma_init()
785 fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128; in dma_init()
786 fman->cam_offset = fman_muram_alloc(fman->muram, in dma_init()
787 fman->cam_size); in dma_init()
788 if (IS_ERR_VALUE(fman->cam_offset)) { in dma_init()
789 dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n", in dma_init()
791 return -ENOMEM; in dma_init()
794 if (fman->cfg->dma_cam_num_of_entries % 8 || in dma_init()
795 fman->cfg->dma_cam_num_of_entries > 32) { in dma_init()
796 dev_err(fman->dev, "%s: wrong dma_cam_num_of_entries\n", in dma_init()
798 return -EINVAL; in dma_init()
802 fman_muram_offset_to_vbase(fman->muram, in dma_init()
803 fman->cam_offset); in dma_init()
805 (32 - fman->cfg->dma_cam_num_of_entries)) - 1), in dma_init()
809 fman->cfg->cam_base_addr = fman->cam_offset; in dma_init()
821 tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT); in fpm_init()
822 iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd); in fpm_init()
824 tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) | in fpm_init()
825 ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) | in fpm_init()
826 ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) | in fpm_init()
827 ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT)); in fpm_init()
828 iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1); in fpm_init()
831 (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) | in fpm_init()
832 ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) | in fpm_init()
833 ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) | in fpm_init()
834 ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT)); in fpm_init()
835 iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2); in fpm_init()
843 if (cfg->exceptions & EX_FPM_STALL_ON_TASKS) in fpm_init()
845 if (cfg->exceptions & EX_FPM_SINGLE_ECC) in fpm_init()
847 if (cfg->exceptions & EX_FPM_DOUBLE_ECC) in fpm_init()
849 tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT); in fpm_init()
850 tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT); in fpm_init()
855 iowrite32be(tmp_reg, &fpm_rg->fmfp_ee); in fpm_init()
859 iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]); in fpm_init()
861 /* RAM ECC - enable and clear events */ in fpm_init()
868 iowrite32be(tmp_reg, &fpm_rg->fm_rcr); in fpm_init()
871 if (cfg->exceptions & EX_IRAM_ECC) { in fpm_init()
875 if (cfg->exceptions & EX_MURAM_ECC) { in fpm_init()
879 iowrite32be(tmp_reg, &fpm_rg->fm_rie); in fpm_init()
890 tmp_reg = cfg->fifo_base_addr; in bmi_init()
893 tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) << in bmi_init()
895 iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1); in bmi_init()
897 tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) << in bmi_init()
900 iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2); in bmi_init()
907 BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr); in bmi_init()
909 if (cfg->exceptions & EX_BMI_LIST_RAM_ECC) in bmi_init()
911 if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC) in bmi_init()
913 if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC) in bmi_init()
915 if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC) in bmi_init()
917 iowrite32be(tmp_reg, &bmi_rg->fmbm_ier); in bmi_init()
930 &qmi_rg->fmqm_eie); in qmi_init()
932 if (cfg->exceptions & EX_QMI_DEQ_FROM_UNKNOWN_PORTID) in qmi_init()
934 if (cfg->exceptions & EX_QMI_DOUBLE_ECC) in qmi_init()
937 iowrite32be(tmp_reg, &qmi_rg->fmqm_eien); in qmi_init()
941 iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie); in qmi_init()
942 if (cfg->exceptions & EX_QMI_SINGLE_ECC) in qmi_init()
945 iowrite32be(tmp_reg, &qmi_rg->fmqm_ien); in qmi_init()
951 iowrite32be(HWP_RPIMAC_PEN, &hwp_rg->fmprrpimac); in hwp_init()
960 /* clear&enable global counters - calculate reg and save for later, in enable()
961 * because it's the same reg for QMI enable in enable()
966 cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh; in enable()
968 iowrite32be(BMI_INIT_START, &fman->bmi_regs->fmbm_init); in enable()
970 &fman->qmi_regs->fmqm_gc); in enable()
982 tmp = ioread32be(&fman->dma_regs->fmdmmr); in set_exception()
988 iowrite32be(tmp, &fman->dma_regs->fmdmmr); in set_exception()
993 tmp = ioread32be(&fman->dma_regs->fmdmmr); in set_exception()
998 iowrite32be(tmp, &fman->dma_regs->fmdmmr); in set_exception()
1001 tmp = ioread32be(&fman->fpm_regs->fmfp_ee); in set_exception()
1006 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee); in set_exception()
1009 tmp = ioread32be(&fman->fpm_regs->fmfp_ee); in set_exception()
1014 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee); in set_exception()
1017 tmp = ioread32be(&fman->fpm_regs->fmfp_ee); in set_exception()
1022 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee); in set_exception()
1025 tmp = ioread32be(&fman->qmi_regs->fmqm_ien); in set_exception()
1030 iowrite32be(tmp, &fman->qmi_regs->fmqm_ien); in set_exception()
1033 tmp = ioread32be(&fman->qmi_regs->fmqm_eien); in set_exception()
1038 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien); in set_exception()
1041 tmp = ioread32be(&fman->qmi_regs->fmqm_eien); in set_exception()
1046 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien); in set_exception()
1049 tmp = ioread32be(&fman->bmi_regs->fmbm_ier); in set_exception()
1054 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier); in set_exception()
1057 tmp = ioread32be(&fman->bmi_regs->fmbm_ier); in set_exception()
1062 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier); in set_exception()
1065 tmp = ioread32be(&fman->bmi_regs->fmbm_ier); in set_exception()
1070 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier); in set_exception()
1073 tmp = ioread32be(&fman->bmi_regs->fmbm_ier); in set_exception()
1078 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier); in set_exception()
1081 tmp = ioread32be(&fman->fpm_regs->fm_rie); in set_exception()
1084 enable_rams_ecc(fman->fpm_regs); in set_exception()
1091 disable_rams_ecc(fman->fpm_regs); in set_exception()
1094 iowrite32be(tmp, &fman->fpm_regs->fm_rie); in set_exception()
1097 tmp = ioread32be(&fman->fpm_regs->fm_rie); in set_exception()
1100 enable_rams_ecc(fman->fpm_regs); in set_exception()
1107 disable_rams_ecc(fman->fpm_regs); in set_exception()
1110 iowrite32be(tmp, &fman->fpm_regs->fm_rie); in set_exception()
1113 return -EINVAL; in set_exception()
1122 tmp = ioread32be(&fpm_rg->fmfp_ee); in resume()
1128 iowrite32be(tmp, &fpm_rg->fmfp_ee); in resume()
1133 u8 minor = state->rev_info.minor; in fill_soc_specific_params()
1134 /* P4080 - Major 2 in fill_soc_specific_params()
1135 * P2041/P3041/P5020/P5040 - Major 3 in fill_soc_specific_params()
1136 * Tx/Bx - Major 6 in fill_soc_specific_params()
1138 switch (state->rev_info.major) { in fill_soc_specific_params()
1140 state->bmi_max_fifo_size = 160 * 1024; in fill_soc_specific_params()
1141 state->fm_iram_size = 64 * 1024; in fill_soc_specific_params()
1142 state->dma_thresh_max_commq = 31; in fill_soc_specific_params()
1143 state->dma_thresh_max_buf = 127; in fill_soc_specific_params()
1144 state->qmi_max_num_of_tnums = 64; in fill_soc_specific_params()
1145 state->qmi_def_tnums_thresh = 48; in fill_soc_specific_params()
1146 state->bmi_max_num_of_tasks = 128; in fill_soc_specific_params()
1147 state->max_num_of_open_dmas = 32; in fill_soc_specific_params()
1148 state->fm_port_num_of_cg = 256; in fill_soc_specific_params()
1149 state->num_of_rx_ports = 6; in fill_soc_specific_params()
1150 state->total_fifo_size = 136 * 1024; in fill_soc_specific_params()
1154 state->bmi_max_fifo_size = 160 * 1024; in fill_soc_specific_params()
1155 state->fm_iram_size = 64 * 1024; in fill_soc_specific_params()
1156 state->dma_thresh_max_commq = 31; in fill_soc_specific_params()
1157 state->dma_thresh_max_buf = 127; in fill_soc_specific_params()
1158 state->qmi_max_num_of_tnums = 64; in fill_soc_specific_params()
1159 state->qmi_def_tnums_thresh = 48; in fill_soc_specific_params()
1160 state->bmi_max_num_of_tasks = 128; in fill_soc_specific_params()
1161 state->max_num_of_open_dmas = 32; in fill_soc_specific_params()
1162 state->fm_port_num_of_cg = 256; in fill_soc_specific_params()
1163 state->num_of_rx_ports = 5; in fill_soc_specific_params()
1164 state->total_fifo_size = 100 * 1024; in fill_soc_specific_params()
1168 state->dma_thresh_max_commq = 83; in fill_soc_specific_params()
1169 state->dma_thresh_max_buf = 127; in fill_soc_specific_params()
1170 state->qmi_max_num_of_tnums = 64; in fill_soc_specific_params()
1171 state->qmi_def_tnums_thresh = 32; in fill_soc_specific_params()
1172 state->fm_port_num_of_cg = 256; in fill_soc_specific_params()
1176 state->bmi_max_fifo_size = 192 * 1024; in fill_soc_specific_params()
1177 state->bmi_max_num_of_tasks = 64; in fill_soc_specific_params()
1178 state->max_num_of_open_dmas = 32; in fill_soc_specific_params()
1179 state->num_of_rx_ports = 5; in fill_soc_specific_params()
1181 state->fm_iram_size = 32 * 1024; in fill_soc_specific_params()
1183 state->fm_iram_size = 64 * 1024; in fill_soc_specific_params()
1184 state->total_fifo_size = 156 * 1024; in fill_soc_specific_params()
1188 state->bmi_max_fifo_size = 384 * 1024; in fill_soc_specific_params()
1189 state->fm_iram_size = 64 * 1024; in fill_soc_specific_params()
1190 state->bmi_max_num_of_tasks = 128; in fill_soc_specific_params()
1191 state->max_num_of_open_dmas = 84; in fill_soc_specific_params()
1192 state->num_of_rx_ports = 8; in fill_soc_specific_params()
1193 state->total_fifo_size = 295 * 1024; in fill_soc_specific_params()
1196 return -EINVAL; in fill_soc_specific_params()
1202 return -EINVAL; in fill_soc_specific_params()
1219 if (fman->cam_offset) in free_init_resources()
1220 fman_muram_free_mem(fman->muram, fman->cam_offset, in free_init_resources()
1221 fman->cam_size); in free_init_resources()
1222 if (fman->fifo_offset) in free_init_resources()
1223 fman_muram_free_mem(fman->muram, fman->fifo_offset, in free_init_resources()
1224 fman->fifo_size); in free_init_resources()
1230 struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; in bmi_err_event()
1233 event = ioread32be(&bmi_rg->fmbm_ievr); in bmi_err_event()
1234 mask = ioread32be(&bmi_rg->fmbm_ier); in bmi_err_event()
1237 force = ioread32be(&bmi_rg->fmbm_ifr); in bmi_err_event()
1239 iowrite32be(force & ~event, &bmi_rg->fmbm_ifr); in bmi_err_event()
1241 iowrite32be(event, &bmi_rg->fmbm_ievr); in bmi_err_event()
1244 ret = fman->exception_cb(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC); in bmi_err_event()
1246 ret = fman->exception_cb(fman, FMAN_EX_BMI_LIST_RAM_ECC); in bmi_err_event()
1248 ret = fman->exception_cb(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC); in bmi_err_event()
1250 ret = fman->exception_cb(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC); in bmi_err_event()
1258 struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs; in qmi_err_event()
1261 event = ioread32be(&qmi_rg->fmqm_eie); in qmi_err_event()
1262 mask = ioread32be(&qmi_rg->fmqm_eien); in qmi_err_event()
1266 force = ioread32be(&qmi_rg->fmqm_eif); in qmi_err_event()
1268 iowrite32be(force & ~event, &qmi_rg->fmqm_eif); in qmi_err_event()
1270 iowrite32be(event, &qmi_rg->fmqm_eie); in qmi_err_event()
1273 ret = fman->exception_cb(fman, FMAN_EX_QMI_DOUBLE_ECC); in qmi_err_event()
1275 ret = fman->exception_cb(fman, in qmi_err_event()
1286 struct fman_dma_regs __iomem *dma_rg = fman->dma_regs; in dma_err_event()
1289 status = ioread32be(&dma_rg->fmdmsr); in dma_err_event()
1290 mask = ioread32be(&dma_rg->fmdmmr); in dma_err_event()
1304 iowrite32be(status, &dma_rg->fmdmsr); in dma_err_event()
1309 addr = (u64)ioread32be(&dma_rg->fmdmtal); in dma_err_event()
1310 addr |= ((u64)(ioread32be(&dma_rg->fmdmtah)) << 32); in dma_err_event()
1312 com_id = ioread32be(&dma_rg->fmdmtcid); in dma_err_event()
1316 hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id); in dma_err_event()
1320 ret = fman->bus_error_cb(fman, relative_port_id, addr, tnum, in dma_err_event()
1324 ret = fman->exception_cb(fman, FMAN_EX_DMA_SINGLE_PORT_ECC); in dma_err_event()
1326 ret = fman->exception_cb(fman, FMAN_EX_DMA_READ_ECC); in dma_err_event()
1328 ret = fman->exception_cb(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC); in dma_err_event()
1330 ret = fman->exception_cb(fman, FMAN_EX_DMA_FM_WRITE_ECC); in dma_err_event()
1338 struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; in fpm_err_event()
1341 event = ioread32be(&fpm_rg->fmfp_ee); in fpm_err_event()
1343 iowrite32be(event, &fpm_rg->fmfp_ee); in fpm_err_event()
1347 ret = fman->exception_cb(fman, FMAN_EX_FPM_DOUBLE_ECC); in fpm_err_event()
1349 ret = fman->exception_cb(fman, FMAN_EX_FPM_STALL_ON_TASKS); in fpm_err_event()
1352 ret = fman->exception_cb(fman, FMAN_EX_FPM_SINGLE_ECC); in fpm_err_event()
1360 struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; in muram_err_intr()
1363 event = ioread32be(&fpm_rg->fm_rcr); in muram_err_intr()
1364 mask = ioread32be(&fpm_rg->fm_rie); in muram_err_intr()
1367 iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr); in muram_err_intr()
1370 ret = fman->exception_cb(fman, FMAN_EX_MURAM_ECC); in muram_err_intr()
1378 struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs; in qmi_event()
1381 event = ioread32be(&qmi_rg->fmqm_ie); in qmi_event()
1382 mask = ioread32be(&qmi_rg->fmqm_ien); in qmi_event()
1385 force = ioread32be(&qmi_rg->fmqm_if); in qmi_event()
1387 iowrite32be(force & ~event, &qmi_rg->fmqm_if); in qmi_event()
1389 iowrite32be(event, &qmi_rg->fmqm_ie); in qmi_event()
1392 ret = fman->exception_cb(fman, FMAN_EX_QMI_SINGLE_ECC); in qmi_event()
1399 struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; in enable_time_stamp()
1400 u16 fm_clk_freq = fman->state->fm_clk_freq; in enable_time_stamp()
1403 ts_freq = (u32)(1 << fman->state->count1_micro_bit); in enable_time_stamp()
1418 frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq; in enable_time_stamp()
1420 if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq) in enable_time_stamp()
1424 iowrite32be(tmp, &fpm_rg->fmfp_tsc2); in enable_time_stamp()
1427 iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1); in enable_time_stamp()
1428 fman->state->enabled_time_stamp = true; in enable_time_stamp()
1436 iram = fman->base_addr + IMEM_OFFSET; in clear_iram()
1438 /* Enable the auto-increment */ in clear_iram()
1439 iowrite32be(IRAM_IADD_AIE, &iram->iadd); in clear_iram()
1443 } while ((ioread32be(&iram->iadd) != IRAM_IADD_AIE) && --count); in clear_iram()
1445 return -EBUSY; in clear_iram()
1447 for (i = 0; i < (fman->state->fm_iram_size / 4); i++) in clear_iram()
1448 iowrite32be(0xffffffff, &iram->idata); in clear_iram()
1450 iowrite32be(fman->state->fm_iram_size - 4, &iram->iadd); in clear_iram()
1454 } while ((ioread32be(&iram->idata) != 0xffffffff) && --count); in clear_iram()
1456 return -EBUSY; in clear_iram()
1554 struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; in set_size_of_fifo()
1563 if (extra_fifo && !fman->state->extra_fifo_pool_size) in set_size_of_fifo()
1564 fman->state->extra_fifo_pool_size = in set_size_of_fifo()
1565 fman->state->num_of_rx_ports * FMAN_BMI_FIFO_UNITS; in set_size_of_fifo()
1567 fman->state->extra_fifo_pool_size = in set_size_of_fifo()
1568 max(fman->state->extra_fifo_pool_size, extra_fifo); in set_size_of_fifo()
1571 if ((fman->state->accumulated_fifo_size + fifo) > in set_size_of_fifo()
1572 (fman->state->total_fifo_size - in set_size_of_fifo()
1573 fman->state->extra_fifo_pool_size)) { in set_size_of_fifo()
1574 dev_err(fman->dev, "%s: Requested fifo size and extra size exceed total FIFO size.\n", in set_size_of_fifo()
1576 return -EAGAIN; in set_size_of_fifo()
1580 tmp = (fifo / FMAN_BMI_FIFO_UNITS - 1) | in set_size_of_fifo()
1583 iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]); in set_size_of_fifo()
1586 fman->state->accumulated_fifo_size += fifo; in set_size_of_fifo()
1594 struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; in set_num_of_tasks()
1600 fman->state->extra_tasks_pool_size = in set_num_of_tasks()
1601 max(fman->state->extra_tasks_pool_size, extra_tasks); in set_num_of_tasks()
1604 if ((fman->state->accumulated_num_of_tasks + tasks) > in set_num_of_tasks()
1605 (fman->state->total_num_of_tasks - in set_num_of_tasks()
1606 fman->state->extra_tasks_pool_size)) { in set_num_of_tasks()
1607 …dev_err(fman->dev, "%s: Requested num_of_tasks and extra tasks pool for fm%d exceed total num_of_t… in set_num_of_tasks()
1608 __func__, fman->state->fm_id); in set_num_of_tasks()
1609 return -EAGAIN; in set_num_of_tasks()
1612 fman->state->accumulated_num_of_tasks += tasks; in set_num_of_tasks()
1615 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & in set_num_of_tasks()
1617 tmp |= ((u32)((tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) | in set_num_of_tasks()
1619 iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); in set_num_of_tasks()
1628 struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs; in set_num_of_open_dmas()
1638 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); in set_num_of_open_dmas()
1642 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]); in set_num_of_open_dmas()
1650 fman->state->extra_open_dmas_pool_size = in set_num_of_open_dmas()
1651 (u8)max(fman->state->extra_open_dmas_pool_size, in set_num_of_open_dmas()
1653 fman->state->accumulated_num_of_open_dmas += current_val; in set_num_of_open_dmas()
1660 fman->state->extra_open_dmas_pool_size = in set_num_of_open_dmas()
1661 (u8)max(fman->state->extra_open_dmas_pool_size, in set_num_of_open_dmas()
1664 if ((fman->state->rev_info.major < 6) && in set_num_of_open_dmas()
1665 (fman->state->accumulated_num_of_open_dmas - current_val + in set_num_of_open_dmas()
1666 open_dmas > fman->state->max_num_of_open_dmas)) { in set_num_of_open_dmas()
1667 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds total num_of_open_dmas.\n", in set_num_of_open_dmas()
1668 __func__, fman->state->fm_id); in set_num_of_open_dmas()
1669 return -EAGAIN; in set_num_of_open_dmas()
1670 } else if ((fman->state->rev_info.major >= 6) && in set_num_of_open_dmas()
1671 !((fman->state->rev_info.major == 6) && in set_num_of_open_dmas()
1672 (fman->state->rev_info.minor == 0)) && in set_num_of_open_dmas()
1673 (fman->state->accumulated_num_of_open_dmas - in set_num_of_open_dmas()
1675 fman->state->dma_thresh_max_commq + 1)) { in set_num_of_open_dmas()
1676 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds DMA Command queue (%d)\n", in set_num_of_open_dmas()
1677 __func__, fman->state->fm_id, in set_num_of_open_dmas()
1678 fman->state->dma_thresh_max_commq + 1); in set_num_of_open_dmas()
1679 return -EAGAIN; in set_num_of_open_dmas()
1682 WARN_ON(fman->state->accumulated_num_of_open_dmas < current_val); in set_num_of_open_dmas()
1684 fman->state->accumulated_num_of_open_dmas -= current_val; in set_num_of_open_dmas()
1685 fman->state->accumulated_num_of_open_dmas += open_dmas; in set_num_of_open_dmas()
1687 if (fman->state->rev_info.major < 6) in set_num_of_open_dmas()
1689 (u8)(fman->state->accumulated_num_of_open_dmas + in set_num_of_open_dmas()
1690 fman->state->extra_open_dmas_pool_size); in set_num_of_open_dmas()
1692 /* calculate reg */ in set_num_of_open_dmas()
1693 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) & in set_num_of_open_dmas()
1695 tmp |= (u32)(((open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) | in set_num_of_open_dmas()
1697 iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]); in set_num_of_open_dmas()
1703 tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK; in set_num_of_open_dmas()
1704 tmp |= (u32)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT; in set_num_of_open_dmas()
1705 iowrite32be(tmp, &bmi_rg->fmbm_cfg2); in set_num_of_open_dmas()
1716 base_addr = fman->dts_params.base_addr; in fman_config()
1718 fman->state = kzalloc(sizeof(*fman->state), GFP_KERNEL); in fman_config()
1719 if (!fman->state) in fman_config()
1723 fman->cfg = kzalloc(sizeof(*fman->cfg), GFP_KERNEL); in fman_config()
1724 if (!fman->cfg) in fman_config()
1728 fman->muram = in fman_config()
1729 fman_muram_init(fman->dts_params.muram_res.start, in fman_config()
1730 resource_size(&fman->dts_params.muram_res)); in fman_config()
1731 if (!fman->muram) in fman_config()
1735 fman->state->fm_id = fman->dts_params.id; in fman_config()
1736 fman->state->fm_clk_freq = fman->dts_params.clk_freq; in fman_config()
1737 fman->state->qman_channel_base = fman->dts_params.qman_channel_base; in fman_config()
1738 fman->state->num_of_qman_channels = in fman_config()
1739 fman->dts_params.num_of_qman_channels; in fman_config()
1740 fman->state->res = fman->dts_params.res; in fman_config()
1741 fman->exception_cb = fman_exceptions; in fman_config()
1742 fman->bus_error_cb = fman_bus_error; in fman_config()
1743 fman->fpm_regs = base_addr + FPM_OFFSET; in fman_config()
1744 fman->bmi_regs = base_addr + BMI_OFFSET; in fman_config()
1745 fman->qmi_regs = base_addr + QMI_OFFSET; in fman_config()
1746 fman->dma_regs = base_addr + DMA_OFFSET; in fman_config()
1747 fman->hwp_regs = base_addr + HWP_OFFSET; in fman_config()
1748 fman->kg_regs = base_addr + KG_OFFSET; in fman_config()
1749 fman->base_addr = base_addr; in fman_config()
1751 spin_lock_init(&fman->spinlock); in fman_config()
1752 fman_defconfig(fman->cfg); in fman_config()
1754 fman->state->extra_fifo_pool_size = 0; in fman_config()
1755 fman->state->exceptions = (EX_DMA_BUS_ERROR | in fman_config()
1772 fman_get_revision(fman, &fman->state->rev_info); in fman_config()
1774 err = fill_soc_specific_params(fman->state); in fman_config()
1779 if (fman->state->rev_info.major >= 6) in fman_config()
1780 fman->cfg->dma_aid_mode = FMAN_DMA_AID_OUT_PORT_ID; in fman_config()
1782 fman->cfg->qmi_def_tnums_thresh = fman->state->qmi_def_tnums_thresh; in fman_config()
1784 fman->state->total_num_of_tasks = in fman_config()
1785 (u8)DFLT_TOTAL_NUM_OF_TASKS(fman->state->rev_info.major, in fman_config()
1786 fman->state->rev_info.minor, in fman_config()
1787 fman->state->bmi_max_num_of_tasks); in fman_config()
1789 if (fman->state->rev_info.major < 6) { in fman_config()
1790 fman->cfg->dma_comm_qtsh_clr_emer = in fman_config()
1791 (u8)DFLT_DMA_COMM_Q_LOW(fman->state->rev_info.major, in fman_config()
1792 fman->state->dma_thresh_max_commq); in fman_config()
1794 fman->cfg->dma_comm_qtsh_asrt_emer = in fman_config()
1795 (u8)DFLT_DMA_COMM_Q_HIGH(fman->state->rev_info.major, in fman_config()
1796 fman->state->dma_thresh_max_commq); in fman_config()
1798 fman->cfg->dma_cam_num_of_entries = in fman_config()
1799 DFLT_DMA_CAM_NUM_OF_ENTRIES(fman->state->rev_info.major); in fman_config()
1801 fman->cfg->dma_read_buf_tsh_clr_emer = in fman_config()
1802 DFLT_DMA_READ_INT_BUF_LOW(fman->state->dma_thresh_max_buf); in fman_config()
1804 fman->cfg->dma_read_buf_tsh_asrt_emer = in fman_config()
1805 DFLT_DMA_READ_INT_BUF_HIGH(fman->state->dma_thresh_max_buf); in fman_config()
1807 fman->cfg->dma_write_buf_tsh_clr_emer = in fman_config()
1808 DFLT_DMA_WRITE_INT_BUF_LOW(fman->state->dma_thresh_max_buf); in fman_config()
1810 fman->cfg->dma_write_buf_tsh_asrt_emer = in fman_config()
1811 DFLT_DMA_WRITE_INT_BUF_HIGH(fman->state->dma_thresh_max_buf); in fman_config()
1813 fman->cfg->dma_axi_dbg_num_of_beats = in fman_config()
1820 kfree(fman->cfg); in fman_config()
1822 kfree(fman->state); in fman_config()
1825 return -EINVAL; in fman_config()
1833 if (fman->state->rev_info.major < 6) { in fman_reset()
1834 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc); in fman_reset()
1839 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) & in fman_reset()
1840 FPM_RSTC_FM_RESET) && --count); in fman_reset()
1842 err = -EBUSY; in fman_reset()
1849 u32 devdisr2, reg; in fman_reset() local
1854 "fsl,qoriq-device-config-2.0"); in fman_reset()
1856 dev_err(fman->dev, "%s: Couldn't find guts node\n", in fman_reset()
1863 dev_err(fman->dev, "%s: Couldn't map %pOF regs\n", in fman_reset()
1870 devdisr2 = ioread32be(&guts_regs->devdisr2); in fman_reset()
1871 if (fman->dts_params.id == 0) in fman_reset()
1872 reg = devdisr2 & ~FMAN1_ALL_MACS_MASK; in fman_reset()
1874 reg = devdisr2 & ~FMAN2_ALL_MACS_MASK; in fman_reset()
1877 iowrite32be(reg, &guts_regs->devdisr2); in fman_reset()
1881 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc); in fman_reset()
1887 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) & in fman_reset()
1888 FPM_RSTC_FM_RESET) && --count); in fman_reset()
1894 err = -EBUSY; in fman_reset()
1900 iowrite32be(devdisr2, &guts_regs->devdisr2); in fman_reset()
1912 dev_dbg(fman->dev, "%s: Didn't perform FManV3 reset due to Errata A007273!\n", in fman_reset()
1925 if (is_init_done(fman->cfg)) in fman_init()
1926 return -EINVAL; in fman_init()
1928 fman->state->count1_micro_bit = FM_TIMESTAMP_1_USEC_BIT; in fman_init()
1930 cfg = fman->cfg; in fman_init()
1932 /* clear revision-dependent non existing exception */ in fman_init()
1933 if (fman->state->rev_info.major < 6) in fman_init()
1934 fman->state->exceptions &= ~FMAN_EX_BMI_DISPATCH_RAM_ECC; in fman_init()
1936 if (fman->state->rev_info.major >= 6) in fman_init()
1937 fman->state->exceptions &= ~FMAN_EX_QMI_SINGLE_ECC; in fman_init()
1940 memset_io((void __iomem *)(fman->base_addr + CGP_OFFSET), 0, in fman_init()
1941 fman->state->fm_port_num_of_cg); in fman_init()
1944 * Skipping non-existent port 0 (i = 1) in fman_init()
1949 fman->liodn_offset[i] = in fman_init()
1950 ioread32be(&fman->bmi_regs->fmbm_spliodn[i - 1]); in fman_init()
1953 liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]); in fman_init()
1962 fman->liodn_base[i] = liodn_base; in fman_init()
1969 if (ioread32be(&fman->qmi_regs->fmqm_gs) & QMI_GS_HALT_NOT_BUSY) { in fman_init()
1970 resume(fman->fpm_regs); in fman_init()
1975 } while (((ioread32be(&fman->qmi_regs->fmqm_gs)) & in fman_init()
1976 QMI_GS_HALT_NOT_BUSY) && --count); in fman_init()
1978 dev_warn(fman->dev, "%s: QMI is in halt not busy state\n", in fman_init()
1983 return -EINVAL; in fman_init()
1985 cfg->exceptions = fman->state->exceptions; in fman_init()
1996 fpm_init(fman->fpm_regs, fman->cfg); in fman_init()
2000 fman->fifo_offset = fman_muram_alloc(fman->muram, in fman_init()
2001 fman->state->total_fifo_size); in fman_init()
2002 if (IS_ERR_VALUE(fman->fifo_offset)) { in fman_init()
2004 dev_err(fman->dev, "%s: MURAM alloc for BMI FIFO failed\n", in fman_init()
2006 return -ENOMEM; in fman_init()
2009 cfg->fifo_base_addr = fman->fifo_offset; in fman_init()
2010 cfg->total_fifo_size = fman->state->total_fifo_size; in fman_init()
2011 cfg->total_num_of_tasks = fman->state->total_num_of_tasks; in fman_init()
2012 cfg->clk_freq = fman->state->fm_clk_freq; in fman_init()
2015 bmi_init(fman->bmi_regs, fman->cfg); in fman_init()
2018 qmi_init(fman->qmi_regs, fman->cfg); in fman_init()
2021 hwp_init(fman->hwp_regs); in fman_init()
2024 fman->keygen = keygen_init(fman->kg_regs); in fman_init()
2025 if (!fman->keygen) in fman_init()
2026 return -EINVAL; in fman_init()
2034 kfree(fman->cfg); in fman_init()
2035 fman->cfg = NULL; in fman_init()
2045 if (!is_init_done(fman->cfg)) in fman_set_exception()
2046 return -EINVAL; in fman_set_exception()
2051 fman->state->exceptions |= bit_mask; in fman_set_exception()
2053 fman->state->exceptions &= ~bit_mask; in fman_set_exception()
2055 dev_err(fman->dev, "%s: Undefined exception (%d)\n", in fman_set_exception()
2057 return -EINVAL; in fman_set_exception()
2086 fman->intr_mng[event].isr_cb = isr_cb; in fman_register_intr()
2087 fman->intr_mng[event].src_handle = src_arg; in fman_register_intr()
2110 fman->intr_mng[event].isr_cb = NULL; in fman_unregister_intr()
2111 fman->intr_mng[event].src_handle = NULL; in fman_unregister_intr()
2129 u8 port_id = port_params->port_id, mac_id; in fman_set_port_params()
2131 spin_lock_irqsave(&fman->spinlock, flags); in fman_set_port_params()
2133 err = set_num_of_tasks(fman, port_params->port_id, in fman_set_port_params()
2134 &port_params->num_of_tasks, in fman_set_port_params()
2135 &port_params->num_of_extra_tasks); in fman_set_port_params()
2140 if (port_params->port_type != FMAN_PORT_TYPE_RX) { in fman_set_port_params()
2141 u32 enq_th, deq_th, reg; in fman_set_port_params() local
2144 fman->state->accumulated_num_of_deq_tnums += in fman_set_port_params()
2145 port_params->deq_pipeline_depth; in fman_set_port_params()
2146 enq_th = (ioread32be(&fman->qmi_regs->fmqm_gc) & in fman_set_port_params()
2151 if (enq_th >= (fman->state->qmi_max_num_of_tnums - in fman_set_port_params()
2152 fman->state->accumulated_num_of_deq_tnums)) { in fman_set_port_params()
2154 fman->state->qmi_max_num_of_tnums - in fman_set_port_params()
2155 fman->state->accumulated_num_of_deq_tnums - 1; in fman_set_port_params()
2157 reg = ioread32be(&fman->qmi_regs->fmqm_gc); in fman_set_port_params()
2158 reg &= ~QMI_CFG_ENQ_MASK; in fman_set_port_params()
2159 reg |= (enq_th << QMI_CFG_ENQ_SHIFT); in fman_set_port_params()
2160 iowrite32be(reg, &fman->qmi_regs->fmqm_gc); in fman_set_port_params()
2163 deq_th = ioread32be(&fman->qmi_regs->fmqm_gc) & in fman_set_port_params()
2168 * (fman->state->qmi_max_num_of_tnums-1). in fman_set_port_params()
2170 if ((deq_th <= fman->state->accumulated_num_of_deq_tnums) && in fman_set_port_params()
2171 (deq_th < fman->state->qmi_max_num_of_tnums - 1)) { in fman_set_port_params()
2172 deq_th = fman->state->accumulated_num_of_deq_tnums + 1; in fman_set_port_params()
2173 reg = ioread32be(&fman->qmi_regs->fmqm_gc); in fman_set_port_params()
2174 reg &= ~QMI_CFG_DEQ_MASK; in fman_set_port_params()
2175 reg |= deq_th; in fman_set_port_params()
2176 iowrite32be(reg, &fman->qmi_regs->fmqm_gc); in fman_set_port_params()
2180 err = set_size_of_fifo(fman, port_params->port_id, in fman_set_port_params()
2181 &port_params->size_of_fifo, in fman_set_port_params()
2182 &port_params->extra_size_of_fifo); in fman_set_port_params()
2186 err = set_num_of_open_dmas(fman, port_params->port_id, in fman_set_port_params()
2187 &port_params->num_of_open_dmas, in fman_set_port_params()
2188 &port_params->num_of_extra_open_dmas); in fman_set_port_params()
2192 set_port_liodn(fman, port_id, fman->liodn_base[port_id], in fman_set_port_params()
2193 fman->liodn_offset[port_id]); in fman_set_port_params()
2195 if (fman->state->rev_info.major < 6) in fman_set_port_params()
2196 set_port_order_restoration(fman->fpm_regs, port_id); in fman_set_port_params()
2198 mac_id = hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id); in fman_set_port_params()
2200 if (port_params->max_frame_length >= fman->state->mac_mfl[mac_id]) { in fman_set_port_params()
2201 fman->state->port_mfl[mac_id] = port_params->max_frame_length; in fman_set_port_params()
2203 dev_warn(fman->dev, "%s: Port (%d) max_frame_length is smaller than MAC (%d) current MTU\n", in fman_set_port_params()
2205 err = -EINVAL; in fman_set_port_params()
2209 spin_unlock_irqrestore(&fman->spinlock, flags); in fman_set_port_params()
2214 spin_unlock_irqrestore(&fman->spinlock, flags); in fman_set_port_params()
2230 struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs; in fman_reset_mac()
2233 if (fman->state->rev_info.major >= 6) { in fman_reset_mac()
2234 dev_err(fman->dev, "%s: FMan MAC reset no available for FMan V3!\n", in fman_reset_mac()
2236 return -EINVAL; in fman_reset_mac()
2272 dev_warn(fman->dev, "%s: Illegal MAC Id [%d]\n", in fman_reset_mac()
2274 return -EINVAL; in fman_reset_mac()
2278 iowrite32be(msk, &fpm_rg->fm_rstc); in fman_reset_mac()
2279 while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout) in fman_reset_mac()
2283 return -EIO; in fman_reset_mac()
2304 if ((!fman->state->port_mfl[mac_id]) || in fman_set_mac_max_frame()
2305 (mfl <= fman->state->port_mfl[mac_id])) { in fman_set_mac_max_frame()
2306 fman->state->mac_mfl[mac_id] = mfl; in fman_set_mac_max_frame()
2308 dev_warn(fman->dev, "%s: MAC max_frame_length is larger than Port max_frame_length\n", in fman_set_mac_max_frame()
2310 return -EINVAL; in fman_set_mac_max_frame()
2326 return fman->state->fm_clk_freq; in fman_get_clock_freq()
2339 return fman->state->bmi_max_fifo_size; in fman_get_bmi_max_fifo_size()
2345 * @fman: - Pointer to the FMan module
2346 * @rev_info: - A structure of revision information parameters.
2358 tmp = ioread32be(&fman->fpm_regs->fm_ip_rev_1); in fman_get_revision()
2359 rev_info->major = (u8)((tmp & FPM_REV1_MAJOR_MASK) >> in fman_get_revision()
2361 rev_info->minor = tmp & FPM_REV1_MINOR_MASK; in fman_get_revision()
2378 if (fman->state->rev_info.major >= 6) { in fman_get_qman_channel_id()
2384 for (i = 0; i < fman->state->num_of_qman_channels; i++) { in fman_get_qman_channel_id()
2394 for (i = 0; i < fman->state->num_of_qman_channels; i++) { in fman_get_qman_channel_id()
2400 if (i == fman->state->num_of_qman_channels) in fman_get_qman_channel_id()
2403 return fman->state->qman_channel_base + i; in fman_get_qman_channel_id()
2417 return fman->state->res; in fman_get_mem_region()
2422 /* Extra headroom for RX buffers - Default, min and max */
2467 …pr_warn("Invalid fsl_fm_max_frm value (%d) in bootargs, valid range is %d-%d. Falling back to the … in fman_get_max_frm()
2493 …pr_warn("Invalid fsl_fm_rx_extra_headroom value (%d) in bootargs, valid range is %d-%d. Falling ba… in fman_get_rx_extra_headroom()
2540 if (!is_init_done(fman->cfg)) in fman_err_irq()
2543 fpm_rg = fman->fpm_regs; in fman_err_irq()
2546 pending = ioread32be(&fpm_rg->fm_epi); in fman_err_irq()
2638 if (!is_init_done(fman->cfg)) in fman_irq()
2641 fpm_rg = fman->fpm_regs; in fman_irq()
2644 pending = ioread32be(&fpm_rg->fm_npi); in fman_irq()
2711 .compatible = "fsl,fman-muram"},
2732 fm_node = of_node_get(of_dev->dev.of_node); in read_dts_node()
2734 err = of_property_read_u32(fm_node, "cell-index", &val); in read_dts_node()
2736 dev_err(&of_dev->dev, "%s: failed to read cell-index for %pOF\n", in read_dts_node()
2740 fman->dts_params.id = (u8)val; in read_dts_node()
2745 dev_err(&of_dev->dev, "%s: Can't get FMan IRQ resource\n", in read_dts_node()
2749 irq = res->start; in read_dts_node()
2754 dev_err(&of_dev->dev, "%s: Can't get FMan Error IRQ resource\n", in read_dts_node()
2758 fman->dts_params.err_irq = res->start; in read_dts_node()
2763 dev_err(&of_dev->dev, "%s: Can't get FMan memory resource\n", in read_dts_node()
2768 phys_base_addr = res->start; in read_dts_node()
2773 dev_err(&of_dev->dev, "%s: Failed to get FM%d clock structure\n", in read_dts_node()
2774 __func__, fman->dts_params.id); in read_dts_node()
2780 dev_err(&of_dev->dev, "%s: Failed to determine FM%d clock rate\n", in read_dts_node()
2781 __func__, fman->dts_params.id); in read_dts_node()
2785 fman->dts_params.clk_freq = DIV_ROUND_UP(clk_rate, 1000000); in read_dts_node()
2787 err = of_property_read_u32_array(fm_node, "fsl,qman-channel-range", in read_dts_node()
2790 dev_err(&of_dev->dev, "%s: failed to read fsl,qman-channel-range for %pOF\n", in read_dts_node()
2794 fman->dts_params.qman_channel_base = range[0]; in read_dts_node()
2795 fman->dts_params.num_of_qman_channels = range[1]; in read_dts_node()
2800 dev_err(&of_dev->dev, "%s: could not find MURAM node\n", in read_dts_node()
2806 &fman->dts_params.muram_res); in read_dts_node()
2809 dev_err(&of_dev->dev, "%s: of_address_to_resource() = %d\n", in read_dts_node()
2816 err = devm_request_irq(&of_dev->dev, irq, fman_irq, IRQF_SHARED, in read_dts_node()
2819 dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n", in read_dts_node()
2824 if (fman->dts_params.err_irq != 0) { in read_dts_node()
2825 err = devm_request_irq(&of_dev->dev, fman->dts_params.err_irq, in read_dts_node()
2827 "fman-err", fman); in read_dts_node()
2829 dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n", in read_dts_node()
2830 __func__, fman->dts_params.err_irq, err); in read_dts_node()
2835 fman->dts_params.res = in read_dts_node()
2836 devm_request_mem_region(&of_dev->dev, phys_base_addr, in read_dts_node()
2838 if (!fman->dts_params.res) { in read_dts_node()
2839 dev_err(&of_dev->dev, "%s: request_mem_region() failed\n", in read_dts_node()
2844 fman->dts_params.base_addr = in read_dts_node()
2845 devm_ioremap(&of_dev->dev, phys_base_addr, mem_size); in read_dts_node()
2846 if (!fman->dts_params.base_addr) { in read_dts_node()
2847 dev_err(&of_dev->dev, "%s: devm_ioremap() failed\n", __func__); in read_dts_node()
2851 fman->dev = &of_dev->dev; in read_dts_node()
2853 err = of_platform_populate(fm_node, NULL, NULL, &of_dev->dev); in read_dts_node()
2855 dev_err(&of_dev->dev, "%s: of_platform_populate() failed\n", in read_dts_node()
2862 of_property_read_bool(fm_node, "fsl,erratum-a050385"); in read_dts_node()
2880 dev = &of_dev->dev; in fman_probe()
2884 return -EIO; in fman_probe()
2889 return -EINVAL; in fman_probe()
2894 return -EINVAL; in fman_probe()
2897 if (fman->dts_params.err_irq == 0) { in fman_probe()
2919 dev_dbg(dev, "FMan%d probed\n", fman->dts_params.id); in fman_probe()
2934 .name = "fsl-fman",