ethernet/freescale/fec.h

32 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
38 #define FEC_R_CNTRL		0x084 /* Receive control reg */
54 #define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
55 #define FEC_R_FSTART		0x150 /* FIFO receive start reg */
56 #define FEC_R_DES_START_1	0x160 /* Receive descriptor ring 1 */
58 #define FEC_R_BUFF_SIZE_1	0x168 /* Maximum receive buff ring1 size */
59 #define FEC_R_DES_START_2	0x16c /* Receive descriptor ring 2 */
61 #define FEC_R_BUFF_SIZE_2	0x174 /* Maximum receive buff ring2 size */
62 #define FEC_R_DES_START_0	0x180 /* Receive descriptor ring */
64 #define FEC_R_BUFF_SIZE_0	0x188 /* Maximum receive buff size */
65 #define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
66 #define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
67 #define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
68 #define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
69 #define FEC_FTRL		0x1b0 /* Frame truncation receive length*/
70 #define FEC_RACC		0x1c4 /* Receive Accelerator function */
71 #define FEC_RCMR_1		0x1c8 /* Receive classification match ring 1 */
72 #define FEC_RCMR_2		0x1cc /* Receive classification match ring 2 */
138 #define IEEE_R_MACERR		0x2d8 /* Receive FIFO overflow count */
148 #define FEC_R_DES_ACTIVE_0	0x010 /* Receive descriptor reg */
156 #define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
157 #define FEC_R_FSTART		0x090 /* FIFO receive start reg */
160 #define FEC_R_CNTRL		0x104 /* Receive control reg */
167 #define FEC_R_DES_START_0	0x3d0 /* Receive descriptor ring */
173 #define FEC_R_BUFF_SIZE_0	0x3d8 /* Maximum receive buff size */
240 #define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
253 /* Buffer descriptor control/status used by Ethernet receive.
269 /* Enhanced buffer descriptor control/status used by Ethernet receive */
420  * - Two class indicators on receive with configurable priority
455  * those FIFO receive registers are resolved in other platforms.