chelsio/cxgb4vf/adapter.h

2  * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5  * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
13  *     Redistribution and use in source and binary forms, with or
17  *      - Redistributions of source code must retain the above
21  *      - Redistributions in binary form must reproduce the above
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
61 	 * MSI-X interrupt index usage.
63 	MSIX_FW		= 0,		/* MSI-X index for firmware Q */
64 	MSIX_IQFLINT	= 1,		/* MSI-X index base for Ingress Qs */
69 	 * The maximum number of Ingress and Egress Queues is determined by
71 	 * ancillary queues.  Each "Queue Set" requires one Ingress Queue
72 	 * for RX Packet Ingress Event notifications and two Egress Queues for
89  * Per-"port" information.  This is really per-Virtual Interface information
90  * but the use of the "port" nomanclature makes it easier to go back and forth
111  * queues are organized into "Queue Sets" with one ingress and one egress
113  * (Virtual Interfaces).  One extra ingress queue is used to receive
115  * use here are really "Relative Queue IDs" which are returned as part of the
116  * firmware command to allocate queues.  These queue IDs are relative to the
117  * absolute Queue ID base of the section of the Queue ID space allocated to
122  * SGE free-list queue state.
126 	unsigned int avail;		/* # of available RX buffers */
135 	 * Write-once/infrequently fields.
136 	 * -------------------------------
142 	struct rx_sw_desc *sdesc;	/* address of SW RX descriptor ring */
143 	__be64 *desc;			/* address of HW RX descriptor ring */
176 	 * Write-once/infrequently fields.
177 	 * -------------------------------
203 	unsigned long rx_cso;		/* # of Rx checksum offloads */
204 	unsigned long vlan_ex;		/* # of Rx VLAN extractions */
205 	unsigned long rx_drops;		/* # of packets dropped due to no mem */
220  * TX Descriptors.  For convenience, it also contains a pointer to a parallel
226 	 * Egress Queues are measured in units of SGE_EQ_IDXSIZE by the
233 	unsigned int in_use;		/* # of in-use TX descriptors */
241 	 * Write-once/infrequently fields.
242 	 * -------------------------------
278 	 * Extra ingress queues for asynchronous firmware events and
287 	 * State for managing "starving Free Lists" -- Free Lists which have
288 	 * fallen below a certain threshold of buffers available to the
289 	 * hardware and attempts to refill them up to that threshold have
291 	 * make periodic attempts to refill these starving Free Lists ...
302 	 * Write-once/infrequently fields.
303 	 * -------------------------------
308 	u16 ethtxq_rover;		/* Tx queue to clean up next */
310 	u8 counter_val[SGE_NCOUNTERS];	/* interrupt RX threshold array */
321 	 * Reverse maps from Absolute Queue IDs to associated queue pointers.
325 	 * subtracting off the Base Queue ID and then use a Relative Queue ID
326 	 * indexed table to get the pointer to the corresponding software
336  * Utility macros to convert Absolute- to Relative-Queue indices and Egress-
337  * and Ingress-Queues.  The EQ_MAP() and IQ_MAP() macros which provide
338  * pointers to Ingress- and Egress-Queues can be used as both L- and R-values
340 #define EQ_IDX(s, abs_id) ((unsigned int)((abs_id) - (s)->egr_base))
341 #define IQ_IDX(s, abs_id) ((unsigned int)((abs_id) - (s)->ingr_base))
343 #define EQ_MAP(s, abs_id) ((s)->egr_map[EQ_IDX(s, abs_id)])
344 #define IQ_MAP(s, abs_id) ((s)->ingr_map[IQ_IDX(s, abs_id)])
347  * Macro to iterate across Queue Sets ("rxq" is a historic misnomer).
350 	for (iter = 0; iter < (sge)->ethqsets; iter++)
363  * Per-"adapter" (Virtual Function) information.
423  * t4_read_reg - read a HW register
427  * Returns the 32-bit value of the given HW register.
431 	return readl(adapter->regs + reg_addr);  in t4_read_reg()
435  * t4_write_reg - write a HW register
438  * @val: the value to write
440  * Write a 32-bit value into the given HW register.
444 	writel(val, adapter->regs + reg_addr);  in t4_write_reg()
461  * t4_read_reg64 - read a 64-bit HW register
465  * Returns the 64-bit value of the given HW register.
469 	return readq(adapter->regs + reg_addr);  in t4_read_reg64()
473  * t4_write_reg64 - write a 64-bit HW register
476  * @val: the value to write
478  * Write a 64-bit value into the given HW register.
483 	writeq(val, adapter->regs + reg_addr);  in t4_write_reg64()
487  * port_name - return the string name of a port
495 	return adapter->port[pidx]->name;  in port_name()
499  * t4_os_set_hw_addr - store a port's MAC address in SW
510 	memcpy(adapter->port[pidx]->dev_addr, hw_addr, ETH_ALEN);  in t4_os_set_hw_addr()
514  * netdev2pinfo - return the port_info structure associated with a net_device
525  * adap2pinfo - return the port_info of a port
533 	return netdev_priv(adapter->port[pidx]);  in adap2pinfo()
537  * netdev2adap - return the adapter structure associated with a net_device
544 	return netdev2pinfo(dev)->adapter;  in netdev2adap()
549  * is "contracted" to provide for the common code.