Lines Matching full:enum
83 enum {
92 enum {
97 enum {
106 enum {
118 enum dev_master {
124 enum dev_state {
130 enum cc_pause {
136 enum cc_fec {
142 enum {
149 enum cxgb4_netdev_tls_ops {
196 enum {
445 enum pcie_memwin drv_memwin;
466 enum chip_type chip; /* chip code */
574 enum fw_caps {
589 enum cc_pause requested_fc; /* flow control user has requested */
590 enum cc_pause fc; /* actual link flow control */
591 enum cc_pause advertised_fc; /* actual advertised flow control */
593 enum cc_fec requested_fec; /* Forward Error Correction: */
594 enum cc_fec fec; /* requested and actual in use */
607 enum {
613 enum {
624 enum {
631 enum {
637 enum {
661 enum fw_port_type port_type;
705 enum { /* adapter flags */
720 enum {
918 enum cxgb4_uld uld_type;
921 enum sge_eosw_state {
932 enum sge_eosw_state state; /* Current ETHOFLD State */
1067 enum {
1119 enum chip_type chip;
1264 enum {
1268 enum {
1273 enum {
1278 enum {
1282 enum {
1428 enum {
1434 enum {
1441 enum {
1649 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1855 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1872 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1876 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1879 enum t4_bar2_qtype qtype,
1934 const char *t4_get_port_type_description(enum fw_port_type port_type);
1971 enum dev_master master, enum dev_state *state);
2075 enum ctxt_type ctype, u32 *data);
2077 enum ctxt_type ctype, u32 *data);