Lines Matching defs:adapter_params
438 struct adapter_params { struct
439 struct sge_params sge;
440 struct tp_params tp;
441 struct vpd_params vpd;
442 struct pf_resources pfres;
443 struct pci_params pci;
444 struct devlog_params devlog;
445 enum pcie_memwin drv_memwin;
447 unsigned int cim_la_size;
449 unsigned int sf_size; /* serial flash size in bytes */
450 unsigned int sf_nsec; /* # of flash sectors */
452 unsigned int fw_vers; /* firmware version */
453 unsigned int bs_vers; /* bootstrap version */
454 unsigned int tp_vers; /* TP microcode version */
455 unsigned int er_vers; /* expansion ROM version */
456 unsigned int scfg_vers; /* Serial Configuration version */
457 unsigned int vpd_vers; /* VPD Version */
458 u8 api_vers[7];
460 unsigned short mtus[NMTUS];
461 unsigned short a_wnd[NCCTRL_WIN];
462 unsigned short b_wnd[NCCTRL_WIN];
464 unsigned char nports; /* # of ethernet ports */
465 unsigned char portvec;
466 enum chip_type chip; /* chip code */
467 struct arch_specific_params arch; /* chip specific params */
468 unsigned char offload;
469 unsigned char crypto; /* HW capability for crypto */
470 unsigned char ethofld; /* QoS support */
472 unsigned char bypass;
473 unsigned char hash_filter;
475 unsigned int ofldq_wr_cred;
476 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
478 unsigned int nsched_cls; /* number of traffic classes */
479 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
480 unsigned int max_ird_adapter; /* Max read depth per adapter */
481 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
482 u8 fw_caps_support; /* 32-bit Port Capabilities */
483 bool filter2_wr_support; /* FW support for FILTER2_WR */
484 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
489 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
490 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
491 bool write_cmpl_support; /* FW supports WRITE_CMPL */