Lines Matching +full:0 +full:x27200
211 #define OCTNIC_NCMD_AUTONEG_ON 0x1
212 #define OCTNIC_NCMD_PHY_ON 0x2
269 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
281 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
390 return 0; in lio_get_link_ksettings()
424 return 0; in lio_set_link_ksettings()
431 return 0; in lio_set_link_ksettings()
443 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo)); in lio_get_drvinfo()
459 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo)); in lio_get_vf_drvinfo()
472 int ret = 0; in lio_send_queue_count_update()
474 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in lio_send_queue_count_update()
476 nctrl.ncmd.u64 = 0; in lio_send_queue_count_update()
480 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in lio_send_queue_count_update()
486 dev_err(&oct->pci_dev->dev, "Failed to send Queue reset command (ret: 0x%x)\n", in lio_send_queue_count_update()
491 return 0; in lio_send_queue_count_update()
500 u32 max_rx = 0, max_tx = 0, tx_count = 0, rx_count = 0; in lio_ethtool_get_channels()
501 u32 combined_count = 0, max_combined = 0; in lio_ethtool_get_channels()
521 u64 reg_val = 0ULL; in lio_ethtool_get_channels()
522 u64 ctrl = CN23XX_VF_SLI_IQ_PKT_CONTROL64(0); in lio_ethtool_get_channels()
542 int num_msix_irqs = 0; in lio_irq_reallocate_irqs()
546 return 0; in lio_irq_reallocate_irqs()
560 for (i = 0; i < num_msix_irqs; i++) { in lio_irq_reallocate_irqs()
567 oct->ioq_vector[i].vector = 0; in lio_irq_reallocate_irqs()
596 return 0; in lio_irq_reallocate_irqs()
606 int stopped = 0; in lio_ethtool_set_channels()
608 if (strcmp(oct->fw_info.liquidio_firmware_version, "1.6.1") < 0) { in lio_ethtool_set_channels()
631 u64 reg_val = 0ULL; in lio_ethtool_set_channels()
632 u64 ctrl = CN23XX_VF_SLI_IQ_PKT_CONTROL64(0); in lio_ethtool_set_channels()
645 return 0; in lio_ethtool_set_channels()
662 return 0; in lio_ethtool_set_channels()
699 return 0; in lio_get_eeprom()
707 int ret = 0; in octnet_gpio_access()
709 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in octnet_gpio_access()
711 nctrl.ncmd.u64 = 0; in octnet_gpio_access()
715 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_gpio_access()
726 return 0; in octnet_gpio_access()
734 int ret = 0; in octnet_id_active()
736 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in octnet_id_active()
738 nctrl.ncmd.u64 = 0; in octnet_id_active()
741 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_id_active()
752 return 0; in octnet_id_active()
765 int retval = 0; in octnet_mdio45_access()
770 sizeof(struct oct_mdio_cmd_resp), 0); in octnet_mdio45_access()
784 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_mdio45_access()
787 0, 0, 0); in octnet_mdio45_access()
803 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_mdio45_access()
850 ret = octnet_mdio45_access(lio, 0, in lio_set_phys_id()
856 ret = octnet_mdio45_access(lio, 0, in lio_set_phys_id()
882 return 0; in lio_set_phys_id()
934 return 0; in lio_set_phys_id()
944 return 0; in lio_set_phys_id()
953 u32 tx_max_pending = 0, rx_max_pending = 0, tx_pending = 0, in lio_ethtool_get_ringparam()
954 rx_pending = 0; in lio_ethtool_get_ringparam()
969 rx_pending = oct->droq[0]->max_count; in lio_ethtool_get_ringparam()
970 tx_pending = oct->instr_queue[0]->max_count; in lio_ethtool_get_ringparam()
977 ering->rx_mini_pending = 0; in lio_ethtool_get_ringparam()
978 ering->rx_jumbo_pending = 0; in lio_ethtool_get_ringparam()
979 ering->rx_mini_max_pending = 0; in lio_ethtool_get_ringparam()
980 ering->rx_jumbo_max_pending = 0; in lio_ethtool_get_ringparam()
999 resp_size, 0); in lio_23xx_reconfigure_queue_count()
1015 if_cfg.u64 = 0; in lio_23xx_reconfigure_queue_count()
1021 sc->iq_no = 0; in lio_23xx_reconfigure_queue_count()
1023 OPCODE_NIC_QCOUNT_UPDATE, 0, in lio_23xx_reconfigure_queue_count()
1024 if_cfg.u64, 0); in lio_23xx_reconfigure_queue_count()
1038 retval = wait_for_sc_completion_timeout(oct, sc, 0); in lio_23xx_reconfigure_queue_count()
1056 for (j = 0; j < lio->linfo.num_rxpciq; j++) { in lio_23xx_reconfigure_queue_count()
1061 for (j = 0; j < lio->linfo.num_txpciq; j++) { in lio_23xx_reconfigure_queue_count()
1069 lio->txq = lio->linfo.txpciq[0].s.q_no; in lio_23xx_reconfigure_queue_count()
1070 lio->rxq = lio->linfo.rxpciq[0].s.q_no; in lio_23xx_reconfigure_queue_count()
1077 return 0; in lio_23xx_reconfigure_queue_count()
1084 int i, queue_count_update = 0; in lio_reset_queues()
1148 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { in lio_reset_queues()
1154 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { in lio_reset_queues()
1212 for (i = 0; i < oct->num_oqs; i++) in lio_reset_queues()
1227 if (liquidio_setup_io_queues(oct, 0, num_qs, num_qs)) { in lio_reset_queues()
1251 return 0; in lio_reset_queues()
1260 int stopped = 0; in lio_ethtool_set_ringparam()
1273 rx_count_old = oct->droq[0]->max_count; in lio_ethtool_set_ringparam()
1274 tx_count_old = oct->instr_queue[0]->max_count; in lio_ethtool_set_ringparam()
1277 return 0; in lio_ethtool_set_ringparam()
1302 return 0; in lio_ethtool_set_ringparam()
1328 OCTNET_CMD_VERBOSE_ENABLE, 0); in lio_set_msglevel()
1331 OCTNET_CMD_VERBOSE_DISABLE, 0); in lio_set_msglevel()
1353 pause->autoneg = 0; in lio_get_pauseparam()
1370 int ret = 0; in lio_set_pauseparam()
1375 if (linfo->link.s.duplex == 0) { in lio_set_pauseparam()
1385 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in lio_set_pauseparam()
1387 nctrl.ncmd.u64 = 0; in lio_set_pauseparam()
1389 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in lio_set_pauseparam()
1398 nctrl.ncmd.s.param1 = 0; in lio_set_pauseparam()
1406 nctrl.ncmd.s.param2 = 0; in lio_set_pauseparam()
1419 return 0; in lio_set_pauseparam()
1430 int i = 0, j; in lio_get_ethtool_stats()
1631 for (j = 0; j < MAX_OCTEON_INSTR_QUEUES(oct_dev); j++) { in lio_get_ethtool_stats()
1674 for (j = 0; j < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); j++) { in lio_get_ethtool_stats()
1719 int i = 0, j, vj; in lio_vf_get_ethtool_stats()
1753 for (vj = 0; vj < oct_dev->num_iqs; vj++) { in lio_vf_get_ethtool_stats()
1795 for (vj = 0; vj < oct_dev->num_oqs; vj++) { in lio_vf_get_ethtool_stats()
1832 for (i = 0; i < ARRAY_SIZE(oct_priv_flags_strings); i++) { in lio_get_priv_flags_strings()
1856 for (j = 0; j < num_stats; j++) { in lio_get_strings()
1862 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) { in lio_get_strings()
1865 for (j = 0; j < num_iq_stats; j++) { in lio_get_strings()
1873 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) { in lio_get_strings()
1876 for (j = 0; j < num_oq_stats; j++) { in lio_get_strings()
1904 for (j = 0; j < num_stats; j++) { in lio_vf_get_strings()
1910 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) { in lio_vf_get_strings()
1913 for (j = 0; j < num_iq_stats; j++) { in lio_vf_get_strings()
1921 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) { in lio_vf_get_strings()
1924 for (j = 0; j < num_oq_stats; j++) { in lio_vf_get_strings()
2004 0, in octnet_get_intrmod_cfg()
2005 sizeof(struct oct_intrmod_resp), 0); in octnet_get_intrmod_cfg()
2011 memset(resp, 0, sizeof(struct oct_intrmod_resp)); in octnet_get_intrmod_cfg()
2013 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_get_intrmod_cfg()
2016 OPCODE_NIC_INTRMOD_PARAMS, 0, 0, 0); in octnet_get_intrmod_cfg()
2030 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_get_intrmod_cfg()
2046 return 0; in octnet_get_intrmod_cfg()
2062 16, 0); in octnet_set_intrmod_cfg()
2072 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_set_intrmod_cfg()
2075 OPCODE_NIC_INTRMOD_CFG, 0, 0, 0); in octnet_set_intrmod_cfg()
2089 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_set_intrmod_cfg()
2094 if (retval == 0) { in octnet_set_intrmod_cfg()
2100 return 0; in octnet_set_intrmod_cfg()
2144 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no]; in lio_get_intr_coalesce()
2179 return 0; in lio_get_intr_coalesce()
2187 int ret = 0; in oct_cfg_adaptive_intr()
2249 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2255 (0x3fffff00000000UL)) | in oct_cfg_rx_intrcnt()
2271 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2276 (0x3fffff00000000UL)) | in oct_cfg_rx_intrcnt()
2287 return 0; in oct_cfg_rx_intrcnt()
2327 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2350 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2365 return 0; in oct_cfg_rx_intrtime()
2393 for (q_no = 0; q_no < oct->num_iqs; q_no++) { in oct_cfg_tx_intrcnt()
2397 val = (val & 0xFFFF000000000000ULL) | in oct_cfg_tx_intrcnt()
2410 return 0; in oct_cfg_tx_intrcnt()
2419 struct oct_intrmod_cfg intrmod = {0}; in lio_set_intr_coalesce()
2430 for (j = 0; j < lio->linfo.num_txpciq; j++) { in lio_set_intr_coalesce()
2450 intrmod.rx_enable = intr_coal->use_adaptive_rx_coalesce ? 1 : 0; in lio_set_intr_coalesce()
2451 intrmod.tx_enable = intr_coal->use_adaptive_tx_coalesce ? 1 : 0; in lio_set_intr_coalesce()
2482 return 0; in lio_set_intr_coalesce()
2516 return 0; in lio_get_ts_info()
2539 int len = 0; in cn23xx_read_csr_reg()
2546 /*0x29030 or 0x29040*/ in cn23xx_read_csr_reg()
2553 /*0x27080 or 0x27090*/ in cn23xx_read_csr_reg()
2560 /*0x27000 or 0x27010*/ in cn23xx_read_csr_reg()
2567 /*0x29120*/ in cn23xx_read_csr_reg()
2568 reg = 0x29120; in cn23xx_read_csr_reg()
2572 /*0x27300*/ in cn23xx_read_csr_reg()
2573 reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2579 /*0x27200*/ in cn23xx_read_csr_reg()
2580 reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2592 /*0x29140*/ in cn23xx_read_csr_reg()
2597 /*0x29160*/ in cn23xx_read_csr_reg()
2598 reg = 0x29160; in cn23xx_read_csr_reg()
2602 /*0x29180*/ in cn23xx_read_csr_reg()
2607 /*0x291E0*/ in cn23xx_read_csr_reg()
2612 /*0x29210*/ in cn23xx_read_csr_reg()
2618 /*0x29220*/ in cn23xx_read_csr_reg()
2619 reg = 0x29220; in cn23xx_read_csr_reg()
2624 if (pf_num == 0) { in cn23xx_read_csr_reg()
2625 /*0x29260*/ in cn23xx_read_csr_reg()
2631 /*0x29270*/ in cn23xx_read_csr_reg()
2638 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2645 /*0x10040*/ in cn23xx_read_csr_reg()
2646 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2653 /*0x10080*/ in cn23xx_read_csr_reg()
2654 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2661 /*0x10090*/ in cn23xx_read_csr_reg()
2662 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2669 /*0x10050*/ in cn23xx_read_csr_reg()
2670 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2678 /*0x10070*/ in cn23xx_read_csr_reg()
2679 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2686 /*0x100a0*/ in cn23xx_read_csr_reg()
2687 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2694 /*0x100b0*/ in cn23xx_read_csr_reg()
2695 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2701 /*0x100c0*/ in cn23xx_read_csr_reg()
2702 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2703 reg = 0x100c0 + i * CN23XX_OQ_OFFSET; in cn23xx_read_csr_reg()
2708 /*0x10000*/ in cn23xx_read_csr_reg()
2709 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2717 /*0x10010*/ in cn23xx_read_csr_reg()
2718 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2726 /*0x10020*/ in cn23xx_read_csr_reg()
2727 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2735 /*0x10030*/ in cn23xx_read_csr_reg()
2736 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2744 /*0x10040*/ in cn23xx_read_csr_reg()
2745 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) in cn23xx_read_csr_reg()
2757 int len = 0; in cn23xx_vf_read_csr_reg()
2765 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2772 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2779 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2786 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2793 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2800 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2807 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2814 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2820 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2821 reg = 0x100c0 + i * CN23XX_VF_OQ_OFFSET; in cn23xx_vf_read_csr_reg()
2827 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2828 reg = 0x100d0 + i * CN23XX_VF_IQ_OFFSET; in cn23xx_vf_read_csr_reg()
2834 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2841 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2848 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2855 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2862 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2875 int i, len = 0; in cn6xxx_read_csr_reg()
2903 len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 0): %08x\n", in cn6xxx_read_csr_reg()
2913 for (i = 0; i < oct->num_oqs; i++) { in cn6xxx_read_csr_reg()
2929 for (i = 0; i <= 3; i++) { in cn6xxx_read_csr_reg()
2943 CN6XXX_DMA_CNT(0), in cn6xxx_read_csr_reg()
2944 octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); in cn6xxx_read_csr_reg()
2945 reg = CN6XXX_DMA_PKT_INT_LEVEL(0); in cn6xxx_read_csr_reg()
2947 CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2948 reg = CN6XXX_DMA_TIME_INT_LEVEL(0); in cn6xxx_read_csr_reg()
2950 CN6XXX_DMA_TIME_INT_LEVEL(0), in cn6xxx_read_csr_reg()
2969 for (i = 0; i < 16; i++) { in cn6xxx_read_csr_reg()
2981 int i, len = 0; in cn6xxx_read_config_reg()
2988 for (i = 0; i <= 13; i++) { in cn6xxx_read_config_reg()
2990 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n", in cn6xxx_read_config_reg()
2996 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n", in cn6xxx_read_config_reg()
3008 int len = 0; in lio_get_regs()
3015 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX); in lio_get_regs()
3019 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX_VF); in lio_get_regs()
3024 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN); in lio_get_regs()
3044 bool intr_by_tx_bytes = !!(flags & (0x1 << OCT_PRIV_FLAG_TX_BYTES)); in lio_set_priv_flags()
3048 return 0; in lio_set_priv_flags()
3063 return 0; in lio_get_fecparam()
3073 return 0; in lio_get_fecparam()
3088 liquidio_set_fec(lio, 0); in lio_set_fecparam()
3097 return 0; in lio_set_fecparam()