broadcom/bnxt/bnxt.h

1 /* Broadcom NetXtreme-C/E network driver.
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2018 Broadcom Limited
186 	((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
191 	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
255 	    (((rxcmp1)->rx_cmp_flags2 &	RX_CMP_L4_CS_BITS) &&		\
256 	     !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
259 	    ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &			\
263 	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\
280 	((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &		\
317 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
321 	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
326 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
330 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
334 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
364 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
368 	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &		\
372 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
413 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
417 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
421 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
425 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
429 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
437 	((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &			\
441 	(!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &			\
470 	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &			\
474 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
479 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
521 /* 64-bit doorbell */
543 #define INVALID_HW_RING_ID	((u16)-1)
560 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
571 	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\
581 #define MAX_TPA_P5_MASK	(MAX_TPA_P5 - 1)
610 #define BNXT_MAX_RX_DESC_CNT		(RX_DESC_CNT * MAX_RX_PAGES - 1)
611 #define BNXT_MAX_RX_JUM_DESC_CNT	(RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
612 #define BNXT_MAX_TX_DESC_CNT		(TX_DESC_CNT * MAX_TX_PAGES - 1)
614 #define RX_RING(x)	(((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
615 #define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))
617 #define TX_RING(x)	(((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
618 #define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))
620 #define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
621 #define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))
624 	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\
625 	 !((raw_cons) & bp->cp_bit))
628 	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
629 	 !((raw_cons) & bp->cp_bit))
632 	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\
633 	 !((raw_cons) & bp->cp_bit))
636 	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
639 	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
642 	(le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
644 #define NEXT_RX(idx)		(((idx) + 1) & bp->rx_ring_mask)
646 #define NEXT_RX_AGG(idx)	(((idx) + 1) & bp->rx_agg_ring_mask)
648 #define NEXT_TX(idx)		(((idx) + 1) & bp->tx_ring_mask)
652 #define RING_CMP(idx)		((idx) & bp->cp_ring_mask)
655 #define BNXT_HWRM_MAX_REQ_LEN		(bp->hwrm_max_req_len)
659 #define HWRM_CMD_TIMEOUT		(bp->hwrm_cmd_timeout)
675 	 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
1002 #define INVALID_STATS_CTX_ID	-1
1217 	u32			preemphasis;  member
1280 	((link_info)->support_pam4_speeds)
1339 	((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1399 	/* Stat counter mask (width) */
1666 #define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))
1667 #define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)
1668 #define BNXT_NPAR(bp)		((bp)->port_partition_type)
1669 #define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)
1672 				  ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG)) && \
1673 				 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1674 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1675 #define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1677 				 (!((bp)->flags & BNXT_FLAG_CHIP_P5) ||	\
1678 				  (bp)->max_tpa_v2) && !is_kdump_kernel())
1681 	((bp)->chip_num == CHIP_NUM_58818)
1684 	((bp)->chip_num == CHIP_NUM_57508 ||	\
1685 	 (bp)->chip_num == CHIP_NUM_57504 ||	\
1686 	 (bp)->chip_num == CHIP_NUM_57502)
1694 	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\
1695 	 BNXT_CHIP_NUM_5745X((bp)->chip_num) ||	\
1696 	 BNXT_CHIP_NUM_588XX((bp)->chip_num) ||	\
1697 	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\
1787 	(test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||	\
1788 	 pci_channel_offline((bp)->pdev))
1828 #define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1857 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1864 #define BNXT_FW_MAJ(bp)		((bp)->fw_ver_code >> 48)
1928 	/* lock to protect VF-rep creation/cleanup via
1929 	 * multiple paths such as ->sriov_configure() and
1930 	 * devlink ->eswitch_mode_set()
1936 	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1943 #define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)
1973 	/* devlink interface and vf-rep structs */
1977 	struct bnxt_vf_rep	**vf_reps; /* array of vf-rep ptrs */
1978 	u16			*cfa_code_map; /* cfa_code -> vf_idx map */
2047 	return bp->tx_ring_size -  in bnxt_tx_avail()
2048 		((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);  in bnxt_tx_avail()
2054 	spin_lock(&bp->db_lock);		\
2057 	spin_unlock(&bp->db_lock);		\
2067 	if (bp->flags & BNXT_FLAG_CHIP_P5) {  in bnxt_db_write_relaxed()
2068 		writeq_relaxed(db->db_key64 | idx, db->doorbell);  in bnxt_db_write_relaxed()
2070 		u32 db_val = db->db_key32 | idx;  in bnxt_db_write_relaxed()
2072 		writel_relaxed(db_val, db->doorbell);  in bnxt_db_write_relaxed()
2073 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)  in bnxt_db_write_relaxed()
2074 			writel_relaxed(db_val, db->doorbell);  in bnxt_db_write_relaxed()
2082 	if (bp->flags & BNXT_FLAG_CHIP_P5) {  in bnxt_db_write()
2083 		writeq(db->db_key64 | idx, db->doorbell);  in bnxt_db_write()
2085 		u32 db_val = db->db_key32 | idx;  in bnxt_db_write()
2087 		writel(db_val, db->doorbell);  in bnxt_db_write()
2088 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)  in bnxt_db_write()
2089 			writel(db_val, db->doorbell);  in bnxt_db_write()
2121 	return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&  in bnxt_kong_hwrm_message()
2122 		bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));  in bnxt_kong_hwrm_message()
2127 	return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&  in bnxt_hwrm_kong_chnl()
2128 		req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));  in bnxt_hwrm_kong_chnl()
2134 		return bp->hwrm_cmd_kong_resp_addr;  in bnxt_get_hwrm_resp_addr()
2136 		return bp->hwrm_cmd_resp_addr;  in bnxt_get_hwrm_resp_addr()
2144 		seq_id = bp->hwrm_cmd_seq++;  in bnxt_get_hwrm_seq_id()
2146 		seq_id = bp->hwrm_cmd_kong_seq++;  in bnxt_get_hwrm_seq_id()