39 #define N_TX_BUFF_ORDER	0
46 #define MACE_BUFF_SIZE	0x800
49 #define BROKEN_ADDRCHG_REV	0x0941
53 #define MACE_BASE	(void *)(0x50F1C000)
54 #define MACE_PROM	(void *)(0x50F08001)
105 	psc_write_word(PSC_ENETRD_CMD + set, 0x0100);  in mace_load_rxdma_base()
108 	psc_write_word(PSC_ENETRD_CMD + set, 0x9800);  in mace_load_rxdma_base()
109 	mp->rx_tail = 0;  in mace_load_rxdma_base()
124 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_rxdma_reset()
125 	mace_load_rxdma_base(dev, 0x00);  in mace_rxdma_reset()
126 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_rxdma_reset()
128 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_rxdma_reset()
129 	mace_load_rxdma_base(dev, 0x10);  in mace_rxdma_reset()
130 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_rxdma_reset()
133 	mp->rx_slot = 0;  in mace_rxdma_reset()
135 	psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);  in mace_rxdma_reset()
136 	psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);  in mace_rxdma_reset()
149 	psc_write_word(PSC_ENETWR_CTL, 0x8800);  in mace_txdma_reset()
154 	mp->tx_slot = mp->tx_sloti = 0;  in mace_txdma_reset()
157 	psc_write_word(PSC_ENETWR_CTL, 0x0400);  in mace_txdma_reset()
167 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_dma_off()
168 	psc_write_word(PSC_ENETRD_CTL, 0x1000);  in mace_dma_off()
169 	psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);  in mace_dma_off()
170 	psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);  in mace_dma_off()
172 	psc_write_word(PSC_ENETWR_CTL, 0x8800);  in mace_dma_off()
173 	psc_write_word(PSC_ENETWR_CTL, 0x1000);  in mace_dma_off()
174 	psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);  in mace_dma_off()
175 	psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);  in mace_dma_off()
199 	unsigned char checksum = 0;  in mace_probe()
221 	 * The PROM contains 8 bytes which total 0xFF when XOR'd  in mace_probe()
229 	for (j = 0; j < 6; ++j) {  in mace_probe()
238 	if (checksum != 0xFF) {  in mace_probe()
246 	pr_info("Onboard MACE, hardware address %pM, chip revision 0x%04X\n",  in mace_probe()
251 		return 0;  in mace_probe()
282 	mb->maccc = 0;	/* turn off tx, rx */  in mace_reset()
283 	mb->imr = 0xFF;	/* disable all intrs for now */  in mace_reset()
291 	mb->rcvfc = 0;  in mace_reset()
301 		while ((mb->iac & ADDRCHG) != 0)  in mace_reset()
304 	for (i = 0; i < 8; ++i)  in mace_reset()
305 		mb->ladrf = 0;  in mace_reset()
309 		mb->iac = 0;  in mace_reset()
330 		while ((mb->iac & ADDRCHG) != 0)  in __mace_set_address()
333 	for (i = 0; i < 6; ++i)  in __mace_set_address()
336 		mb->iac = 0;  in __mace_set_address()
356 	return 0;  in mace_set_address()
372 	if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {  in mace_open()
376 	if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {  in mace_open()
400 	psc_write_word(PSC_ENETWR_CTL, 0x9000);  in mace_open()
401 	psc_write_word(PSC_ENETRD_CTL, 0x9000);  in mace_open()
402 	psc_write_word(PSC_ENETWR_CTL, 0x0400);  in mace_open()
403 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_open()
412 	return 0;  in mace_open()
432 	mb->maccc = 0;		/* disable rx and tx	 */  in mace_close()
433 	mb->imr = 0xFF;		/* disable all irqs	 */  in mace_close()
436 	return 0;  in mace_close()
470 	psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);  in mace_xmit_start()
472 	mp->tx_slot ^= 0x10;  in mace_xmit_start()
499 			for (i = 0; i < 8; i++) {  in mace_set_multicast()
500 				multicast_filter[i] = 0xFF;  in mace_set_multicast()
503 			for (i = 0; i < 8; i++)  in mace_set_multicast()
504 				multicast_filter[i] = 0;  in mace_set_multicast()
517 			while ((mb->iac & ADDRCHG) != 0)  in mace_set_multicast()
520 		for (i = 0; i < 8; ++i)  in mace_set_multicast()
523 			mb->iac = 0;  in mace_set_multicast()
568 		if ((fs & XMTSV) == 0) {  in mace_interrupt()
612 	mb->maccc = 0;  in mace_tx_timeout()
651 		unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 );  in mace_dma_rx_frame()
683 	if (!(baka & 0x60000000)) return IRQ_NONE;  in mace_dma_intr()
691 	if (status & 0x2000) {  in mace_dma_intr()
693 	} else if (status & 0x0100) {  in mace_dma_intr()
694 		psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);  in mace_dma_intr()
712 			mp->rx_slot ^= 0x10;  in mace_dma_intr()
714 			psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);  in mace_dma_intr()
724 	if (status & 0x2000) {  in mace_dma_intr()
726 	} else if (status & 0x0100) {  in mace_dma_intr()
727 		psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);  in mace_dma_intr()
728 		mp->tx_sloti ^= 0x10;  in mace_dma_intr()
755 	return 0;  in mac_mace_device_remove()