Lines Matching +full:run +full:- +full:control
1 // SPDX-License-Identifier: GPL-2.0-only
30 static int port_aaui = -1;
115 int j, rev, rc = -EBUSY; in mace_probe()
120 return -ENODEV; in mace_probe()
123 addr = of_get_property(mace, "mac-address", NULL); in mace_probe()
125 addr = of_get_property(mace, "local-mac-address", NULL); in mace_probe()
127 printk(KERN_ERR "Can't get mac-address for MACE %pOF\n", in mace_probe()
129 return -ENODEV; in mace_probe()
134 * lazy allocate the driver-wide dummy buffer. (Note that we in mace_probe()
140 return -ENOMEM; in mace_probe()
145 return -EBUSY; in mace_probe()
150 rc = -ENOMEM; in mace_probe()
153 SET_NETDEV_DEV(dev, &mdev->ofdev.dev); in mace_probe()
156 mp->mdev = mdev; in mace_probe()
159 dev->base_addr = macio_resource_start(mdev, 0); in mace_probe()
160 mp->mace = ioremap(dev->base_addr, 0x1000); in mace_probe()
161 if (mp->mace == NULL) { in mace_probe()
163 rc = -ENOMEM; in mace_probe()
166 dev->irq = macio_irq(mdev, 0); in mace_probe()
170 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; in mace_probe()
172 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) | in mace_probe()
173 in_8(&mp->mace->chipid_lo); in mace_probe()
177 mp->maccc = ENXMT | ENRCV; in mace_probe()
179 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000); in mace_probe()
180 if (mp->tx_dma == NULL) { in mace_probe()
182 rc = -ENOMEM; in mace_probe()
185 mp->tx_dma_intr = macio_irq(mdev, 1); in mace_probe()
187 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000); in mace_probe()
188 if (mp->rx_dma == NULL) { in mace_probe()
190 rc = -ENOMEM; in mace_probe()
193 mp->rx_dma_intr = macio_irq(mdev, 2); in mace_probe()
195 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1); in mace_probe()
196 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1; in mace_probe()
198 memset((char *) mp->tx_cmds, 0, in mace_probe()
200 timer_setup(&mp->tx_timeout, mace_tx_timeout, 0); in mace_probe()
201 spin_lock_init(&mp->lock); in mace_probe()
202 mp->timeout_active = 0; in mace_probe()
205 mp->port_aaui = port_aaui; in mace_probe()
209 mp->port_aaui = 1; in mace_probe()
212 mp->port_aaui = 1; in mace_probe()
214 mp->port_aaui = 0; in mace_probe()
219 dev->netdev_ops = &mace_netdev_ops; in mace_probe()
226 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev); in mace_probe()
228 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq); in mace_probe()
231 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev); in mace_probe()
233 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr); in mace_probe()
236 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev); in mace_probe()
238 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr); in mace_probe()
249 dev->name, dev->dev_addr, in mace_probe()
250 mp->chipid >> 8, mp->chipid & 0xff); in mace_probe()
261 iounmap(mp->rx_dma); in mace_probe()
263 iounmap(mp->tx_dma); in mace_probe()
265 iounmap(mp->mace); in mace_probe()
287 free_irq(dev->irq, dev); in mace_remove()
288 free_irq(mp->tx_dma_intr, dev); in mace_remove()
289 free_irq(mp->rx_dma_intr, dev); in mace_remove()
291 iounmap(mp->rx_dma); in mace_remove()
292 iounmap(mp->tx_dma); in mace_remove()
293 iounmap(mp->mace); in mace_remove()
306 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); in dbdma_reset()
312 for (i = 200; i > 0; --i) in dbdma_reset()
313 if (le32_to_cpu(dma->control) & RUN) in dbdma_reset()
320 volatile struct mace __iomem *mb = mp->mace; in mace_reset()
323 /* soft-reset the chip */ in mace_reset()
325 while (--i) { in mace_reset()
326 out_8(&mb->biucc, SWRST); in mace_reset()
327 if (in_8(&mb->biucc) & SWRST) { in mace_reset()
338 out_8(&mb->imr, 0xff); /* disable all intrs for now */ in mace_reset()
339 i = in_8(&mb->ir); in mace_reset()
340 out_8(&mb->maccc, 0); /* turn off tx, rx */ in mace_reset()
342 out_8(&mb->biucc, XMTSP_64); in mace_reset()
343 out_8(&mb->utr, RTRD); in mace_reset()
344 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST); in mace_reset()
345 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */ in mace_reset()
346 out_8(&mb->rcvfc, 0); in mace_reset()
349 __mace_set_address(dev, dev->dev_addr); in mace_reset()
352 if (mp->chipid == BROKEN_ADDRCHG_REV) in mace_reset()
353 out_8(&mb->iac, LOGADDR); in mace_reset()
355 out_8(&mb->iac, ADDRCHG | LOGADDR); in mace_reset()
356 while ((in_8(&mb->iac) & ADDRCHG) != 0) in mace_reset()
360 out_8(&mb->ladrf, 0); in mace_reset()
363 if (mp->chipid != BROKEN_ADDRCHG_REV) in mace_reset()
364 out_8(&mb->iac, 0); in mace_reset()
366 if (mp->port_aaui) in mace_reset()
367 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO); in mace_reset()
369 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO); in mace_reset()
375 volatile struct mace __iomem *mb = mp->mace; in __mace_set_address()
380 if (mp->chipid == BROKEN_ADDRCHG_REV) in __mace_set_address()
381 out_8(&mb->iac, PHYADDR); in __mace_set_address()
383 out_8(&mb->iac, ADDRCHG | PHYADDR); in __mace_set_address()
384 while ((in_8(&mb->iac) & ADDRCHG) != 0) in __mace_set_address()
388 out_8(&mb->padr, dev->dev_addr[i] = p[i]); in __mace_set_address()
389 if (mp->chipid != BROKEN_ADDRCHG_REV) in __mace_set_address()
390 out_8(&mb->iac, 0); in __mace_set_address()
396 volatile struct mace __iomem *mb = mp->mace; in mace_set_address()
399 spin_lock_irqsave(&mp->lock, flags); in mace_set_address()
404 out_8(&mb->maccc, mp->maccc); in mace_set_address()
406 spin_unlock_irqrestore(&mp->lock, flags); in mace_set_address()
416 if (mp->rx_bufs[i] != NULL) { in mace_clean_rings()
417 dev_kfree_skb(mp->rx_bufs[i]); in mace_clean_rings()
418 mp->rx_bufs[i] = NULL; in mace_clean_rings()
421 for (i = mp->tx_empty; i != mp->tx_fill; ) { in mace_clean_rings()
422 dev_kfree_skb(mp->tx_bufs[i]); in mace_clean_rings()
431 volatile struct mace __iomem *mb = mp->mace; in mace_open()
432 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; in mace_open()
433 volatile struct dbdma_regs __iomem *td = mp->tx_dma; in mace_open()
444 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd)); in mace_open()
445 cp = mp->rx_cmds; in mace_open()
446 for (i = 0; i < N_RX_RING - 1; ++i) { in mace_open()
451 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */ in mace_open()
452 data = skb->data; in mace_open()
454 mp->rx_bufs[i] = skb; in mace_open()
455 cp->req_count = cpu_to_le16(RX_BUFLEN); in mace_open()
456 cp->command = cpu_to_le16(INPUT_LAST + INTR_ALWAYS); in mace_open()
457 cp->phy_addr = cpu_to_le32(virt_to_bus(data)); in mace_open()
458 cp->xfer_status = 0; in mace_open()
461 mp->rx_bufs[i] = NULL; in mace_open()
462 cp->command = cpu_to_le16(DBDMA_STOP); in mace_open()
463 mp->rx_fill = i; in mace_open()
464 mp->rx_empty = 0; in mace_open()
468 cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS); in mace_open()
469 cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->rx_cmds)); in mace_open()
472 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_open()
473 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds)); in mace_open()
474 out_le32(&rd->control, (RUN << 16) | RUN); in mace_open()
477 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING; in mace_open()
478 cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS); in mace_open()
479 cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->tx_cmds)); in mace_open()
482 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); in mace_open()
483 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds)); in mace_open()
484 mp->tx_fill = 0; in mace_open()
485 mp->tx_empty = 0; in mace_open()
486 mp->tx_fullup = 0; in mace_open()
487 mp->tx_active = 0; in mace_open()
488 mp->tx_bad_runt = 0; in mace_open()
491 out_8(&mb->maccc, mp->maccc); in mace_open()
493 out_8(&mb->imr, RCVINT); in mace_open()
501 volatile struct mace __iomem *mb = mp->mace; in mace_close()
502 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; in mace_close()
503 volatile struct dbdma_regs __iomem *td = mp->tx_dma; in mace_close()
506 out_8(&mb->maccc, 0); in mace_close()
507 out_8(&mb->imr, 0xff); /* disable all intrs */ in mace_close()
510 rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_close()
511 td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_close()
522 if (mp->timeout_active) in mace_set_timeout()
523 del_timer(&mp->tx_timeout); in mace_set_timeout()
524 mp->tx_timeout.expires = jiffies + TX_TIMEOUT; in mace_set_timeout()
525 add_timer(&mp->tx_timeout); in mace_set_timeout()
526 mp->timeout_active = 1; in mace_set_timeout()
532 volatile struct dbdma_regs __iomem *td = mp->tx_dma; in mace_xmit_start()
538 spin_lock_irqsave(&mp->lock, flags); in mace_xmit_start()
539 fill = mp->tx_fill; in mace_xmit_start()
543 if (next == mp->tx_empty) { in mace_xmit_start()
545 mp->tx_fullup = 1; in mace_xmit_start()
546 spin_unlock_irqrestore(&mp->lock, flags); in mace_xmit_start()
549 spin_unlock_irqrestore(&mp->lock, flags); in mace_xmit_start()
552 len = skb->len; in mace_xmit_start()
557 mp->tx_bufs[fill] = skb; in mace_xmit_start()
558 cp = mp->tx_cmds + NCMDS_TX * fill; in mace_xmit_start()
559 cp->req_count = cpu_to_le16(len); in mace_xmit_start()
560 cp->phy_addr = cpu_to_le32(virt_to_bus(skb->data)); in mace_xmit_start()
562 np = mp->tx_cmds + NCMDS_TX * next; in mace_xmit_start()
563 out_le16(&np->command, DBDMA_STOP); in mace_xmit_start()
566 spin_lock_irqsave(&mp->lock, flags); in mace_xmit_start()
567 mp->tx_fill = next; in mace_xmit_start()
568 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) { in mace_xmit_start()
569 out_le16(&cp->xfer_status, 0); in mace_xmit_start()
570 out_le16(&cp->command, OUTPUT_LAST); in mace_xmit_start()
571 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); in mace_xmit_start()
572 ++mp->tx_active; in mace_xmit_start()
577 if (next == mp->tx_empty) in mace_xmit_start()
579 spin_unlock_irqrestore(&mp->lock, flags); in mace_xmit_start()
587 volatile struct mace __iomem *mb = mp->mace; in mace_set_multicast()
592 spin_lock_irqsave(&mp->lock, flags); in mace_set_multicast()
593 mp->maccc &= ~PROM; in mace_set_multicast()
594 if (dev->flags & IFF_PROMISC) { in mace_set_multicast()
595 mp->maccc |= PROM; in mace_set_multicast()
600 if (dev->flags & IFF_ALLMULTI) { in mace_set_multicast()
607 crc = ether_crc_le(6, ha->addr); in mace_set_multicast()
619 if (mp->chipid == BROKEN_ADDRCHG_REV) in mace_set_multicast()
620 out_8(&mb->iac, LOGADDR); in mace_set_multicast()
622 out_8(&mb->iac, ADDRCHG | LOGADDR); in mace_set_multicast()
623 while ((in_8(&mb->iac) & ADDRCHG) != 0) in mace_set_multicast()
627 out_8(&mb->ladrf, multicast_filter[i]); in mace_set_multicast()
628 if (mp->chipid != BROKEN_ADDRCHG_REV) in mace_set_multicast()
629 out_8(&mb->iac, 0); in mace_set_multicast()
632 out_8(&mb->maccc, mp->maccc); in mace_set_multicast()
633 spin_unlock_irqrestore(&mp->lock, flags); in mace_set_multicast()
638 volatile struct mace __iomem *mb = mp->mace; in mace_handle_misc_intrs()
642 dev->stats.rx_missed_errors += 256; in mace_handle_misc_intrs()
643 dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */ in mace_handle_misc_intrs()
645 dev->stats.rx_length_errors += 256; in mace_handle_misc_intrs()
646 dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */ in mace_handle_misc_intrs()
648 ++dev->stats.tx_heartbeat_errors; in mace_handle_misc_intrs()
661 volatile struct mace __iomem *mb = mp->mace; in mace_interrupt()
662 volatile struct dbdma_regs __iomem *td = mp->tx_dma; in mace_interrupt()
669 spin_lock_irqsave(&mp->lock, flags); in mace_interrupt()
670 intr = in_8(&mb->ir); /* read interrupt register */ in mace_interrupt()
671 in_8(&mb->xmtrc); /* get retries */ in mace_interrupt()
674 i = mp->tx_empty; in mace_interrupt()
675 while (in_8(&mb->pr) & XMTSV) { in mace_interrupt()
676 del_timer(&mp->tx_timeout); in mace_interrupt()
677 mp->timeout_active = 0; in mace_interrupt()
683 intr = in_8(&mb->ir); in mace_interrupt()
686 if (mp->tx_bad_runt) { in mace_interrupt()
687 fs = in_8(&mb->xmtfs); in mace_interrupt()
688 mp->tx_bad_runt = 0; in mace_interrupt()
689 out_8(&mb->xmtfc, AUTO_PAD_XMIT); in mace_interrupt()
692 dstat = le32_to_cpu(td->status); in mace_interrupt()
694 out_le32(&td->control, RUN << 16); in mace_interrupt()
699 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; in mace_interrupt()
708 * help. So we disable auto-padding and FCS transmission in mace_interrupt()
712 out_8(&mb->xmtfc, DXMTFCS); in mace_interrupt()
714 fs = in_8(&mb->xmtfs); in mace_interrupt()
724 cp = mp->tx_cmds + NCMDS_TX * i; in mace_interrupt()
725 stat = le16_to_cpu(cp->xfer_status); in mace_interrupt()
732 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; in mace_interrupt()
734 /* there were two bytes with an end-of-packet indication */ in mace_interrupt()
735 mp->tx_bad_runt = 1; in mace_interrupt()
740 * didn't have an end-of-packet indication. in mace_interrupt()
744 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT); in mace_interrupt()
745 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU); in mace_interrupt()
747 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT); in mace_interrupt()
748 out_8(&mb->xmtfc, AUTO_PAD_XMIT); in mace_interrupt()
752 if (i == mp->tx_fill) { in mace_interrupt()
759 ++dev->stats.tx_errors; in mace_interrupt()
761 ++dev->stats.tx_carrier_errors; in mace_interrupt()
763 ++dev->stats.tx_aborted_errors; in mace_interrupt()
765 dev->stats.tx_bytes += mp->tx_bufs[i]->len; in mace_interrupt()
766 ++dev->stats.tx_packets; in mace_interrupt()
768 dev_consume_skb_irq(mp->tx_bufs[i]); in mace_interrupt()
769 --mp->tx_active; in mace_interrupt()
778 if (i != mp->tx_empty) { in mace_interrupt()
779 mp->tx_fullup = 0; in mace_interrupt()
782 mp->tx_empty = i; in mace_interrupt()
783 i += mp->tx_active; in mace_interrupt()
785 i -= N_TX_RING; in mace_interrupt()
786 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) { in mace_interrupt()
789 cp = mp->tx_cmds + NCMDS_TX * i; in mace_interrupt()
790 out_le16(&cp->xfer_status, 0); in mace_interrupt()
791 out_le16(&cp->command, OUTPUT_LAST); in mace_interrupt()
792 ++mp->tx_active; in mace_interrupt()
795 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE); in mace_interrupt()
796 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); in mace_interrupt()
799 spin_unlock_irqrestore(&mp->lock, flags); in mace_interrupt()
806 struct net_device *dev = macio_get_drvdata(mp->mdev); in mace_tx_timeout()
807 volatile struct mace __iomem *mb = mp->mace; in mace_tx_timeout()
808 volatile struct dbdma_regs __iomem *td = mp->tx_dma; in mace_tx_timeout()
809 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; in mace_tx_timeout()
814 spin_lock_irqsave(&mp->lock, flags); in mace_tx_timeout()
815 mp->timeout_active = 0; in mace_tx_timeout()
816 if (mp->tx_active == 0 && !mp->tx_bad_runt) in mace_tx_timeout()
820 mace_handle_misc_intrs(mp, in_8(&mb->ir), dev); in mace_tx_timeout()
822 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty; in mace_tx_timeout()
825 out_8(&mb->maccc, 0); in mace_tx_timeout()
826 printk(KERN_ERR "mace: transmit timeout - resetting\n"); in mace_tx_timeout()
831 cp = bus_to_virt(le32_to_cpu(rd->cmdptr)); in mace_tx_timeout()
833 out_le16(&cp->xfer_status, 0); in mace_tx_timeout()
834 out_le32(&rd->cmdptr, virt_to_bus(cp)); in mace_tx_timeout()
835 out_le32(&rd->control, (RUN << 16) | RUN); in mace_tx_timeout()
838 i = mp->tx_empty; in mace_tx_timeout()
839 mp->tx_active = 0; in mace_tx_timeout()
840 ++dev->stats.tx_errors; in mace_tx_timeout()
841 if (mp->tx_bad_runt) { in mace_tx_timeout()
842 mp->tx_bad_runt = 0; in mace_tx_timeout()
843 } else if (i != mp->tx_fill) { in mace_tx_timeout()
844 dev_kfree_skb(mp->tx_bufs[i]); in mace_tx_timeout()
847 mp->tx_empty = i; in mace_tx_timeout()
849 mp->tx_fullup = 0; in mace_tx_timeout()
851 if (i != mp->tx_fill) { in mace_tx_timeout()
852 cp = mp->tx_cmds + NCMDS_TX * i; in mace_tx_timeout()
853 out_le16(&cp->xfer_status, 0); in mace_tx_timeout()
854 out_le16(&cp->command, OUTPUT_LAST); in mace_tx_timeout()
855 out_le32(&td->cmdptr, virt_to_bus(cp)); in mace_tx_timeout()
856 out_le32(&td->control, (RUN << 16) | RUN); in mace_tx_timeout()
857 ++mp->tx_active; in mace_tx_timeout()
862 out_8(&mb->imr, RCVINT); in mace_tx_timeout()
863 out_8(&mb->maccc, mp->maccc); in mace_tx_timeout()
866 spin_unlock_irqrestore(&mp->lock, flags); in mace_tx_timeout()
878 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; in mace_rxdma_intr()
887 spin_lock_irqsave(&mp->lock, flags); in mace_rxdma_intr()
888 for (i = mp->rx_empty; i != mp->rx_fill; ) { in mace_rxdma_intr()
889 cp = mp->rx_cmds + i; in mace_rxdma_intr()
890 stat = le16_to_cpu(cp->xfer_status); in mace_rxdma_intr()
895 np = mp->rx_cmds + next; in mace_rxdma_intr()
896 if (next != mp->rx_fill && in mace_rxdma_intr()
897 (le16_to_cpu(np->xfer_status) & ACTIVE) != 0) { in mace_rxdma_intr()
903 nb = le16_to_cpu(cp->req_count) - le16_to_cpu(cp->res_count); in mace_rxdma_intr()
904 out_le16(&cp->command, DBDMA_STOP); in mace_rxdma_intr()
906 skb = mp->rx_bufs[i]; in mace_rxdma_intr()
908 ++dev->stats.rx_dropped; in mace_rxdma_intr()
910 data = skb->data; in mace_rxdma_intr()
911 frame_status = (data[nb-3] << 8) + data[nb-4]; in mace_rxdma_intr()
913 ++dev->stats.rx_errors; in mace_rxdma_intr()
915 ++dev->stats.rx_over_errors; in mace_rxdma_intr()
917 ++dev->stats.rx_frame_errors; in mace_rxdma_intr()
919 ++dev->stats.rx_crc_errors; in mace_rxdma_intr()
926 nb -= 4; in mace_rxdma_intr()
928 nb -= 8; in mace_rxdma_intr()
930 skb->protocol = eth_type_trans(skb, dev); in mace_rxdma_intr()
931 dev->stats.rx_bytes += skb->len; in mace_rxdma_intr()
933 mp->rx_bufs[i] = NULL; in mace_rxdma_intr()
934 ++dev->stats.rx_packets; in mace_rxdma_intr()
937 ++dev->stats.rx_errors; in mace_rxdma_intr()
938 ++dev->stats.rx_length_errors; in mace_rxdma_intr()
945 mp->rx_empty = i; in mace_rxdma_intr()
947 i = mp->rx_fill; in mace_rxdma_intr()
952 if (next == mp->rx_empty) in mace_rxdma_intr()
954 cp = mp->rx_cmds + i; in mace_rxdma_intr()
955 skb = mp->rx_bufs[i]; in mace_rxdma_intr()
960 mp->rx_bufs[i] = skb; in mace_rxdma_intr()
963 cp->req_count = cpu_to_le16(RX_BUFLEN); in mace_rxdma_intr()
964 data = skb? skb->data: dummy_buf; in mace_rxdma_intr()
965 cp->phy_addr = cpu_to_le32(virt_to_bus(data)); in mace_rxdma_intr()
966 out_le16(&cp->xfer_status, 0); in mace_rxdma_intr()
967 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); in mace_rxdma_intr()
969 if ((le32_to_cpu(rd->status) & ACTIVE) != 0) { in mace_rxdma_intr()
970 out_le32(&rd->control, (PAUSE << 16) | PAUSE); in mace_rxdma_intr()
971 while ((in_le32(&rd->status) & ACTIVE) != 0) in mace_rxdma_intr()
977 if (i != mp->rx_fill) { in mace_rxdma_intr()
978 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE)); in mace_rxdma_intr()
979 mp->rx_fill = i; in mace_rxdma_intr()
981 spin_unlock_irqrestore(&mp->lock, flags); in mace_rxdma_intr()
1022 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");