ethernet/8390/8390.h

4  * under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
5  * Some of these names and comments originated from the Crynwr
19 /* The 8390 specific per-packet-header format. */
32 /* Without I/O delay - non ISA or later chips */
68 /* You have one of these per-board */
83 	unsigned word16:1;		/* We have the 16-bit (vs 8-bit)
86 	unsigned bigendian:1;		/* 16-bit big endian mode. Do NOT
96 	short tx1, tx2;			/* Packet lengths for ping-pong tx. */
100 	unsigned char saved_irq;	/* Original dev->irq value. */
146 #define E8390_PAGE1	0x40	/* using the two high-order bits */
150  * - removed AMIGA_PCMCIA from this list, handled as ISA io now
151  * - the _p for generates no delay by default 8390p.c overrides this.
172 #define EN0_TSR		EI_SHIFT(0x04)	/* Transmit status reg RD */
174 #define EN0_NCR		EI_SHIFT(0x05)	/* Number of collision reg RD */
178 #define EN0_ISR		EI_SHIFT(0x07)	/* Interrupt status reg RD WR */
180 #define EN0_RSARLO	EI_SHIFT(0x08)	/* Remote start address reg 0 */
182 #define EN0_RSARHI	EI_SHIFT(0x09)	/* Remote start address reg 1 */
183 #define EN0_RCNTLO	EI_SHIFT(0x0a)	/* Remote byte count reg WR */
184 #define EN0_RCNTHI	EI_SHIFT(0x0b)	/* Remote byte count reg WR */
185 #define EN0_RSR		EI_SHIFT(0x0c)	/* rx status reg RD */
186 #define EN0_RXCR	EI_SHIFT(0x0c)	/* RX configuration reg WR */
187 #define EN0_TXCR	EI_SHIFT(0x0d)	/* TX configuration reg WR */
189 #define EN0_DCFG	EI_SHIFT(0x0e)	/* Data configuration reg WR */
191 #define EN0_IMR		EI_SHIFT(0x0f)	/* Interrupt mask reg WR */
194 /* Bits in EN0_ISR - Interrupt status register */
205 /* Bits in EN0_DCFG - Data config register */
234 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */