dsa/mv88e6xxx/chip.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Marvell 88E6xxx Ethernet switch single-chip definition
23 /* PVT limits for 4-bit port and 5-bit switch */
118 	 * ports 2-4 are not routet to pins.
121 	/* Multi-chip Addressing Mode.
123 	 * when it is non-zero, and use indirect access to internal registers.
126 	/* Dual-chip Addressing Mode
128 	 * allowing two to coexist on the same SMI interface.
275 	/* Handles automatic disabling and re-enabling of the PHY
304 	/* There can be two interrupt controllers, which are chained
345 	/* Per-port timestamping resources. */
411 #define LINK_UNFORCED		-2
427 #define SPEED_UNFORCED		-2
428 #define DUPLEX_UNFORCED		-2
509 	int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
512 	/* SERDES lane mapping */
516 				    u8 lane, struct phylink_link_state *state);
518 				 u8 lane, unsigned int mode,
522 				     u8 lane);
524 				  u8 lane, int speed, int duplex);
529 	int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
532 					 u8 lane);
605 	/* Access port-scoped Precision Time Protocol registers */
657 	return chip->info->pvt;  in mv88e6xxx_has_pvt()
662 	return chip->info->num_databases;  in mv88e6xxx_num_databases()
667 	return chip->info->num_macs;  in mv88e6xxx_num_macs()
672 	return chip->info->num_ports;  in mv88e6xxx_num_ports()
677 	return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);  in mv88e6xxx_port_mask()
682 	return chip->info->num_gpio;  in mv88e6xxx_num_gpio()
687 	return (chip->info->invalid_port_mask & BIT(port)) != 0;  in mv88e6xxx_is_invalid_port()
700 	mutex_lock(&chip->reg_lock);  in mv88e6xxx_reg_lock()
705 	mutex_unlock(&chip->reg_lock);  in mv88e6xxx_reg_unlock()