Lines Matching +full:0 +full:x1ff
13 REG_SWITCH_CNTRL = 0,
30 #define MDIO_MASTER_SEL (1 << 0)
33 #define SF2_REV_MASK 0xffff
35 #define SWITCH_TOP_REV_MASK 0xffff
38 #define PHY_REVISION_MASK 0xffff
41 #define IDDQ_BIAS (1 << 0)
48 #define PHY_PHYAD_MASK 0x1F
53 #define RGMII_MODE_EN (1 << 0)
56 #define INT_EPHY (0 << PORT_MODE_SHIFT)
61 #define PORT_MODE_MASK 0x7
67 #define LPI_COUNT_MASK 0x3F
74 #define INTRL2_CPU_STATUS 0x00
75 #define INTRL2_CPU_SET 0x04
76 #define INTRL2_CPU_CLEAR 0x08
77 #define INTRL2_CPU_MASK_STATUS 0x0c
78 #define INTRL2_CPU_MASK_SET 0x10
79 #define INTRL2_CPU_MASK_CLEAR 0x14
82 #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
95 #define P0_IRQ_OFF 0
111 #define P7_IRQ_OFF 0
115 #define ACB_CONTROL 0x00
116 #define ACB_EN (1 << 0)
119 #define ACB_FLUSH_MASK 0x3
121 #define ACB_QUEUE_0_CFG 0x08
122 #define XOFF_THRESHOLD_MASK 0x7ff
125 #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff
129 #define PKTLEN_MASK 0x3f
130 #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4))
133 #define CORE_G_PCTL_PORT0 0x00000
134 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
135 #define CORE_IMP_CTL 0x00020
136 #define RX_DIS (1 << 0)
142 #define CORE_SWMODE 0x0002c
143 #define SW_FWDG_MODE (1 << 0)
147 #define CORE_STS_OVERRIDE_IMP 0x00038
152 #define CORE_STS_OVERRIDE_IMP2 0x39040
154 #define CORE_NEW_CTRL 0x00084
155 #define IP_MC (1 << 0)
164 #define CORE_SWITCH_CTRL 0x00088
167 #define CORE_DIS_LEARN 0x000f0
169 #define CORE_SFT_LRN_CTRL 0x000f8
172 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
173 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
174 #define LINK_STS (1 << 0)
177 #define SPEED_MASK 0x3
182 #define CORE_WATCHDOG_CTRL 0x001e4
187 #define CORE_FAST_AGE_CTRL 0x00220
188 #define EN_FAST_AGE_STATIC (1 << 0)
196 #define CORE_FAST_AGE_PORT 0x00224
197 #define AGE_PORT_MASK 0xf
199 #define CORE_FAST_AGE_VID 0x00228
200 #define AGE_VID_MASK 0x3fff
202 #define CORE_LNKSTS 0x00400
203 #define LNK_STS_MASK 0x1ff
205 #define CORE_SPDSTS 0x00410
206 #define SPDSTS_10 0
210 #define SPDSTS_MASK 0x3
212 #define CORE_DUPSTS 0x00420
213 #define CORE_DUPSTS_MASK 0x1ff
215 #define CORE_PAUSESTS 0x00428
218 #define CORE_GMNCFGCFG 0x0800
219 #define RST_MIB_CNT (1 << 0)
222 #define CORE_IMP0_PRT_ID 0x0804
224 #define CORE_RST_MIB_CNT_EN 0x0950
226 #define CORE_ARLA_VTBL_RWCTRL 0x1600
227 #define ARLA_VTBL_CMD_WRITE 0
232 #define CORE_ARLA_VTBL_ADDR 0x1604
233 #define VTBL_ADDR_INDEX_MASK 0xfff
235 #define CORE_ARLA_VTBL_ENTRY 0x160c
236 #define FWD_MAP_MASK 0x1ff
237 #define UNTAG_MAP_MASK 0x1ff
239 #define MSTP_INDEX_MASK 0x7
243 #define CORE_MEM_PSM_VDD_CTRL 0x2380
245 #define P_TXQ_PSM_VDD_MASK 0x3
249 #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10))
250 #define PRT_TO_QID_MASK 0x3
253 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
254 #define PORT_VLAN_CTRL_MASK 0x1ff
256 #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80
257 #define TXQ_PAUSE_THD_MASK 0x7ff
259 (x) * 0x8)
261 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
264 #define PRI_MASK 0x7
266 #define CORE_JOIN_ALL_VLAN_EN 0xd140
268 #define CORE_CFP_ACC 0x28000
269 #define OP_STR_DONE (1 << 0)
283 #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT)
286 #define XCESS_ADDR_MASK 0xff
294 #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010
296 #define CORE_CFP_DATA_PORT_0 0x28040
298 (x) * 0x10)
302 #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT)
304 #define IPTOS_MASK 0xff
306 #define IPPROTO_MASK (0xff << IPPROTO_SHIFT)
314 #define SLICE_NUM_MASK 0x3
316 #define CORE_CFP_MASK_PORT_0 0x280c0
319 (x) * 0x10)
321 #define CORE_ACT_POL_DATA0 0x28140
322 #define VLAN_BYP (1 << 0)
326 #define REASON_CODE_MASK 0x3f
329 #define NEW_TC_MASK 0x7
332 #define DST_MAP_IB_MASK 0x1ff
334 #define CHANGE_FWRD_MAP_IB_MASK 0x3
335 #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT)
340 #define NEW_DSCP_IB_MASK 0x3f
342 #define CORE_ACT_POL_DATA1 0x28150
343 #define CHANGE_DSCP_IB (1 << 0)
345 #define DST_MAP_OB_MASK 0x3ff
347 #define CHANGE_FWRD_MAP_OB_MASK 0x3
349 #define NEW_DSCP_OB_MASK 0x3f
352 #define CHAIN_ID_MASK 0xff
355 #define NEW_COLOR_MASK 0x3
356 #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT)
361 #define CORE_ACT_POL_DATA2 0x28160
362 #define MAC_LIMIT_BYPASS (1 << 0)
365 #define NEW_TC_O_MASK 0x7
370 #define CORE_RATE_METER0 0x28180
371 #define COLOR_MODE (1 << 0)
375 #define POLICER_MODE_MASK 0x3
376 #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT)
381 #define CORE_RATE_METER1 0x28190
382 #define EIR_TK_BKT_MASK 0x7fffff
384 #define CORE_RATE_METER2 0x281a0
385 #define EIR_BKT_SIZE_MASK 0xfffff
387 #define CORE_RATE_METER3 0x281b0
388 #define EIR_REF_CNT_MASK 0x7ffff
390 #define CORE_RATE_METER4 0x281c0
391 #define CIR_TK_BKT_MASK 0x7fffff
393 #define CORE_RATE_METER5 0x281d0
394 #define CIR_BKT_SIZE_MASK 0xfffff
396 #define CORE_RATE_METER6 0x281e0
397 #define CIR_REF_CNT_MASK 0x7ffff
399 #define CORE_STAT_GREEN_CNTR 0x28200
400 #define CORE_STAT_YELLOW_CNTR 0x28210
401 #define CORE_STAT_RED_CNTR 0x28220
403 #define CORE_CFP_CTL_REG 0x28400
404 #define CFP_EN_MAP_MASK 0x1ff
407 #define CORE_UDF_0_A_0_8_PORT_0 0x28440
408 #define CFG_UDF_OFFSET_MASK 0x1f
410 #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT)
415 #define CORE_UDF_0_B_0_8_PORT_0 0x28500
418 #define CORE_UDF_0_D_0_11_PORT_0 0x28680
425 #define UDF_SLICE_OFFSET 0x40