1 // SPDX-License-Identifier: GPL-2.0-only
5  *  Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
14 /* nand registers */
18 #define  NAND_WAIT_RD		BIT(0) /* NAND flash status output */
19 #define  NAND_WAIT_WR_C		BIT(3) /* NAND Write/Read complete */
24  * nand commands
25  * The pins of the NAND chip are selected based on the address bits of the
41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
76 	return readb(data->nandaddr + op);  in xway_readb()
84 	writeb(value, data->nandaddr + op);  in xway_writeb()
92 	case -1:  in xway_select_chip()
95 		spin_unlock_irqrestore(&ebu_lock, data->csflags);  in xway_select_chip()
98 		spin_lock_irqsave(&ebu_lock, data->csflags);  in xway_select_chip()
151 	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;  in xway_attach_chip()
153 	if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)  in xway_attach_chip()
154 		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;  in xway_attach_chip()
164  * Probe for the NAND device.
176 	data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),  in xway_nand_probe()
179 		return -ENOMEM;  in xway_nand_probe()
182 	data->nandaddr = devm_ioremap_resource(&pdev->dev, res);  in xway_nand_probe()
183 	if (IS_ERR(data->nandaddr))  in xway_nand_probe()
184 		return PTR_ERR(data->nandaddr);  in xway_nand_probe()
186 	nand_set_flash_node(&data->chip, pdev->dev.of_node);  in xway_nand_probe()
187 	mtd = nand_to_mtd(&data->chip);  in xway_nand_probe()
188 	mtd->dev.parent = &pdev->dev;  in xway_nand_probe()
190 	data->chip.legacy.cmd_ctrl = xway_cmd_ctrl;  in xway_nand_probe()
191 	data->chip.legacy.dev_ready = xway_dev_ready;  in xway_nand_probe()
192 	data->chip.legacy.select_chip = xway_select_chip;  in xway_nand_probe()
193 	data->chip.legacy.write_buf = xway_write_buf;  in xway_nand_probe()
194 	data->chip.legacy.read_buf = xway_read_buf;  in xway_nand_probe()
195 	data->chip.legacy.read_byte = xway_read_byte;  in xway_nand_probe()
196 	data->chip.legacy.chip_delay = 30;  in xway_nand_probe()
198 	nand_controller_init(&data->controller);  in xway_nand_probe()
199 	data->controller.ops = &xway_nand_ops;  in xway_nand_probe()
200 	data->chip.controller = &data->controller;  in xway_nand_probe()
203 	nand_set_controller_data(&data->chip, data);  in xway_nand_probe()
206 	err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs);  in xway_nand_probe()
210 	/* setup the EBU to run in NAND mode on our base addr */  in xway_nand_probe()
211 	ltq_ebu_w32(CPHYSADDR(data->nandaddr)  in xway_nand_probe()
223 	err = nand_scan(&data->chip, 1);  in xway_nand_probe()
229 		nand_cleanup(&data->chip);  in xway_nand_probe()
235  * Remove a NAND device.
240 	struct nand_chip *chip = &data->chip;  in xway_nand_remove()
251 	{ .compatible = "lantiq,nand-xway" },
259 		.name		= "lantiq,nand-xway",