Lines Matching +full:nand +full:- +full:ecc +full:- +full:maximize
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
210 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
211 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_rs_ecc()
219 return -ERANGE; in tegra_nand_ooblayout_no_free()
223 .ecc = tegra_nand_ooblayout_rs_ecc,
231 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength, in tegra_nand_ooblayout_bch_ecc()
235 return -ERANGE; in tegra_nand_ooblayout_bch_ecc()
237 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_bch_ecc()
238 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_bch_ecc()
244 .ecc = tegra_nand_ooblayout_bch_ecc,
253 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_irq()
254 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
255 dev_dbg(ctrl->dev, "isr %08x\n", isr); in tegra_nand_irq()
262 * HW ECC was successful. The data sheet states: in tegra_nand_irq()
263 * Correctable OR Un-correctable errors occurred in the DMA transfer... in tegra_nand_irq()
266 ctrl->last_read_error = true; in tegra_nand_irq()
269 complete(&ctrl->command_complete); in tegra_nand_irq()
272 dev_err(ctrl->dev, "FIFO underrun\n"); in tegra_nand_irq()
275 dev_err(ctrl->dev, "FIFO overrun\n"); in tegra_nand_irq()
279 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
280 complete(&ctrl->dma_complete); in tegra_nand_irq()
284 writel_relaxed(isr, ctrl->regs + ISR); in tegra_nand_irq()
313 dev_err(ctrl->dev, "Tegra NAND controller register dump\n"); in tegra_nand_dump_reg()
320 reg = readl_relaxed(ctrl->regs + (i * 4)); in tegra_nand_dump_reg()
321 dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg); in tegra_nand_dump_reg()
329 disable_irq(ctrl->irq); in tegra_nand_controller_abort()
332 writel_relaxed(0, ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
333 writel_relaxed(0, ctrl->regs + COMMAND); in tegra_nand_controller_abort()
336 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_controller_abort()
337 writel_relaxed(isr, ctrl->regs + ISR); in tegra_nand_controller_abort()
338 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
339 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
341 reinit_completion(&ctrl->command_complete); in tegra_nand_controller_abort()
342 reinit_completion(&ctrl->dma_complete); in tegra_nand_controller_abort()
344 enable_irq(ctrl->irq); in tegra_nand_controller_abort()
352 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_cmd()
358 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in tegra_nand_cmd()
363 instr = &subop->instrs[op_id]; in tegra_nand_cmd()
365 switch (instr->type) { in tegra_nand_cmd()
369 writel_relaxed(instr->ctx.cmd.opcode, in tegra_nand_cmd()
370 ctrl->regs + CMD_REG1); in tegra_nand_cmd()
373 writel_relaxed(instr->ctx.cmd.opcode, in tegra_nand_cmd()
374 ctrl->regs + CMD_REG2); in tegra_nand_cmd()
382 addrs = &instr->ctx.addr.addrs[offset]; in tegra_nand_cmd()
387 naddrs -= i; in tegra_nand_cmd()
391 writel_relaxed(addr1, ctrl->regs + ADDR_REG1); in tegra_nand_cmd()
392 writel_relaxed(addr2, ctrl->regs + ADDR_REG2); in tegra_nand_cmd()
411 memcpy(®, instr->ctx.data.buf.out + offset, size); in tegra_nand_cmd()
413 writel_relaxed(reg, ctrl->regs + RESP); in tegra_nand_cmd()
422 cmd |= COMMAND_GO | COMMAND_CE(ctrl->cur_cs); in tegra_nand_cmd()
423 writel_relaxed(cmd, ctrl->regs + COMMAND); in tegra_nand_cmd()
424 ret = wait_for_completion_timeout(&ctrl->command_complete, in tegra_nand_cmd()
427 dev_err(ctrl->dev, "COMMAND timeout\n"); in tegra_nand_cmd()
430 return -ETIMEDOUT; in tegra_nand_cmd()
434 reg = readl_relaxed(ctrl->regs + RESP); in tegra_nand_cmd()
435 memcpy(instr_data_in->ctx.data.buf.in + offset, ®, size); in tegra_nand_cmd()
460 struct tegra_nand_chip *nand = to_tegra_chip(chip); in tegra_nand_select_target() local
461 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_select_target()
463 ctrl->cur_cs = nand->cs[die_nr]; in tegra_nand_select_target()
471 tegra_nand_select_target(chip, op->cs); in tegra_nand_exec_op()
480 struct tegra_nand_chip *nand = to_tegra_chip(chip); in tegra_nand_hw_ecc() local
482 if (chip->ecc.algo == NAND_ECC_ALGO_BCH && enable) in tegra_nand_hw_ecc()
483 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG); in tegra_nand_hw_ecc()
485 writel_relaxed(0, ctrl->regs + BCH_CONFIG); in tegra_nand_hw_ecc()
488 writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG); in tegra_nand_hw_ecc()
490 writel_relaxed(nand->config, ctrl->regs + CONFIG); in tegra_nand_hw_ecc()
497 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_page_xfer()
503 tegra_nand_select_target(chip, chip->cur_cs); in tegra_nand_page_xfer()
506 writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1); in tegra_nand_page_xfer()
507 writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2); in tegra_nand_page_xfer()
509 writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1); in tegra_nand_page_xfer()
510 writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2); in tegra_nand_page_xfer()
514 /* Lower 16-bits are column, by default 0 */ in tegra_nand_page_xfer()
518 addr1 |= mtd->writesize; in tegra_nand_page_xfer()
519 writel_relaxed(addr1, ctrl->regs + ADDR_REG1); in tegra_nand_page_xfer()
521 if (chip->options & NAND_ROW_ADDR_3) { in tegra_nand_page_xfer()
522 writel_relaxed(page >> 16, ctrl->regs + ADDR_REG2); in tegra_nand_page_xfer()
529 dma_addr = dma_map_single(ctrl->dev, buf, mtd->writesize, dir); in tegra_nand_page_xfer()
530 ret = dma_mapping_error(ctrl->dev, dma_addr); in tegra_nand_page_xfer()
532 dev_err(ctrl->dev, "dma mapping error\n"); in tegra_nand_page_xfer()
533 return -EINVAL; in tegra_nand_page_xfer()
536 writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A); in tegra_nand_page_xfer()
537 writel_relaxed(dma_addr, ctrl->regs + DATA_PTR); in tegra_nand_page_xfer()
541 dma_addr_oob = dma_map_single(ctrl->dev, oob_buf, mtd->oobsize, in tegra_nand_page_xfer()
543 ret = dma_mapping_error(ctrl->dev, dma_addr_oob); in tegra_nand_page_xfer()
545 dev_err(ctrl->dev, "dma mapping error\n"); in tegra_nand_page_xfer()
546 ret = -EINVAL; in tegra_nand_page_xfer()
550 writel_relaxed(oob_len - 1, ctrl->regs + DMA_CFG_B); in tegra_nand_page_xfer()
551 writel_relaxed(dma_addr_oob, ctrl->regs + TAG_PTR); in tegra_nand_page_xfer()
568 writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL); in tegra_nand_page_xfer()
571 COMMAND_CE(ctrl->cur_cs); in tegra_nand_page_xfer()
583 writel_relaxed(cmd, ctrl->regs + COMMAND); in tegra_nand_page_xfer()
585 ret = wait_for_completion_timeout(&ctrl->command_complete, in tegra_nand_page_xfer()
588 dev_err(ctrl->dev, "COMMAND timeout\n"); in tegra_nand_page_xfer()
591 ret = -ETIMEDOUT; in tegra_nand_page_xfer()
595 ret = wait_for_completion_timeout(&ctrl->dma_complete, in tegra_nand_page_xfer()
598 dev_err(ctrl->dev, "DMA timeout\n"); in tegra_nand_page_xfer()
601 ret = -ETIMEDOUT; in tegra_nand_page_xfer()
608 dma_unmap_single(ctrl->dev, dma_addr_oob, mtd->oobsize, dir); in tegra_nand_page_xfer()
611 dma_unmap_single(ctrl->dev, dma_addr, mtd->writesize, dir); in tegra_nand_page_xfer()
620 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_read_page_raw()
623 mtd->oobsize, page, true); in tegra_nand_read_page_raw()
630 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_write_page_raw()
633 mtd->oobsize, page, false); in tegra_nand_write_page_raw()
640 return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi, in tegra_nand_read_oob()
641 mtd->oobsize, page, true); in tegra_nand_read_oob()
648 return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi, in tegra_nand_write_oob()
649 mtd->oobsize, page, false); in tegra_nand_write_oob()
656 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_read_page_hwecc()
657 struct tegra_nand_chip *nand = to_tegra_chip(chip); in tegra_nand_read_page_hwecc() local
658 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_read_page_hwecc()
669 /* No correctable or un-correctable errors, page must have 0 bitflips */ in tegra_nand_read_page_hwecc()
670 if (!ctrl->last_read_error) in tegra_nand_read_page_hwecc()
674 * Correctable or un-correctable errors occurred. Use DEC_STAT_BUF in tegra_nand_read_page_hwecc()
675 * which contains information for all ECC selections. in tegra_nand_read_page_hwecc()
682 ctrl->last_read_error = false; in tegra_nand_read_page_hwecc()
683 dec_stat = readl_relaxed(ctrl->regs + DEC_STAT_BUF); in tegra_nand_read_page_hwecc()
707 if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) { in tegra_nand_read_page_hwecc()
708 mtd->ecc_stats.failed += hweight8(fail_sec_flag); in tegra_nand_read_page_hwecc()
713 * All sectors failed to correct, but the ECC isn't smart in tegra_nand_read_page_hwecc()
716 * erased or if error correction just failed for all sub- in tegra_nand_read_page_hwecc()
723 for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) { in tegra_nand_read_page_hwecc()
724 u8 *data = buf + (chip->ecc.size * bit); in tegra_nand_read_page_hwecc()
725 u8 *oob = chip->oob_poi + nand->ecc.offset + in tegra_nand_read_page_hwecc()
726 (chip->ecc.bytes * bit); in tegra_nand_read_page_hwecc()
728 ret = nand_check_erased_ecc_chunk(data, chip->ecc.size, in tegra_nand_read_page_hwecc()
729 oob, chip->ecc.bytes, in tegra_nand_read_page_hwecc()
731 chip->ecc.strength); in tegra_nand_read_page_hwecc()
733 mtd->ecc_stats.failed++; in tegra_nand_read_page_hwecc()
735 mtd->ecc_stats.corrected += ret; in tegra_nand_read_page_hwecc()
749 * bitflips encountered in any of the ECC regions. As there is in tegra_nand_read_page_hwecc()
756 mtd->ecc_stats.corrected += max_corr_cnt * hweight8(corr_sec_flag); in tegra_nand_read_page_hwecc()
766 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_write_page_hwecc()
767 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_write_page_hwecc()
785 unsigned int rate = clk_get_rate(ctrl->clk) / 1000000; in tegra_nand_setup_timing()
789 val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min, in tegra_nand_setup_timing()
790 timings->tRC_min), period); in tegra_nand_setup_timing()
793 val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min), in tegra_nand_setup_timing()
794 max(timings->tALS_min, timings->tALH_min)), in tegra_nand_setup_timing()
798 val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000, in tegra_nand_setup_timing()
802 reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1)); in tegra_nand_setup_timing()
803 reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1)); in tegra_nand_setup_timing()
804 reg |= TIMING_TWH(OFFSET(DIV_ROUND_UP(timings->tWH_min, period), 1)); in tegra_nand_setup_timing()
805 reg |= TIMING_TWP(OFFSET(DIV_ROUND_UP(timings->tWP_min, period), 1)); in tegra_nand_setup_timing()
806 reg |= TIMING_TRH(OFFSET(DIV_ROUND_UP(timings->tREH_min, period), 1)); in tegra_nand_setup_timing()
808 writel_relaxed(reg, ctrl->regs + TIMING_1); in tegra_nand_setup_timing()
810 val = DIV_ROUND_UP(timings->tADL_min, period); in tegra_nand_setup_timing()
813 writel_relaxed(reg, ctrl->regs + TIMING_2); in tegra_nand_setup_timing()
819 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_setup_interface()
846 bool maximize = base->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH; in tegra_nand_get_strength() local
851 * maximize the BCH strength. in tegra_nand_get_strength()
856 if (maximize) { in tegra_nand_get_strength()
857 strength_sel = strength[strength_len - i - 1]; in tegra_nand_get_strength()
861 if (strength_sel < requirements->strength) in tegra_nand_get_strength()
867 bytes_per_page = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_get_strength()
870 if (bytes_per_page < (oobsize - SKIP_SPARE_BYTES)) in tegra_nand_get_strength()
874 return -EINVAL; in tegra_nand_get_strength()
882 switch (chip->ecc.algo) { in tegra_nand_select_strength()
885 if (chip->options & NAND_IS_BOOT_MEDIUM) { in tegra_nand_select_strength()
895 if (chip->options & NAND_IS_BOOT_MEDIUM) { in tegra_nand_select_strength()
904 return -EINVAL; in tegra_nand_select_strength()
913 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_attach_chip()
915 nanddev_get_ecc_requirements(&chip->base); in tegra_nand_attach_chip()
916 struct tegra_nand_chip *nand = to_tegra_chip(chip); in tegra_nand_attach_chip() local
921 if (chip->bbt_options & NAND_BBT_USE_FLASH) in tegra_nand_attach_chip()
922 chip->bbt_options |= NAND_BBT_NO_OOB; in tegra_nand_attach_chip()
924 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in tegra_nand_attach_chip()
925 chip->ecc.size = 512; in tegra_nand_attach_chip()
926 chip->ecc.steps = mtd->writesize / chip->ecc.size; in tegra_nand_attach_chip()
927 if (requirements->step_size != 512) { in tegra_nand_attach_chip()
928 dev_err(ctrl->dev, "Unsupported step size %d\n", in tegra_nand_attach_chip()
929 requirements->step_size); in tegra_nand_attach_chip()
930 return -EINVAL; in tegra_nand_attach_chip()
933 chip->ecc.read_page = tegra_nand_read_page_hwecc; in tegra_nand_attach_chip()
934 chip->ecc.write_page = tegra_nand_write_page_hwecc; in tegra_nand_attach_chip()
935 chip->ecc.read_page_raw = tegra_nand_read_page_raw; in tegra_nand_attach_chip()
936 chip->ecc.write_page_raw = tegra_nand_write_page_raw; in tegra_nand_attach_chip()
937 chip->ecc.read_oob = tegra_nand_read_oob; in tegra_nand_attach_chip()
938 chip->ecc.write_oob = tegra_nand_write_oob; in tegra_nand_attach_chip()
940 if (chip->options & NAND_BUSWIDTH_16) in tegra_nand_attach_chip()
941 nand->config |= CONFIG_BUS_WIDTH_16; in tegra_nand_attach_chip()
943 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { in tegra_nand_attach_chip()
944 if (mtd->writesize < 2048) in tegra_nand_attach_chip()
945 chip->ecc.algo = NAND_ECC_ALGO_RS; in tegra_nand_attach_chip()
947 chip->ecc.algo = NAND_ECC_ALGO_BCH; in tegra_nand_attach_chip()
950 if (chip->ecc.algo == NAND_ECC_ALGO_BCH && mtd->writesize < 2048) { in tegra_nand_attach_chip()
951 dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n"); in tegra_nand_attach_chip()
952 return -EINVAL; in tegra_nand_attach_chip()
955 if (!chip->ecc.strength) { in tegra_nand_attach_chip()
956 ret = tegra_nand_select_strength(chip, mtd->oobsize); in tegra_nand_attach_chip()
958 dev_err(ctrl->dev, in tegra_nand_attach_chip()
960 requirements->strength); in tegra_nand_attach_chip()
964 chip->ecc.strength = ret; in tegra_nand_attach_chip()
967 nand->config_ecc = CONFIG_PIPE_EN | CONFIG_SKIP_SPARE | in tegra_nand_attach_chip()
970 switch (chip->ecc.algo) { in tegra_nand_attach_chip()
972 bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength; in tegra_nand_attach_chip()
974 nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL | in tegra_nand_attach_chip()
976 switch (chip->ecc.strength) { in tegra_nand_attach_chip()
978 nand->config_ecc |= CONFIG_TVAL_4; in tegra_nand_attach_chip()
981 nand->config_ecc |= CONFIG_TVAL_6; in tegra_nand_attach_chip()
984 nand->config_ecc |= CONFIG_TVAL_8; in tegra_nand_attach_chip()
987 dev_err(ctrl->dev, "ECC strength %d not supported\n", in tegra_nand_attach_chip()
988 chip->ecc.strength); in tegra_nand_attach_chip()
989 return -EINVAL; in tegra_nand_attach_chip()
993 bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength; in tegra_nand_attach_chip()
995 nand->bch_config = BCH_ENABLE; in tegra_nand_attach_chip()
996 switch (chip->ecc.strength) { in tegra_nand_attach_chip()
998 nand->bch_config |= BCH_TVAL_4; in tegra_nand_attach_chip()
1001 nand->bch_config |= BCH_TVAL_8; in tegra_nand_attach_chip()
1004 nand->bch_config |= BCH_TVAL_14; in tegra_nand_attach_chip()
1007 nand->bch_config |= BCH_TVAL_16; in tegra_nand_attach_chip()
1010 dev_err(ctrl->dev, "ECC strength %d not supported\n", in tegra_nand_attach_chip()
1011 chip->ecc.strength); in tegra_nand_attach_chip()
1012 return -EINVAL; in tegra_nand_attach_chip()
1016 dev_err(ctrl->dev, "ECC algorithm not supported\n"); in tegra_nand_attach_chip()
1017 return -EINVAL; in tegra_nand_attach_chip()
1020 dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n", in tegra_nand_attach_chip()
1021 chip->ecc.algo == NAND_ECC_ALGO_BCH ? "BCH" : "RS", in tegra_nand_attach_chip()
1022 chip->ecc.strength); in tegra_nand_attach_chip()
1024 chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE); in tegra_nand_attach_chip()
1026 switch (mtd->writesize) { in tegra_nand_attach_chip()
1028 nand->config |= CONFIG_PS_256; in tegra_nand_attach_chip()
1031 nand->config |= CONFIG_PS_512; in tegra_nand_attach_chip()
1034 nand->config |= CONFIG_PS_1024; in tegra_nand_attach_chip()
1037 nand->config |= CONFIG_PS_2048; in tegra_nand_attach_chip()
1040 nand->config |= CONFIG_PS_4096; in tegra_nand_attach_chip()
1043 dev_err(ctrl->dev, "Unsupported writesize %d\n", in tegra_nand_attach_chip()
1044 mtd->writesize); in tegra_nand_attach_chip()
1045 return -ENODEV; in tegra_nand_attach_chip()
1048 /* Store complete configuration for HW ECC in config_ecc */ in tegra_nand_attach_chip()
1049 nand->config_ecc |= nand->config; in tegra_nand_attach_chip()
1051 /* Non-HW ECC read/writes complete OOB */ in tegra_nand_attach_chip()
1052 nand->config |= CONFIG_TAG_BYTE_SIZE(mtd->oobsize - 1); in tegra_nand_attach_chip()
1053 writel_relaxed(nand->config, ctrl->regs + CONFIG); in tegra_nand_attach_chip()
1067 struct device_node *np = dev->of_node; in tegra_nand_chips_init()
1070 struct tegra_nand_chip *nand; in tegra_nand_chips_init() local
1077 dev_err(dev, "Currently only one NAND chip supported\n"); in tegra_nand_chips_init()
1078 return -EINVAL; in tegra_nand_chips_init()
1086 return -EINVAL; in tegra_nand_chips_init()
1089 /* Retrieve CS id, currently only single die NAND supported */ in tegra_nand_chips_init()
1096 nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL); in tegra_nand_chips_init()
1097 if (!nand) in tegra_nand_chips_init()
1098 return -ENOMEM; in tegra_nand_chips_init()
1100 nand->cs[0] = cs; in tegra_nand_chips_init()
1102 nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW); in tegra_nand_chips_init()
1104 if (IS_ERR(nand->wp_gpio)) { in tegra_nand_chips_init()
1105 ret = PTR_ERR(nand->wp_gpio); in tegra_nand_chips_init()
1110 chip = &nand->chip; in tegra_nand_chips_init()
1111 chip->controller = &ctrl->controller; in tegra_nand_chips_init()
1115 mtd->dev.parent = dev; in tegra_nand_chips_init()
1116 mtd->owner = THIS_MODULE; in tegra_nand_chips_init()
1120 if (!mtd->name) in tegra_nand_chips_init()
1121 mtd->name = "tegra_nand"; in tegra_nand_chips_init()
1123 chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA; in tegra_nand_chips_init()
1129 mtd_ooblayout_ecc(mtd, 0, &nand->ecc); in tegra_nand_chips_init()
1138 ctrl->chip = chip; in tegra_nand_chips_init()
1150 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); in tegra_nand_probe()
1152 return -ENOMEM; in tegra_nand_probe()
1154 ctrl->dev = &pdev->dev; in tegra_nand_probe()
1155 nand_controller_init(&ctrl->controller); in tegra_nand_probe()
1156 ctrl->controller.ops = &tegra_nand_controller_ops; in tegra_nand_probe()
1159 ctrl->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_nand_probe()
1160 if (IS_ERR(ctrl->regs)) in tegra_nand_probe()
1161 return PTR_ERR(ctrl->regs); in tegra_nand_probe()
1163 rst = devm_reset_control_get(&pdev->dev, "nand"); in tegra_nand_probe()
1167 ctrl->clk = devm_clk_get(&pdev->dev, "nand"); in tegra_nand_probe()
1168 if (IS_ERR(ctrl->clk)) in tegra_nand_probe()
1169 return PTR_ERR(ctrl->clk); in tegra_nand_probe()
1171 err = clk_prepare_enable(ctrl->clk); in tegra_nand_probe()
1177 dev_err(ctrl->dev, "Failed to reset HW: %d\n", err); in tegra_nand_probe()
1181 writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD); in tegra_nand_probe()
1182 writel_relaxed(HWSTATUS_MASK_DEFAULT, ctrl->regs + HWSTATUS_MASK); in tegra_nand_probe()
1183 writel_relaxed(INT_MASK, ctrl->regs + IER); in tegra_nand_probe()
1185 init_completion(&ctrl->command_complete); in tegra_nand_probe()
1186 init_completion(&ctrl->dma_complete); in tegra_nand_probe()
1188 ctrl->irq = platform_get_irq(pdev, 0); in tegra_nand_probe()
1189 err = devm_request_irq(&pdev->dev, ctrl->irq, tegra_nand_irq, 0, in tegra_nand_probe()
1190 dev_name(&pdev->dev), ctrl); in tegra_nand_probe()
1192 dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err); in tegra_nand_probe()
1196 writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL); in tegra_nand_probe()
1198 err = tegra_nand_chips_init(ctrl->dev, ctrl); in tegra_nand_probe()
1207 clk_disable_unprepare(ctrl->clk); in tegra_nand_probe()
1214 struct nand_chip *chip = ctrl->chip; in tegra_nand_remove()
1224 clk_disable_unprepare(ctrl->clk); in tegra_nand_remove()
1230 { .compatible = "nvidia,tegra20-nand" },
1237 .name = "tegra-nand",
1245 MODULE_DESCRIPTION("NVIDIA Tegra NAND driver");