Lines Matching +full:nand +full:- +full:ecc +full:- +full:placement
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * NXP LPC32XX NAND SLC driver
24 #include <linux/dma-mapping.h>
32 #define LPC32XX_MODNAME "lpc32xx-nand"
35 * SLC NAND controller register offsets
57 #define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
58 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
65 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
66 #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
76 #define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
88 #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
110 /* ECC line party fetch macro */
115 * DMA requires storage space for the DMA local buffer and the hardware ECC
122 /* Number of bytes used for ECC stored in NAND per 256 bytes */
126 * If the NAND base clock frequency can't be fetched, this frequency will be
128 * used for NAND accesses.
136 * NAND ECC Layout for small page NAND devices
143 return -ERANGE; in lpc32xx_ooblayout_ecc()
145 oobregion->length = 6; in lpc32xx_ooblayout_ecc()
146 oobregion->offset = 10; in lpc32xx_ooblayout_ecc()
155 return -ERANGE; in lpc32xx_ooblayout_free()
158 oobregion->offset = 0; in lpc32xx_ooblayout_free()
159 oobregion->length = 4; in lpc32xx_ooblayout_free()
161 oobregion->offset = 6; in lpc32xx_ooblayout_free()
162 oobregion->length = 4; in lpc32xx_ooblayout_free()
169 .ecc = lpc32xx_ooblayout_ecc,
201 * NAND platform configuration structure
231 * DMA and CPU addresses of ECC work area and data buffer
243 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); in lpc32xx_nand_setup()
247 writel(0, SLC_CFG(host->io_base)); in lpc32xx_nand_setup()
248 writel(0, SLC_IEN(host->io_base)); in lpc32xx_nand_setup()
250 SLC_ICR(host->io_base)); in lpc32xx_nand_setup()
253 clkrate = clk_get_rate(host->clk); in lpc32xx_nand_setup()
258 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) | in lpc32xx_nand_setup()
259 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) | in lpc32xx_nand_setup()
260 SLCTAC_WHOLD(clkrate, host->ncfg->whold) | in lpc32xx_nand_setup()
261 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) | in lpc32xx_nand_setup()
262 SLCTAC_RDR(host->ncfg->rdr_clks) | in lpc32xx_nand_setup()
263 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) | in lpc32xx_nand_setup()
264 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) | in lpc32xx_nand_setup()
265 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup); in lpc32xx_nand_setup()
266 writel(tmp, SLC_TAC(host->io_base)); in lpc32xx_nand_setup()
279 tmp = readl(SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
284 writel(tmp, SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
288 writel(cmd, SLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
290 writel(cmd, SLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
302 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0) in lpc32xx_nand_device_ready()
309 * Enable NAND write protect
313 if (gpio_is_valid(host->ncfg->wp_gpio)) in lpc32xx_wp_enable()
314 gpio_set_value(host->ncfg->wp_gpio, 0); in lpc32xx_wp_enable()
318 * Disable NAND write protect
322 if (gpio_is_valid(host->ncfg->wp_gpio)) in lpc32xx_wp_disable()
323 gpio_set_value(host->ncfg->wp_gpio, 1); in lpc32xx_wp_disable()
327 * Prepares SLC for transfers with H/W ECC enabled
331 /* Hardware ECC is enabled automatically in hardware as needed */ in lpc32xx_nand_ecc_enable()
335 * Calculates the ECC for the data
342 * ECC is calculated automatically in hardware during syndrome read in lpc32xx_nand_ecc_calculate()
349 * Read a single byte from NAND device
355 return (uint8_t)readl(SLC_DATA(host->io_base)); in lpc32xx_nand_read_byte()
359 * Simple device read without ECC
365 /* Direct device read with no ECC */ in lpc32xx_nand_read_buf()
366 while (len-- > 0) in lpc32xx_nand_read_buf()
367 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base)); in lpc32xx_nand_read_buf()
371 * Simple device write without ECC
378 /* Direct device write with no ECC */ in lpc32xx_nand_write_buf()
379 while (len-- > 0) in lpc32xx_nand_write_buf()
380 writel((uint32_t)*buf++, SLC_DATA(host->io_base)); in lpc32xx_nand_write_buf()
384 * Read the OOB data from the device without ECC using FIFO method
390 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); in lpc32xx_nand_read_oob_syndrome()
394 * Write the OOB data to the device without ECC using FIFO method
400 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, in lpc32xx_nand_write_oob_syndrome()
401 mtd->oobsize); in lpc32xx_nand_write_oob_syndrome()
405 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
407 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) in lpc32xx_slc_ecc_copy() argument
412 uint32_t ce = ecc[i / 3]; in lpc32xx_slc_ecc_copy()
436 host->dma_slave_config.direction = dir; in lpc32xx_xmit_dma()
437 host->dma_slave_config.src_addr = dma; in lpc32xx_xmit_dma()
438 host->dma_slave_config.dst_addr = dma; in lpc32xx_xmit_dma()
439 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in lpc32xx_xmit_dma()
440 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in lpc32xx_xmit_dma()
441 host->dma_slave_config.src_maxburst = 4; in lpc32xx_xmit_dma()
442 host->dma_slave_config.dst_maxburst = 4; in lpc32xx_xmit_dma()
444 host->dma_slave_config.device_fc = false; in lpc32xx_xmit_dma()
445 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { in lpc32xx_xmit_dma()
446 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); in lpc32xx_xmit_dma()
447 return -ENXIO; in lpc32xx_xmit_dma()
450 sg_init_one(&host->sgl, mem, len); in lpc32xx_xmit_dma()
452 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, in lpc32xx_xmit_dma()
455 dev_err(mtd->dev.parent, "Failed to map sg list\n"); in lpc32xx_xmit_dma()
456 return -ENXIO; in lpc32xx_xmit_dma()
458 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, in lpc32xx_xmit_dma()
461 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); in lpc32xx_xmit_dma()
465 init_completion(&host->comp); in lpc32xx_xmit_dma()
466 desc->callback = lpc32xx_dma_complete_func; in lpc32xx_xmit_dma()
467 desc->callback_param = &host->comp; in lpc32xx_xmit_dma()
470 dma_async_issue_pending(host->dma_chan); in lpc32xx_xmit_dma()
472 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000)); in lpc32xx_xmit_dma()
474 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, in lpc32xx_xmit_dma()
479 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, in lpc32xx_xmit_dma()
481 return -ENXIO; in lpc32xx_xmit_dma()
485 * DMA read/write transfers with ECC support
504 dma_buf = host->data_buf; in lpc32xx_xfer()
507 memcpy(host->data_buf, buf, mtd->writesize); in lpc32xx_xfer()
511 writel(readl(SLC_CFG(host->io_base)) | in lpc32xx_xfer()
513 SLCCFG_DMA_BURST, SLC_CFG(host->io_base)); in lpc32xx_xfer()
515 writel((readl(SLC_CFG(host->io_base)) | in lpc32xx_xfer()
518 SLC_CFG(host->io_base)); in lpc32xx_xfer()
521 /* Clear initial ECC */ in lpc32xx_xfer()
522 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base)); in lpc32xx_xfer()
525 writel(mtd->writesize, SLC_TC(host->io_base)); in lpc32xx_xfer()
527 /* Start transfer in the NAND controller */ in lpc32xx_xfer()
528 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START, in lpc32xx_xfer()
529 SLC_CTRL(host->io_base)); in lpc32xx_xfer()
531 for (i = 0; i < chip->ecc.steps; i++) { in lpc32xx_xfer()
533 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma), in lpc32xx_xfer()
534 dma_buf + i * chip->ecc.size, in lpc32xx_xfer()
535 mtd->writesize / chip->ecc.steps, dir); in lpc32xx_xfer()
539 /* Always _read_ ECC */ in lpc32xx_xfer()
540 if (i == chip->ecc.steps - 1) in lpc32xx_xfer()
542 if (!read) /* ECC availability delayed on write */ in lpc32xx_xfer()
544 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma), in lpc32xx_xfer()
545 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM); in lpc32xx_xfer()
551 * According to NXP, the DMA can be finished here, but the NAND in lpc32xx_xfer()
553 * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty) in lpc32xx_xfer()
557 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) { in lpc32xx_xfer()
558 dev_warn(mtd->dev.parent, "FIFO not empty!\n"); in lpc32xx_xfer()
560 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) && in lpc32xx_xfer()
564 dev_err(mtd->dev.parent, "FIFO held data too long\n"); in lpc32xx_xfer()
565 status = -EIO; in lpc32xx_xfer()
569 /* Read last calculated ECC value */ in lpc32xx_xfer()
572 host->ecc_buf[chip->ecc.steps - 1] = in lpc32xx_xfer()
573 readl(SLC_ECC(host->io_base)); in lpc32xx_xfer()
576 dmaengine_terminate_all(host->dma_chan); in lpc32xx_xfer()
578 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO || in lpc32xx_xfer()
579 readl(SLC_TC(host->io_base))) { in lpc32xx_xfer()
581 dev_err(mtd->dev.parent, "DMA FIFO failure\n"); in lpc32xx_xfer()
582 status = -EIO; in lpc32xx_xfer()
585 /* Stop DMA & HW ECC */ in lpc32xx_xfer()
586 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START, in lpc32xx_xfer()
587 SLC_CTRL(host->io_base)); in lpc32xx_xfer()
588 writel(readl(SLC_CFG(host->io_base)) & in lpc32xx_xfer()
590 SLCCFG_DMA_BURST), SLC_CFG(host->io_base)); in lpc32xx_xfer()
593 memcpy(buf, host->data_buf, mtd->writesize); in lpc32xx_xfer()
599 * Read the data and OOB data from the device, use ECC correction with the
600 * data, disable ECC for the OOB data
614 /* Read data and oob, calculate ECC */ in lpc32xx_nand_read_page_syndrome()
615 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1); in lpc32xx_nand_read_page_syndrome()
618 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize); in lpc32xx_nand_read_page_syndrome()
620 /* Convert to stored ECC format */ in lpc32xx_nand_read_page_syndrome()
621 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps); in lpc32xx_nand_read_page_syndrome()
623 /* Pointer to ECC data retrieved from NAND spare area */ in lpc32xx_nand_read_page_syndrome()
628 oobecc = chip->oob_poi + oobregion.offset; in lpc32xx_nand_read_page_syndrome()
630 for (i = 0; i < chip->ecc.steps; i++) { in lpc32xx_nand_read_page_syndrome()
631 stat = chip->ecc.correct(chip, buf, oobecc, in lpc32xx_nand_read_page_syndrome()
632 &tmpecc[i * chip->ecc.bytes]); in lpc32xx_nand_read_page_syndrome()
634 mtd->ecc_stats.failed++; in lpc32xx_nand_read_page_syndrome()
636 mtd->ecc_stats.corrected += stat; in lpc32xx_nand_read_page_syndrome()
638 buf += chip->ecc.size; in lpc32xx_nand_read_page_syndrome()
639 oobecc += chip->ecc.bytes; in lpc32xx_nand_read_page_syndrome()
646 * Read the data and OOB data from the device, no ECC correction with the
659 chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps); in lpc32xx_nand_read_page_raw_syndrome()
660 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize); in lpc32xx_nand_read_page_raw_syndrome()
666 * Write the data and OOB data to the device, use ECC with the data,
667 * disable ECC for the OOB data
681 /* Write data, calculate ECC on outbound data */ in lpc32xx_nand_write_page_syndrome()
682 error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0); in lpc32xx_nand_write_page_syndrome()
687 * The calculated ECC needs some manual work done to it before in lpc32xx_nand_write_page_syndrome()
688 * committing it to NAND. Process the calculated ECC and place in lpc32xx_nand_write_page_syndrome()
694 pb = chip->oob_poi + oobregion.offset; in lpc32xx_nand_write_page_syndrome()
695 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps); in lpc32xx_nand_write_page_syndrome()
697 /* Write ECC data to device */ in lpc32xx_nand_write_page_syndrome()
698 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); in lpc32xx_nand_write_page_syndrome()
704 * Write the data and OOB data to the device, no ECC correction with the
715 chip->ecc.size * chip->ecc.steps); in lpc32xx_nand_write_page_raw_syndrome()
716 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); in lpc32xx_nand_write_page_raw_syndrome()
723 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip); in lpc32xx_nand_dma_setup()
726 if (!host->pdata || !host->pdata->dma_filter) { in lpc32xx_nand_dma_setup()
727 dev_err(mtd->dev.parent, "no DMA platform data\n"); in lpc32xx_nand_dma_setup()
728 return -ENOENT; in lpc32xx_nand_dma_setup()
733 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, in lpc32xx_nand_dma_setup()
734 "nand-slc"); in lpc32xx_nand_dma_setup()
735 if (!host->dma_chan) { in lpc32xx_nand_dma_setup()
736 dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); in lpc32xx_nand_dma_setup()
737 return -EBUSY; in lpc32xx_nand_dma_setup()
746 struct device_node *np = dev->of_node; in lpc32xx_parse_dt()
752 of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks); in lpc32xx_parse_dt()
753 of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth); in lpc32xx_parse_dt()
754 of_property_read_u32(np, "nxp,whold", &ncfg->whold); in lpc32xx_parse_dt()
755 of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup); in lpc32xx_parse_dt()
756 of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks); in lpc32xx_parse_dt()
757 of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth); in lpc32xx_parse_dt()
758 of_property_read_u32(np, "nxp,rhold", &ncfg->rhold); in lpc32xx_parse_dt()
759 of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup); in lpc32xx_parse_dt()
761 if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold || in lpc32xx_parse_dt()
762 !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth || in lpc32xx_parse_dt()
763 !ncfg->rhold || !ncfg->rsetup) { in lpc32xx_parse_dt()
768 ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0); in lpc32xx_parse_dt()
778 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) in lpc32xx_nand_attach_chip()
781 /* OOB and ECC CPU and DMA work areas */ in lpc32xx_nand_attach_chip()
782 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE); in lpc32xx_nand_attach_chip()
789 if (mtd->writesize <= 512) in lpc32xx_nand_attach_chip()
792 chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; in lpc32xx_nand_attach_chip()
794 chip->ecc.size = 256; in lpc32xx_nand_attach_chip()
795 chip->ecc.strength = 1; in lpc32xx_nand_attach_chip()
796 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES; in lpc32xx_nand_attach_chip()
797 chip->ecc.prepad = 0; in lpc32xx_nand_attach_chip()
798 chip->ecc.postpad = 0; in lpc32xx_nand_attach_chip()
799 chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome; in lpc32xx_nand_attach_chip()
800 chip->ecc.read_page = lpc32xx_nand_read_page_syndrome; in lpc32xx_nand_attach_chip()
801 chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome; in lpc32xx_nand_attach_chip()
802 chip->ecc.write_page = lpc32xx_nand_write_page_syndrome; in lpc32xx_nand_attach_chip()
803 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; in lpc32xx_nand_attach_chip()
804 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; in lpc32xx_nand_attach_chip()
805 chip->ecc.calculate = lpc32xx_nand_ecc_calculate; in lpc32xx_nand_attach_chip()
806 chip->ecc.correct = nand_correct_data; in lpc32xx_nand_attach_chip()
807 chip->ecc.hwctl = lpc32xx_nand_ecc_enable; in lpc32xx_nand_attach_chip()
811 * won't interfere with the ECC layout. Large and huge page in lpc32xx_nand_attach_chip()
814 if ((chip->bbt_options & NAND_BBT_USE_FLASH) && in lpc32xx_nand_attach_chip()
815 mtd->writesize <= 512) { in lpc32xx_nand_attach_chip()
816 chip->bbt_td = &bbt_smallpage_main_descr; in lpc32xx_nand_attach_chip()
817 chip->bbt_md = &bbt_smallpage_mirror_descr; in lpc32xx_nand_attach_chip()
828 * Probe for NAND controller
839 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); in lpc32xx_nand_probe()
841 return -ENOMEM; in lpc32xx_nand_probe()
844 host->io_base = devm_ioremap_resource(&pdev->dev, rc); in lpc32xx_nand_probe()
845 if (IS_ERR(host->io_base)) in lpc32xx_nand_probe()
846 return PTR_ERR(host->io_base); in lpc32xx_nand_probe()
848 host->io_base_dma = rc->start; in lpc32xx_nand_probe()
849 if (pdev->dev.of_node) in lpc32xx_nand_probe()
850 host->ncfg = lpc32xx_parse_dt(&pdev->dev); in lpc32xx_nand_probe()
851 if (!host->ncfg) { in lpc32xx_nand_probe()
852 dev_err(&pdev->dev, in lpc32xx_nand_probe()
853 "Missing or bad NAND config from device tree\n"); in lpc32xx_nand_probe()
854 return -ENOENT; in lpc32xx_nand_probe()
856 if (host->ncfg->wp_gpio == -EPROBE_DEFER) in lpc32xx_nand_probe()
857 return -EPROBE_DEFER; in lpc32xx_nand_probe()
858 if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev, in lpc32xx_nand_probe()
859 host->ncfg->wp_gpio, "NAND WP")) { in lpc32xx_nand_probe()
860 dev_err(&pdev->dev, "GPIO not available\n"); in lpc32xx_nand_probe()
861 return -EBUSY; in lpc32xx_nand_probe()
865 host->pdata = dev_get_platdata(&pdev->dev); in lpc32xx_nand_probe()
867 chip = &host->nand_chip; in lpc32xx_nand_probe()
870 nand_set_flash_node(chip, pdev->dev.of_node); in lpc32xx_nand_probe()
871 mtd->owner = THIS_MODULE; in lpc32xx_nand_probe()
872 mtd->dev.parent = &pdev->dev; in lpc32xx_nand_probe()
874 /* Get NAND clock */ in lpc32xx_nand_probe()
875 host->clk = devm_clk_get(&pdev->dev, NULL); in lpc32xx_nand_probe()
876 if (IS_ERR(host->clk)) { in lpc32xx_nand_probe()
877 dev_err(&pdev->dev, "Clock failure\n"); in lpc32xx_nand_probe()
878 res = -ENOENT; in lpc32xx_nand_probe()
881 res = clk_prepare_enable(host->clk); in lpc32xx_nand_probe()
885 /* Set NAND IO addresses and command/ready functions */ in lpc32xx_nand_probe()
886 chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base); in lpc32xx_nand_probe()
887 chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base); in lpc32xx_nand_probe()
888 chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl; in lpc32xx_nand_probe()
889 chip->legacy.dev_ready = lpc32xx_nand_device_ready; in lpc32xx_nand_probe()
890 chip->legacy.chip_delay = 20; /* 20us command delay time */ in lpc32xx_nand_probe()
892 /* Init NAND controller */ in lpc32xx_nand_probe()
897 /* NAND callbacks for LPC32xx SLC hardware */ in lpc32xx_nand_probe()
898 chip->legacy.read_byte = lpc32xx_nand_read_byte; in lpc32xx_nand_probe()
899 chip->legacy.read_buf = lpc32xx_nand_read_buf; in lpc32xx_nand_probe()
900 chip->legacy.write_buf = lpc32xx_nand_write_buf; in lpc32xx_nand_probe()
904 * extra space for the spare area and ECC storage area in lpc32xx_nand_probe()
906 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE; in lpc32xx_nand_probe()
907 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len, in lpc32xx_nand_probe()
909 if (host->data_buf == NULL) { in lpc32xx_nand_probe()
910 res = -ENOMEM; in lpc32xx_nand_probe()
916 res = -EIO; in lpc32xx_nand_probe()
920 /* Find NAND device */ in lpc32xx_nand_probe()
921 chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops; in lpc32xx_nand_probe()
926 mtd->name = "nxp_lpc3220_slc"; in lpc32xx_nand_probe()
927 res = mtd_device_register(mtd, host->ncfg->parts, in lpc32xx_nand_probe()
928 host->ncfg->num_parts); in lpc32xx_nand_probe()
937 dma_release_channel(host->dma_chan); in lpc32xx_nand_probe()
939 clk_disable_unprepare(host->clk); in lpc32xx_nand_probe()
947 * Remove NAND device.
953 struct nand_chip *chip = &host->nand_chip; in lpc32xx_nand_remove()
959 dma_release_channel(host->dma_chan); in lpc32xx_nand_remove()
962 tmp = readl(SLC_CTRL(host->io_base)); in lpc32xx_nand_remove()
964 writel(tmp, SLC_CTRL(host->io_base)); in lpc32xx_nand_remove()
966 clk_disable_unprepare(host->clk); in lpc32xx_nand_remove()
978 /* Re-enable NAND clock */ in lpc32xx_nand_resume()
979 ret = clk_prepare_enable(host->clk); in lpc32xx_nand_resume()
983 /* Fresh init of NAND controller */ in lpc32xx_nand_resume()
998 tmp = readl(SLC_CTRL(host->io_base)); in lpc32xx_nand_suspend()
1000 writel(tmp, SLC_CTRL(host->io_base)); in lpc32xx_nand_suspend()
1006 clk_disable_unprepare(host->clk); in lpc32xx_nand_suspend()
1017 { .compatible = "nxp,lpc3220-slc" },
1038 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");