Lines Matching +full:nand +full:- +full:ecc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
5 * Driver for NAND portions
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
19 #include <linux/dma-direction.h>
20 #include <linux/dma-mapping.h>
36 #include <mtd/mtd-abi.h>
60 /* fsmc controller registers for NAND flash */
111 * struct fsmc_nand_data - structure for FSMC NAND device state
115 * @nand: Chip related info for a NAND flash.
119 * @mode: Access mode
123 * @write_dma_chan: DMA channel for write access to NAND
126 * @dev_timings: NAND timings
128 * @data_pa: NAND Physical port for Data.
129 * @data_va: NAND port for Data.
130 * @cmd_va: NAND port for Command.
131 * @addr_va: NAND port for Address.
137 struct nand_chip nand; member
141 enum access_mode mode; member
163 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_ecc()
164 return -ERANGE; in fsmc_ecc1_ooblayout_ecc()
166 oobregion->offset = (section * 16) + 2; in fsmc_ecc1_ooblayout_ecc()
167 oobregion->length = 3; in fsmc_ecc1_ooblayout_ecc()
177 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_free()
178 return -ERANGE; in fsmc_ecc1_ooblayout_free()
180 oobregion->offset = (section * 16) + 8; in fsmc_ecc1_ooblayout_free()
182 if (section < chip->ecc.steps - 1) in fsmc_ecc1_ooblayout_free()
183 oobregion->length = 8; in fsmc_ecc1_ooblayout_free()
185 oobregion->length = mtd->oobsize - oobregion->offset; in fsmc_ecc1_ooblayout_free()
191 .ecc = fsmc_ecc1_ooblayout_ecc,
196 * ECC placement definitions in oobfree type format.
197 * There are 13 bytes of ecc for every 512 byte block and it has to be read
206 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_ecc()
207 return -ERANGE; in fsmc_ecc4_ooblayout_ecc()
209 oobregion->length = chip->ecc.bytes; in fsmc_ecc4_ooblayout_ecc()
211 if (!section && mtd->writesize <= 512) in fsmc_ecc4_ooblayout_ecc()
212 oobregion->offset = 0; in fsmc_ecc4_ooblayout_ecc()
214 oobregion->offset = (section * 16) + 2; in fsmc_ecc4_ooblayout_ecc()
224 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_free()
225 return -ERANGE; in fsmc_ecc4_ooblayout_free()
227 oobregion->offset = (section * 16) + 15; in fsmc_ecc4_ooblayout_free()
229 if (section < chip->ecc.steps - 1) in fsmc_ecc4_ooblayout_free()
230 oobregion->length = 3; in fsmc_ecc4_ooblayout_free()
232 oobregion->length = mtd->oobsize - oobregion->offset; in fsmc_ecc4_ooblayout_free()
238 .ecc = fsmc_ecc4_ooblayout_ecc,
244 return container_of(chip, struct fsmc_nand_data, nand); in nand_to_fsmc()
248 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
250 * This routine initializes timing parameters related to NAND memory access in
259 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; in fsmc_nand_setup()
260 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; in fsmc_nand_setup()
261 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; in fsmc_nand_setup()
262 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; in fsmc_nand_setup()
263 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; in fsmc_nand_setup()
264 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; in fsmc_nand_setup()
266 if (host->nand.options & NAND_BUSWIDTH_16) in fsmc_nand_setup()
269 writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC); in fsmc_nand_setup()
270 writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM); in fsmc_nand_setup()
271 writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB); in fsmc_nand_setup()
278 unsigned long hclk = clk_get_rate(host->clk); in fsmc_calc_timings()
282 if (sdrt->tRC_min < 30000) in fsmc_calc_timings()
283 return -EOPNOTSUPP; in fsmc_calc_timings()
285 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1; in fsmc_calc_timings()
286 if (tims->tar > FSMC_TAR_MASK) in fsmc_calc_timings()
287 tims->tar = FSMC_TAR_MASK; in fsmc_calc_timings()
288 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1; in fsmc_calc_timings()
289 if (tims->tclr > FSMC_TCLR_MASK) in fsmc_calc_timings()
290 tims->tclr = FSMC_TCLR_MASK; in fsmc_calc_timings()
292 thiz = sdrt->tCS_min - sdrt->tWP_min; in fsmc_calc_timings()
293 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn); in fsmc_calc_timings()
295 thold = sdrt->tDH_min; in fsmc_calc_timings()
296 if (thold < sdrt->tCH_min) in fsmc_calc_timings()
297 thold = sdrt->tCH_min; in fsmc_calc_timings()
298 if (thold < sdrt->tCLH_min) in fsmc_calc_timings()
299 thold = sdrt->tCLH_min; in fsmc_calc_timings()
300 if (thold < sdrt->tWH_min) in fsmc_calc_timings()
301 thold = sdrt->tWH_min; in fsmc_calc_timings()
302 if (thold < sdrt->tALH_min) in fsmc_calc_timings()
303 thold = sdrt->tALH_min; in fsmc_calc_timings()
304 if (thold < sdrt->tREH_min) in fsmc_calc_timings()
305 thold = sdrt->tREH_min; in fsmc_calc_timings()
306 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn); in fsmc_calc_timings()
307 if (tims->thold == 0) in fsmc_calc_timings()
308 tims->thold = 1; in fsmc_calc_timings()
309 else if (tims->thold > FSMC_THOLD_MASK) in fsmc_calc_timings()
310 tims->thold = FSMC_THOLD_MASK; in fsmc_calc_timings()
312 twait = max(sdrt->tRP_min, sdrt->tWP_min); in fsmc_calc_timings()
313 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1; in fsmc_calc_timings()
314 if (tims->twait == 0) in fsmc_calc_timings()
315 tims->twait = 1; in fsmc_calc_timings()
316 else if (tims->twait > FSMC_TWAIT_MASK) in fsmc_calc_timings()
317 tims->twait = FSMC_TWAIT_MASK; in fsmc_calc_timings()
319 tset = max(sdrt->tCS_min - sdrt->tWP_min, in fsmc_calc_timings()
320 sdrt->tCEA_max - sdrt->tREA_max); in fsmc_calc_timings()
321 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1; in fsmc_calc_timings()
322 if (tims->tset == 0) in fsmc_calc_timings()
323 tims->tset = 1; in fsmc_calc_timings()
324 else if (tims->tset > FSMC_TSET_MASK) in fsmc_calc_timings()
325 tims->tset = FSMC_TSET_MASK; in fsmc_calc_timings()
330 static int fsmc_setup_interface(struct nand_chip *nand, int csline, in fsmc_setup_interface() argument
333 struct fsmc_nand_data *host = nand_to_fsmc(nand); in fsmc_setup_interface()
355 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
357 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode) in fsmc_enable_hwecc() argument
361 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256, in fsmc_enable_hwecc()
362 host->regs_va + FSMC_PC); in fsmc_enable_hwecc()
363 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN, in fsmc_enable_hwecc()
364 host->regs_va + FSMC_PC); in fsmc_enable_hwecc()
365 writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN, in fsmc_enable_hwecc()
366 host->regs_va + FSMC_PC); in fsmc_enable_hwecc()
370 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
371 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
372 * max of 8-bits)
375 u8 *ecc) in fsmc_read_hwecc_ecc4() argument
382 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY) in fsmc_read_hwecc_ecc4()
389 dev_err(host->dev, "calculate ecc timed out\n"); in fsmc_read_hwecc_ecc4()
390 return -ETIMEDOUT; in fsmc_read_hwecc_ecc4()
393 ecc_tmp = readl_relaxed(host->regs_va + ECC1); in fsmc_read_hwecc_ecc4()
394 ecc[0] = ecc_tmp; in fsmc_read_hwecc_ecc4()
395 ecc[1] = ecc_tmp >> 8; in fsmc_read_hwecc_ecc4()
396 ecc[2] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc4()
397 ecc[3] = ecc_tmp >> 24; in fsmc_read_hwecc_ecc4()
399 ecc_tmp = readl_relaxed(host->regs_va + ECC2); in fsmc_read_hwecc_ecc4()
400 ecc[4] = ecc_tmp; in fsmc_read_hwecc_ecc4()
401 ecc[5] = ecc_tmp >> 8; in fsmc_read_hwecc_ecc4()
402 ecc[6] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc4()
403 ecc[7] = ecc_tmp >> 24; in fsmc_read_hwecc_ecc4()
405 ecc_tmp = readl_relaxed(host->regs_va + ECC3); in fsmc_read_hwecc_ecc4()
406 ecc[8] = ecc_tmp; in fsmc_read_hwecc_ecc4()
407 ecc[9] = ecc_tmp >> 8; in fsmc_read_hwecc_ecc4()
408 ecc[10] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc4()
409 ecc[11] = ecc_tmp >> 24; in fsmc_read_hwecc_ecc4()
411 ecc_tmp = readl_relaxed(host->regs_va + STS); in fsmc_read_hwecc_ecc4()
412 ecc[12] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc4()
418 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
419 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
420 * max of 1-bit)
423 u8 *ecc) in fsmc_read_hwecc_ecc1() argument
428 ecc_tmp = readl_relaxed(host->regs_va + ECC1); in fsmc_read_hwecc_ecc1()
429 ecc[0] = ecc_tmp; in fsmc_read_hwecc_ecc1()
430 ecc[1] = ecc_tmp >> 8; in fsmc_read_hwecc_ecc1()
431 ecc[2] = ecc_tmp >> 16; in fsmc_read_hwecc_ecc1()
454 complete(&host->dma_access_complete); in dma_complete()
470 chan = host->write_dma_chan; in dma_xfer()
472 chan = host->read_dma_chan; in dma_xfer()
474 return -EINVAL; in dma_xfer()
476 dma_dev = chan->device; in dma_xfer()
477 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); in dma_xfer()
481 dma_dst = host->data_pa; in dma_xfer()
483 dma_src = host->data_pa; in dma_xfer()
487 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, in dma_xfer()
490 dev_err(host->dev, "device_prep_dma_memcpy error\n"); in dma_xfer()
491 ret = -EIO; in dma_xfer()
495 tx->callback = dma_complete; in dma_xfer()
496 tx->callback_param = host; in dma_xfer()
497 cookie = tx->tx_submit(tx); in dma_xfer()
501 dev_err(host->dev, "dma_submit_error %d\n", cookie); in dma_xfer()
508 wait_for_completion_timeout(&host->dma_access_complete, in dma_xfer()
512 dev_err(host->dev, "wait_for_completion_timeout\n"); in dma_xfer()
513 ret = -ETIMEDOUT; in dma_xfer()
520 dma_unmap_single(dma_dev->dev, dma_addr, len, direction); in dma_xfer()
526 * fsmc_write_buf - write buffer to chip
527 * @host: FSMC NAND controller
542 writel_relaxed(p[i], host->data_va); in fsmc_write_buf()
545 writeb_relaxed(buf[i], host->data_va); in fsmc_write_buf()
550 * fsmc_read_buf - read chip data into buffer
551 * @host: FSMC NAND controller
565 p[i] = readl_relaxed(host->data_va); in fsmc_read_buf()
568 buf[i] = readb_relaxed(host->data_va); in fsmc_read_buf()
573 * fsmc_read_buf_dma - read chip data into buffer
574 * @host: FSMC NAND controller
585 * fsmc_write_buf_dma - write buffer to chip
586 * @host: FSMC NAND controller
597 * fsmc_exec_op - hook called by the core to execute NAND operations
614 pr_debug("Executing operation [%d instructions]:\n", op->ninstrs); in fsmc_exec_op()
616 for (op_id = 0; op_id < op->ninstrs; op_id++) { in fsmc_exec_op()
617 instr = &op->instrs[op_id]; in fsmc_exec_op()
621 switch (instr->type) { in fsmc_exec_op()
623 writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va); in fsmc_exec_op()
627 for (i = 0; i < instr->ctx.addr.naddrs; i++) in fsmc_exec_op()
628 writeb_relaxed(instr->ctx.addr.addrs[i], in fsmc_exec_op()
629 host->addr_va); in fsmc_exec_op()
633 if (host->mode == USE_DMA_ACCESS) in fsmc_exec_op()
634 fsmc_read_buf_dma(host, instr->ctx.data.buf.in, in fsmc_exec_op()
635 instr->ctx.data.len); in fsmc_exec_op()
637 fsmc_read_buf(host, instr->ctx.data.buf.in, in fsmc_exec_op()
638 instr->ctx.data.len); in fsmc_exec_op()
642 if (host->mode == USE_DMA_ACCESS) in fsmc_exec_op()
644 instr->ctx.data.buf.out, in fsmc_exec_op()
645 instr->ctx.data.len); in fsmc_exec_op()
647 fsmc_write_buf(host, instr->ctx.data.buf.out, in fsmc_exec_op()
648 instr->ctx.data.len); in fsmc_exec_op()
653 instr->ctx.waitrdy.timeout_ms); in fsmc_exec_op()
663 * @chip: nand chip info structure
665 * @oob_required: caller expects OOB data read to chip->oob_poi
668 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
670 * data(512 byte) -> ecc(13 byte)
678 int i, j, s, stat, eccsize = chip->ecc.size; in fsmc_read_page_hwecc()
679 int eccbytes = chip->ecc.bytes; in fsmc_read_page_hwecc()
680 int eccsteps = chip->ecc.steps; in fsmc_read_page_hwecc()
682 u8 *ecc_calc = chip->ecc.calc_buf; in fsmc_read_page_hwecc()
683 u8 *ecc_code = chip->ecc.code_buf; in fsmc_read_page_hwecc()
696 chip->ecc.hwctl(chip, NAND_ECC_READ); in fsmc_read_page_hwecc()
713 * to read at least 13 bytes even in case of 16 bit NAND in fsmc_read_page_hwecc()
716 if (chip->options & NAND_BUSWIDTH_16) in fsmc_read_page_hwecc()
723 memcpy(&ecc_code[i], oob, chip->ecc.bytes); in fsmc_read_page_hwecc()
724 chip->ecc.calculate(chip, p, &ecc_calc[i]); in fsmc_read_page_hwecc()
726 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); in fsmc_read_page_hwecc()
728 mtd->ecc_stats.failed++; in fsmc_read_page_hwecc()
730 mtd->ecc_stats.corrected += stat; in fsmc_read_page_hwecc()
742 * @read_ecc: ecc read from device spare area
743 * @calc_ecc: ecc calculated from read data
756 num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF; in fsmc_bch8_correct_data()
766 * would result in an ecc error because the oob data is also in fsmc_bch8_correct_data()
767 * erased to FF and the calculated ecc for an FF data is not in fsmc_bch8_correct_data()
778 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); in fsmc_bch8_correct_data()
779 int bits_data = count_written_bits(dat, chip->ecc.size, 8); in fsmc_bch8_correct_data()
783 memset(dat, 0xff, chip->ecc.size); in fsmc_bch8_correct_data()
787 return -EBADMSG; in fsmc_bch8_correct_data()
791 * ------------------- calc_ecc[] bit wise -----------|--13 bits--| in fsmc_bch8_correct_data()
792 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| in fsmc_bch8_correct_data()
799 ecc1 = readl_relaxed(host->regs_va + ECC1); in fsmc_bch8_correct_data()
800 ecc2 = readl_relaxed(host->regs_va + ECC2); in fsmc_bch8_correct_data()
801 ecc3 = readl_relaxed(host->regs_va + ECC3); in fsmc_bch8_correct_data()
802 ecc4 = readl_relaxed(host->regs_va + STS); in fsmc_bch8_correct_data()
814 while (num_err--) { in fsmc_bch8_correct_data()
817 if (err_idx[i] < chip->ecc.size * 8) { in fsmc_bch8_correct_data()
829 chan->private = slave; in filter()
835 struct nand_chip *nand) in fsmc_nand_probe_config_dt() argument
837 struct device_node *np = pdev->dev.of_node; in fsmc_nand_probe_config_dt()
841 nand->options = 0; in fsmc_nand_probe_config_dt()
843 if (!of_property_read_u32(np, "bank-width", &val)) { in fsmc_nand_probe_config_dt()
845 nand->options |= NAND_BUSWIDTH_16; in fsmc_nand_probe_config_dt()
847 dev_err(&pdev->dev, "invalid bank-width %u\n", val); in fsmc_nand_probe_config_dt()
848 return -EINVAL; in fsmc_nand_probe_config_dt()
852 if (of_get_property(np, "nand-skip-bbtscan", NULL)) in fsmc_nand_probe_config_dt()
853 nand->options |= NAND_SKIP_BBTSCAN; in fsmc_nand_probe_config_dt()
855 host->dev_timings = devm_kzalloc(&pdev->dev, in fsmc_nand_probe_config_dt()
856 sizeof(*host->dev_timings), in fsmc_nand_probe_config_dt()
858 if (!host->dev_timings) in fsmc_nand_probe_config_dt()
859 return -ENOMEM; in fsmc_nand_probe_config_dt()
861 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings, in fsmc_nand_probe_config_dt()
862 sizeof(*host->dev_timings)); in fsmc_nand_probe_config_dt()
864 host->dev_timings = NULL; in fsmc_nand_probe_config_dt()
866 /* Set default NAND bank to 0 */ in fsmc_nand_probe_config_dt()
867 host->bank = 0; in fsmc_nand_probe_config_dt()
870 dev_err(&pdev->dev, "invalid bank %u\n", val); in fsmc_nand_probe_config_dt()
871 return -EINVAL; in fsmc_nand_probe_config_dt()
873 host->bank = val; in fsmc_nand_probe_config_dt()
878 static int fsmc_nand_attach_chip(struct nand_chip *nand) in fsmc_nand_attach_chip() argument
880 struct mtd_info *mtd = nand_to_mtd(nand); in fsmc_nand_attach_chip()
881 struct fsmc_nand_data *host = nand_to_fsmc(nand); in fsmc_nand_attach_chip()
883 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) in fsmc_nand_attach_chip()
884 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in fsmc_nand_attach_chip()
886 if (!nand->ecc.size) in fsmc_nand_attach_chip()
887 nand->ecc.size = 512; in fsmc_nand_attach_chip()
889 if (AMBA_REV_BITS(host->pid) >= 8) { in fsmc_nand_attach_chip()
890 nand->ecc.read_page = fsmc_read_page_hwecc; in fsmc_nand_attach_chip()
891 nand->ecc.calculate = fsmc_read_hwecc_ecc4; in fsmc_nand_attach_chip()
892 nand->ecc.correct = fsmc_bch8_correct_data; in fsmc_nand_attach_chip()
893 nand->ecc.bytes = 13; in fsmc_nand_attach_chip()
894 nand->ecc.strength = 8; in fsmc_nand_attach_chip()
897 if (AMBA_REV_BITS(host->pid) >= 8) { in fsmc_nand_attach_chip()
898 switch (mtd->oobsize) { in fsmc_nand_attach_chip()
906 dev_warn(host->dev, in fsmc_nand_attach_chip()
908 mtd->oobsize); in fsmc_nand_attach_chip()
909 return -EINVAL; in fsmc_nand_attach_chip()
917 switch (nand->ecc.engine_type) { in fsmc_nand_attach_chip()
919 dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); in fsmc_nand_attach_chip()
920 nand->ecc.calculate = fsmc_read_hwecc_ecc1; in fsmc_nand_attach_chip()
921 nand->ecc.correct = nand_correct_data; in fsmc_nand_attach_chip()
922 nand->ecc.hwctl = fsmc_enable_hwecc; in fsmc_nand_attach_chip()
923 nand->ecc.bytes = 3; in fsmc_nand_attach_chip()
924 nand->ecc.strength = 1; in fsmc_nand_attach_chip()
925 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; in fsmc_nand_attach_chip()
929 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) { in fsmc_nand_attach_chip()
930 dev_info(host->dev, in fsmc_nand_attach_chip()
931 "Using 4-bit SW BCH ECC scheme\n"); in fsmc_nand_attach_chip()
939 dev_err(host->dev, "Unsupported ECC mode!\n"); in fsmc_nand_attach_chip()
940 return -ENOTSUPP; in fsmc_nand_attach_chip()
944 * Don't set layout for BCH4 SW ECC. This will be in fsmc_nand_attach_chip()
947 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { in fsmc_nand_attach_chip()
948 switch (mtd->oobsize) { in fsmc_nand_attach_chip()
956 dev_warn(host->dev, in fsmc_nand_attach_chip()
958 mtd->oobsize); in fsmc_nand_attach_chip()
959 return -EINVAL; in fsmc_nand_attach_chip()
973 * fsmc_nand_disable() - Disables the NAND bank
980 val = readl(host->regs_va + FSMC_PC); in fsmc_nand_disable()
982 writel(val, host->regs_va + FSMC_PC); in fsmc_nand_disable()
986 * fsmc_nand_probe - Probe function
993 struct nand_chip *nand; in fsmc_nand_probe() local
1002 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); in fsmc_nand_probe()
1004 return -ENOMEM; in fsmc_nand_probe()
1006 nand = &host->nand; in fsmc_nand_probe()
1008 ret = fsmc_nand_probe_config_dt(pdev, host, nand); in fsmc_nand_probe()
1013 host->data_va = devm_ioremap_resource(&pdev->dev, res); in fsmc_nand_probe()
1014 if (IS_ERR(host->data_va)) in fsmc_nand_probe()
1015 return PTR_ERR(host->data_va); in fsmc_nand_probe()
1017 host->data_pa = (dma_addr_t)res->start; in fsmc_nand_probe()
1020 host->addr_va = devm_ioremap_resource(&pdev->dev, res); in fsmc_nand_probe()
1021 if (IS_ERR(host->addr_va)) in fsmc_nand_probe()
1022 return PTR_ERR(host->addr_va); in fsmc_nand_probe()
1025 host->cmd_va = devm_ioremap_resource(&pdev->dev, res); in fsmc_nand_probe()
1026 if (IS_ERR(host->cmd_va)) in fsmc_nand_probe()
1027 return PTR_ERR(host->cmd_va); in fsmc_nand_probe()
1030 base = devm_ioremap_resource(&pdev->dev, res); in fsmc_nand_probe()
1034 host->regs_va = base + FSMC_NOR_REG_SIZE + in fsmc_nand_probe()
1035 (host->bank * FSMC_NAND_BANK_SZ); in fsmc_nand_probe()
1037 host->clk = devm_clk_get(&pdev->dev, NULL); in fsmc_nand_probe()
1038 if (IS_ERR(host->clk)) { in fsmc_nand_probe()
1039 dev_err(&pdev->dev, "failed to fetch block clock\n"); in fsmc_nand_probe()
1040 return PTR_ERR(host->clk); in fsmc_nand_probe()
1043 ret = clk_prepare_enable(host->clk); in fsmc_nand_probe()
1052 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & in fsmc_nand_probe()
1055 host->pid = pid; in fsmc_nand_probe()
1057 dev_info(&pdev->dev, in fsmc_nand_probe()
1062 host->dev = &pdev->dev; in fsmc_nand_probe()
1064 if (host->mode == USE_DMA_ACCESS) in fsmc_nand_probe()
1065 init_completion(&host->dma_access_complete); in fsmc_nand_probe()
1068 mtd = nand_to_mtd(&host->nand); in fsmc_nand_probe()
1069 nand_set_flash_node(nand, pdev->dev.of_node); in fsmc_nand_probe()
1071 mtd->dev.parent = &pdev->dev; in fsmc_nand_probe()
1073 nand->badblockbits = 7; in fsmc_nand_probe()
1075 if (host->mode == USE_DMA_ACCESS) { in fsmc_nand_probe()
1078 host->read_dma_chan = dma_request_channel(mask, filter, NULL); in fsmc_nand_probe()
1079 if (!host->read_dma_chan) { in fsmc_nand_probe()
1080 dev_err(&pdev->dev, "Unable to get read dma channel\n"); in fsmc_nand_probe()
1083 host->write_dma_chan = dma_request_channel(mask, filter, NULL); in fsmc_nand_probe()
1084 if (!host->write_dma_chan) { in fsmc_nand_probe()
1085 dev_err(&pdev->dev, "Unable to get write dma channel\n"); in fsmc_nand_probe()
1090 if (host->dev_timings) { in fsmc_nand_probe()
1091 fsmc_nand_setup(host, host->dev_timings); in fsmc_nand_probe()
1092 nand->options |= NAND_KEEP_TIMINGS; in fsmc_nand_probe()
1095 nand_controller_init(&host->base); in fsmc_nand_probe()
1096 host->base.ops = &fsmc_nand_controller_ops; in fsmc_nand_probe()
1097 nand->controller = &host->base; in fsmc_nand_probe()
1102 ret = nand_scan(nand, 1); in fsmc_nand_probe()
1106 mtd->name = "nand"; in fsmc_nand_probe()
1112 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); in fsmc_nand_probe()
1117 nand_cleanup(nand); in fsmc_nand_probe()
1119 if (host->mode == USE_DMA_ACCESS) in fsmc_nand_probe()
1120 dma_release_channel(host->write_dma_chan); in fsmc_nand_probe()
1122 if (host->mode == USE_DMA_ACCESS) in fsmc_nand_probe()
1123 dma_release_channel(host->read_dma_chan); in fsmc_nand_probe()
1126 clk_disable_unprepare(host->clk); in fsmc_nand_probe()
1139 struct nand_chip *chip = &host->nand; in fsmc_nand_remove()
1147 if (host->mode == USE_DMA_ACCESS) { in fsmc_nand_remove()
1148 dma_release_channel(host->write_dma_chan); in fsmc_nand_remove()
1149 dma_release_channel(host->read_dma_chan); in fsmc_nand_remove()
1151 clk_disable_unprepare(host->clk); in fsmc_nand_remove()
1163 clk_disable_unprepare(host->clk); in fsmc_nand_suspend()
1173 clk_prepare_enable(host->clk); in fsmc_nand_resume()
1174 if (host->dev_timings) in fsmc_nand_resume()
1175 fsmc_nand_setup(host, host->dev_timings); in fsmc_nand_resume()
1176 nand_reset(&host->nand, 0); in fsmc_nand_resume()
1186 { .compatible = "st,spear600-fsmc-nand" },
1187 { .compatible = "stericsson,fsmc-nand" },
1195 .name = "fsmc-nand",
1205 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");