11  *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12  *   where 0-3 reflects the chip select for NAND.
30 #define MSR_DIVIL_GLD_CAP	0x51400000	/* DIVIL capabilitiies */
31 #define CAP_CS5535		0x2df000ULL
32 #define CAP_CS5536		0x5df500ULL
35 #define MSR_NANDF_DATA		0x5140001b	/* NAND Flash Data Timing MSR */
36 #define MSR_NANDF_CTL		0x5140001c	/* NAND Flash Control Timing */
37 #define MSR_NANDF_RSVD		0x5140001d	/* Reserved */
40 #define MSR_DIVIL_LBAR_FLSH0	0x51400010	/* Flash Chip Select 0 */
41 #define MSR_DIVIL_LBAR_FLSH1	0x51400011	/* Flash Chip Select 1 */
42 #define MSR_DIVIL_LBAR_FLSH2	0x51400012	/* Flash Chip Select 2 */
43 #define MSR_DIVIL_LBAR_FLSH3	0x51400013	/* Flash Chip Select 3 */
52 #define MSR_DIVIL_BALL_OPTS	0x51400015
53 #define PIN_OPT_IDE		(1<<0)	/* 0 for flash, 1 for IDE */
56 #define MM_NAND_DATA		0x00	/* 0 to 0x7ff, in fact */
57 #define MM_NAND_CTL		0x800	/* Any even address 0x800-0x80e */
58 #define MM_NAND_IO		0x801	/* Any odd address 0x801-0x80f */
59 #define MM_NAND_STS		0x810
60 #define MM_NAND_ECC_LSB		0x811
61 #define MM_NAND_ECC_MSB		0x812
62 #define MM_NAND_ECC_COL		0x813
63 #define MM_NAND_LAC		0x814
64 #define MM_NAND_ECC_CTL		0x815
67 #define IO_NAND_DATA		0x00	/* 0 to 3, in fact */
68 #define IO_NAND_CTL		0x04
69 #define IO_NAND_IO		0x05
70 #define IO_NAND_STS		0x06
71 #define IO_NAND_ECC_CTL		0x08
72 #define IO_NAND_ECC_LSB		0x09
73 #define IO_NAND_ECC_MSB		0x0a
74 #define IO_NAND_ECC_COL		0x0b
75 #define IO_NAND_LAC		0x0c
81 #define CS_NAND_CTL_CE		(1<<0)	/* Keep low; 1 to reset */
86 #define CS_NAND_DIST_ST		(1<<0)
90 #define CS_NAND_ECC_ENECC	(1<<0)
118 	return 0;  in cs553x_write_ctrl_byte()
124 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_data_in()
125 	while (unlikely(len > 0x800)) {  in cs553x_data_in()
126 		memcpy_fromio(buf, cs553x->mmio, 0x800);  in cs553x_data_in()
127 		buf += 0x800;  in cs553x_data_in()
128 		len -= 0x800;  in cs553x_data_in()
136 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_data_out()
137 	while (unlikely(len > 0x800)) {  in cs553x_data_out()
138 		memcpy_toio(cs553x->mmio, buf, 0x800);  in cs553x_data_out()
139 		buf += 0x800;  in cs553x_data_out()
140 		len -= 0x800;  in cs553x_data_out()
160 	int ret = 0;  in cs553x_exec_instr()
169 		for (i = 0; i < instr->ctx.addr.naddrs; i++) {  in cs553x_exec_instr()
210 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_exec_op()
211 	for (i = 0; i < op->ninstrs; i++) {  in cs553x_exec_op()
227 	writeb(0x07, cs553x->mmio + MM_NAND_ECC_CTL);  in cs_enable_hwecc()
239 	ecc_code[0] = ecc >> 16;  in cs_calculate_ecc()
241 	return 0;  in cs_calculate_ecc()
249 		return 0;  in cs553x_attach_chip()
258 	return 0;  in cs553x_attach_chip()
269 	int err = 0;  in cs553x_init_one()
273 	pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",  in cs553x_init_one()
300 		pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);  in cs553x_init_one()
346 	return 0;  in is_geode()
361 	val &= ~0xFFULL;  in cs553x_init()
372 	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {  in cs553x_init()
376 			err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);  in cs553x_init()
381 	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {  in cs553x_init()
385 					    NULL, 0);  in cs553x_init()
386 			err = 0;  in cs553x_init()
399 	for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {  in cs553x_cleanup()