Lines Matching +full:nand +full:- +full:no +full:- +full:ecc +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
16 #include <linux/dma-mapping.h>
87 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
92 /* 512B flash cache in the NAND controller HW */
233 /* List of NAND hosts (one for each chip-select) */
236 /* EDU info, per-transaction */
254 /* in-memory cache of the FLASH_CACHE, used only for some commands */
260 const u8 *cs_offsets; /* within each chip-select */
270 /* for low-power standby/resume only */
290 /* use for low-power standby/resume only */
321 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
335 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
337 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
341 /* BRCMNAND v2.1-v2.2 */
371 /* BRCMNAND v3.3-v4.0 */
431 /* BRCMNAND v6.0 - v7.1 */
529 /* Per chip-select offsets for v7.1 */
538 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
547 /* Per chip-select offset for <= v5.0 on CS0 only */
557 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
572 /* Only for pre-v7.1 (with no CFG_EXT register) */
594 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
600 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
613 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
616 if (ctrl->nand_version < 0x0201) { in brcmnand_revision_init()
617 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
618 ctrl->nand_version); in brcmnand_revision_init()
619 return -ENODEV; in brcmnand_revision_init()
623 if (ctrl->nand_version >= 0x0702) in brcmnand_revision_init()
624 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
625 else if (ctrl->nand_version == 0x0701) in brcmnand_revision_init()
626 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
627 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
628 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
629 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
630 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
631 else if (ctrl->nand_version >= 0x0303) in brcmnand_revision_init()
632 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
633 else if (ctrl->nand_version >= 0x0201) in brcmnand_revision_init()
634 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
636 /* Chip-select stride */ in brcmnand_revision_init()
637 if (ctrl->nand_version >= 0x0701) in brcmnand_revision_init()
638 ctrl->reg_spacing = 0x14; in brcmnand_revision_init()
640 ctrl->reg_spacing = 0x10; in brcmnand_revision_init()
642 /* Per chip-select registers */ in brcmnand_revision_init()
643 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
644 ctrl->cs_offsets = brcmnand_cs_offsets_v71; in brcmnand_revision_init()
646 ctrl->cs_offsets = brcmnand_cs_offsets; in brcmnand_revision_init()
648 /* v3.3-5.0 have a different CS0 offset layout */ in brcmnand_revision_init()
649 if (ctrl->nand_version >= 0x0303 && in brcmnand_revision_init()
650 ctrl->nand_version <= 0x0500) in brcmnand_revision_init()
651 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; in brcmnand_revision_init()
655 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
656 /* >= v7.1 use nice power-of-2 values! */ in brcmnand_revision_init()
657 ctrl->max_page_size = 16 * 1024; in brcmnand_revision_init()
658 ctrl->max_block_size = 2 * 1024 * 1024; in brcmnand_revision_init()
660 if (ctrl->nand_version >= 0x0304) in brcmnand_revision_init()
661 ctrl->page_sizes = page_sizes_v3_4; in brcmnand_revision_init()
662 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
663 ctrl->page_sizes = page_sizes_v2_2; in brcmnand_revision_init()
665 ctrl->page_sizes = page_sizes_v2_1; in brcmnand_revision_init()
667 if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
668 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; in brcmnand_revision_init()
670 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; in brcmnand_revision_init()
672 if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
673 ctrl->block_sizes = block_sizes_v6; in brcmnand_revision_init()
674 else if (ctrl->nand_version >= 0x0400) in brcmnand_revision_init()
675 ctrl->block_sizes = block_sizes_v4; in brcmnand_revision_init()
676 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
677 ctrl->block_sizes = block_sizes_v2_2; in brcmnand_revision_init()
679 ctrl->block_sizes = block_sizes_v2_1; in brcmnand_revision_init()
681 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
682 if (ctrl->nand_version < 0x0202) in brcmnand_revision_init()
683 ctrl->max_page_size = 2048; in brcmnand_revision_init()
685 ctrl->max_page_size = 4096; in brcmnand_revision_init()
686 ctrl->max_block_size = 512 * 1024; in brcmnand_revision_init()
691 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
692 ctrl->max_oob = 128; in brcmnand_revision_init()
693 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
694 ctrl->max_oob = 64; in brcmnand_revision_init()
695 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
696 ctrl->max_oob = 32; in brcmnand_revision_init()
698 ctrl->max_oob = 16; in brcmnand_revision_init()
701 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) in brcmnand_revision_init()
702 ctrl->features |= BRCMNAND_HAS_PREFETCH; in brcmnand_revision_init()
708 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
709 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; in brcmnand_revision_init()
711 if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
712 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; in brcmnand_revision_init()
714 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
715 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
716 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) in brcmnand_revision_init()
717 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
725 if (ctrl->nand_version >= 0x0703) in brcmnand_flash_dma_revision_init()
726 ctrl->flash_dma_offsets = flash_dma_regs_v4; in brcmnand_flash_dma_revision_init()
727 else if (ctrl->nand_version == 0x0602) in brcmnand_flash_dma_revision_init()
728 ctrl->flash_dma_offsets = flash_dma_regs_v0; in brcmnand_flash_dma_revision_init()
730 ctrl->flash_dma_offsets = flash_dma_regs_v1; in brcmnand_flash_dma_revision_init()
736 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
747 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
766 return __raw_readl(ctrl->nand_fc + word * 4); in brcmnand_read_fc()
772 __raw_writel(val, ctrl->nand_fc + word * 4); in brcmnand_write_fc()
778 u16 offs = ctrl->edu_offsets[reg]; in edu_writel()
780 brcmnand_writel(val, ctrl->edu_base + offs); in edu_writel()
786 u16 offs = ctrl->edu_offsets[reg]; in edu_readl()
788 return brcmnand_readl(ctrl->edu_base + offs); in edu_readl()
829 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr()
832 (host->cs << 16) | ((addr >> 32) & 0xffff)); in brcmnand_set_cmd_addr()
842 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
843 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()
846 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
847 cs_offs = ctrl->cs0_offsets[reg]; in brcmnand_cs_offset()
849 cs_offs = ctrl->cs_offsets[reg]; in brcmnand_cs_offset()
852 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
854 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
859 if (ctrl->nand_version < 0x0600) in brcmnand_count_corrected()
866 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh()
869 int cs = host->cs; in brcmnand_wr_corr_thresh()
871 if (!ctrl->reg_offsets[reg]) in brcmnand_wr_corr_thresh()
874 if (ctrl->nand_version == 0x0702) in brcmnand_wr_corr_thresh()
876 else if (ctrl->nand_version >= 0x0600) in brcmnand_wr_corr_thresh()
878 else if (ctrl->nand_version >= 0x0500) in brcmnand_wr_corr_thresh()
883 if (ctrl->nand_version >= 0x0702) { in brcmnand_wr_corr_thresh()
887 } else if (ctrl->nand_version >= 0x0600) { in brcmnand_wr_corr_thresh()
892 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); in brcmnand_wr_corr_thresh()
897 if (ctrl->nand_version < 0x0602) in brcmnand_cmd_shift()
903 * NAND ACC CONTROL bitfield
928 if (ctrl->nand_version == 0x0702) in brcmnand_spare_area_mask()
930 else if (ctrl->nand_version >= 0x0600) in brcmnand_spare_area_mask()
932 else if (ctrl->nand_version >= 0x0303) in brcmnand_spare_area_mask()
943 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; in brcmnand_ecc_level_mask()
947 /* v7.2 includes additional ECC levels */ in brcmnand_ecc_level_mask()
948 if (ctrl->nand_version >= 0x0702) in brcmnand_ecc_level_mask()
956 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled()
957 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_set_ecc_enabled()
962 acc_control |= ecc_flags; /* enable RD/WR ECC */ in brcmnand_set_ecc_enabled()
963 acc_control |= host->hwcfg.ecc_level in brcmnand_set_ecc_enabled()
966 acc_control &= ~ecc_flags; /* disable RD/WR ECC */ in brcmnand_set_ecc_enabled()
975 if (ctrl->nand_version >= 0x0702) in brcmnand_sector_1k_shift()
977 else if (ctrl->nand_version >= 0x0600) in brcmnand_sector_1k_shift()
979 else if (ctrl->nand_version >= 0x0500) in brcmnand_sector_1k_shift()
982 return -1; in brcmnand_sector_1k_shift()
987 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k()
989 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_sector_size_1k()
1000 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_sector_size_1k()
1002 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_sector_size_1k()
1043 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", in bcmnand_ctrl_poll_status()
1046 return -ETIMEDOUT; in bcmnand_ctrl_poll_status()
1062 return ctrl->flash_dma_base; in has_flash_dma()
1067 return ctrl->edu_base; in has_edu()
1077 if (ctrl->pio_poll_mode) in disable_ctrl_irqs()
1081 ctrl->flash_dma_base = NULL; in disable_ctrl_irqs()
1082 disable_irq(ctrl->dma_irq); in disable_ctrl_irqs()
1085 disable_irq(ctrl->irq); in disable_ctrl_irqs()
1086 ctrl->pio_poll_mode = true; in disable_ctrl_irqs()
1098 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_writel()
1100 brcmnand_writel(val, ctrl->flash_dma_base + offs); in flash_dma_writel()
1106 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_readl()
1108 return brcmnand_readl(ctrl->flash_dma_base + offs); in flash_dma_readl()
1111 /* Low-level operation types: command, address, write, or read */
1126 if (ctrl->nand_version <= 0x0701) in is_hamming_ecc()
1127 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && in is_hamming_ecc()
1128 cfg->ecc_level == 15; in is_hamming_ecc()
1130 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && in is_hamming_ecc()
1131 cfg->ecc_level == 15) || in is_hamming_ecc()
1132 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); in is_hamming_ecc()
1136 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
1138 * Returns -ERRCODE on failure.
1145 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_ecc()
1146 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_ecc()
1147 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_ecc()
1150 return -ERANGE; in brcmnand_hamming_ooblayout_ecc()
1152 oobregion->offset = (section * sas) + 6; in brcmnand_hamming_ooblayout_ecc()
1153 oobregion->length = 3; in brcmnand_hamming_ooblayout_ecc()
1163 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_free()
1164 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_free()
1165 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_free()
1169 return -ERANGE; in brcmnand_hamming_ooblayout_free()
1176 oobregion->offset = ((section - 1) * sas) + 9; in brcmnand_hamming_ooblayout_free()
1178 if (cfg->page_size > 512) { in brcmnand_hamming_ooblayout_free()
1179 /* Large page NAND uses first 2 bytes for BBI */ in brcmnand_hamming_ooblayout_free()
1180 oobregion->offset = 2; in brcmnand_hamming_ooblayout_free()
1182 /* Small page NAND uses last byte before ECC for BBI */ in brcmnand_hamming_ooblayout_free()
1183 oobregion->offset = 0; in brcmnand_hamming_ooblayout_free()
1184 next--; in brcmnand_hamming_ooblayout_free()
1188 oobregion->length = next - oobregion->offset; in brcmnand_hamming_ooblayout_free()
1194 .ecc = brcmnand_hamming_ooblayout_ecc,
1203 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_ecc()
1204 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_ecc()
1205 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_ecc()
1208 return -ERANGE; in brcmnand_bch_ooblayout_ecc()
1210 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1211 oobregion->length = chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1221 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_lp()
1222 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_lp()
1223 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_free_lp()
1226 return -ERANGE; in brcmnand_bch_ooblayout_free_lp()
1228 if (sas <= chip->ecc.bytes) in brcmnand_bch_ooblayout_free_lp()
1231 oobregion->offset = section * sas; in brcmnand_bch_ooblayout_free_lp()
1232 oobregion->length = sas - chip->ecc.bytes; in brcmnand_bch_ooblayout_free_lp()
1235 oobregion->offset++; in brcmnand_bch_ooblayout_free_lp()
1236 oobregion->length--; in brcmnand_bch_ooblayout_free_lp()
1247 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_sp()
1248 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_sp()
1250 if (section > 1 || sas - chip->ecc.bytes < 6 || in brcmnand_bch_ooblayout_free_sp()
1251 (section && sas - chip->ecc.bytes == 6)) in brcmnand_bch_ooblayout_free_sp()
1252 return -ERANGE; in brcmnand_bch_ooblayout_free_sp()
1255 oobregion->offset = 0; in brcmnand_bch_ooblayout_free_sp()
1256 oobregion->length = 5; in brcmnand_bch_ooblayout_free_sp()
1258 oobregion->offset = 6; in brcmnand_bch_ooblayout_free_sp()
1259 oobregion->length = sas - chip->ecc.bytes - 6; in brcmnand_bch_ooblayout_free_sp()
1266 .ecc = brcmnand_bch_ooblayout_ecc,
1271 .ecc = brcmnand_bch_ooblayout_ecc,
1277 struct brcmnand_cfg *p = &host->hwcfg; in brcmstb_choose_ecc_layout()
1278 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmstb_choose_ecc_layout()
1279 struct nand_ecc_ctrl *ecc = &host->chip.ecc; in brcmstb_choose_ecc_layout() local
1280 unsigned int ecc_level = p->ecc_level; in brcmstb_choose_ecc_layout()
1281 int sas = p->spare_area_size << p->sector_size_1k; in brcmstb_choose_ecc_layout()
1282 int sectors = p->page_size / (512 << p->sector_size_1k); in brcmstb_choose_ecc_layout()
1284 if (p->sector_size_1k) in brcmstb_choose_ecc_layout()
1287 if (is_hamming_ecc(host->ctrl, p)) { in brcmstb_choose_ecc_layout()
1288 ecc->bytes = 3 * sectors; in brcmstb_choose_ecc_layout()
1299 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); in brcmstb_choose_ecc_layout()
1300 if (p->page_size == 512) in brcmstb_choose_ecc_layout()
1305 if (ecc->bytes >= sas) { in brcmstb_choose_ecc_layout()
1306 dev_err(&host->pdev->dev, in brcmstb_choose_ecc_layout()
1307 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", in brcmstb_choose_ecc_layout()
1308 ecc->bytes, sas); in brcmstb_choose_ecc_layout()
1309 return -EINVAL; in brcmstb_choose_ecc_layout()
1319 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wp()
1321 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { in brcmnand_wp()
1322 static int old_wp = -1; in brcmnand_wp()
1326 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); in brcmnand_wp()
1353 dev_err_ratelimited(&host->pdev->dev, in brcmnand_wp()
1354 "nand #WP expected %s\n", in brcmnand_wp()
1364 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()
1365 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; in oob_reg_read()
1367 if (offs >= ctrl->max_oob) in oob_reg_read()
1371 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_read()
1375 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); in oob_reg_read()
1383 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; in oob_reg_write()
1384 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; in oob_reg_write()
1386 if (offs >= ctrl->max_oob) in oob_reg_write()
1390 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_write()
1398 * read_oob_from_regs - read data from OOB registers
1399 * @ctrl: NAND controller
1400 * @i: sub-page sector index
1413 tbytes = max(0, tbytes - (int)ctrl->max_oob); in read_oob_from_regs()
1414 tbytes = min_t(int, tbytes, ctrl->max_oob); in read_oob_from_regs()
1422 * write_oob_to_regs - write data to OOB registers
1423 * @i: sub-page sector index
1436 tbytes = max(0, tbytes - (int)ctrl->max_oob); in write_oob_to_regs()
1437 tbytes = min_t(int, tbytes, ctrl->max_oob); in write_oob_to_regs()
1465 if (ctrl->edu_count) { in brcmnand_edu_irq()
1466 ctrl->edu_count--; in brcmnand_edu_irq()
1473 if (ctrl->edu_count) { in brcmnand_edu_irq()
1474 ctrl->edu_dram_addr += FC_BYTES; in brcmnand_edu_irq()
1475 ctrl->edu_ext_addr += FC_BYTES; in brcmnand_edu_irq()
1477 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_irq()
1479 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_irq()
1483 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_irq()
1489 complete(&ctrl->edu_done); in brcmnand_edu_irq()
1499 if (ctrl->dma_pending) in brcmnand_ctlrdy_irq()
1503 if (ctrl->edu_pending) { in brcmnand_ctlrdy_irq()
1504 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) in brcmnand_ctlrdy_irq()
1508 /* no registered edu irq, call handler */ in brcmnand_ctlrdy_irq()
1512 complete(&ctrl->done); in brcmnand_ctlrdy_irq()
1516 /* Handle SoC-specific interrupt hardware */
1521 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
1531 complete(&ctrl->dma_done); in brcmnand_dma_irq()
1538 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_send_cmd()
1544 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); in brcmnand_send_cmd()
1546 BUG_ON(ctrl->cmd_pending != 0); in brcmnand_send_cmd()
1547 ctrl->cmd_pending = cmd; in brcmnand_send_cmd()
1558 * NAND MTD API: read/program/erase
1570 struct brcmnand_controller *ctrl = host->ctrl; in brcmstb_nand_wait_for_completion()
1575 if (mtd->oops_panic_write) { in brcmstb_nand_wait_for_completion()
1585 sts = wait_for_completion_timeout(&ctrl->done, timeo); in brcmstb_nand_wait_for_completion()
1595 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_waitfunc()
1598 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); in brcmnand_waitfunc()
1599 if (ctrl->cmd_pending) in brcmnand_waitfunc()
1606 dev_err_ratelimited(ctrl->dev, in brcmnand_waitfunc()
1608 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", in brcmnand_waitfunc()
1611 ctrl->cmd_pending = 0; in brcmnand_waitfunc()
1630 struct nand_chip *chip = &host->chip; in brcmnand_low_level_op()
1631 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_low_level_op()
1656 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); in brcmnand_low_level_op()
1670 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_cmdfunc()
1671 u64 addr = (u64)page_addr << chip->page_shift; in brcmnand_cmdfunc()
1677 /* Avoid propagating a negative, don't-care address */ in brcmnand_cmdfunc()
1681 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, in brcmnand_cmdfunc()
1684 host->last_cmd = command; in brcmnand_cmdfunc()
1685 host->last_byte = 0; in brcmnand_cmdfunc()
1686 host->last_addr = addr; in brcmnand_cmdfunc()
1715 addr &= ~((u64)(FC_BYTES - 1)); in brcmnand_cmdfunc()
1721 host->hwcfg.sector_size_1k = in brcmnand_cmdfunc()
1737 /* Copy flash cache word-wise */ in brcmnand_cmdfunc()
1738 u32 *flash_cache = (u32 *)ctrl->flash_cache; in brcmnand_cmdfunc()
1741 brcmnand_soc_data_bus_prepare(ctrl->soc, true); in brcmnand_cmdfunc()
1754 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); in brcmnand_cmdfunc()
1757 if (host->hwcfg.sector_size_1k) in brcmnand_cmdfunc()
1759 host->hwcfg.sector_size_1k); in brcmnand_cmdfunc()
1762 /* Re-enable protection is necessary only after erase */ in brcmnand_cmdfunc()
1770 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_byte()
1774 switch (host->last_cmd) { in brcmnand_read_byte()
1776 if (host->last_byte < 4) in brcmnand_read_byte()
1778 (24 - (host->last_byte << 3)); in brcmnand_read_byte()
1779 else if (host->last_byte < 8) in brcmnand_read_byte()
1781 (56 - (host->last_byte << 3)); in brcmnand_read_byte()
1785 ret = oob_reg_read(ctrl, host->last_byte); in brcmnand_read_byte()
1797 addr = host->last_addr + host->last_byte; in brcmnand_read_byte()
1798 offs = addr & (FC_BYTES - 1); in brcmnand_read_byte()
1801 if (host->last_byte > 0 && offs == 0) in brcmnand_read_byte()
1804 ret = ctrl->flash_cache[offs]; in brcmnand_read_byte()
1807 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { in brcmnand_read_byte()
1810 bool last = host->last_byte == in brcmnand_read_byte()
1811 ONFI_SUBFEATURE_PARAM_LEN - 1; in brcmnand_read_byte()
1817 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); in brcmnand_read_byte()
1818 host->last_byte++; in brcmnand_read_byte()
1837 switch (host->last_cmd) { in brcmnand_write_buf()
1850 * Kick EDU engine
1855 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_edu_trans()
1863 pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_edu_trans()
1864 if (dma_mapping_error(ctrl->dev, pa)) { in brcmnand_edu_trans()
1865 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); in brcmnand_edu_trans()
1866 return -ENOMEM; in brcmnand_edu_trans()
1869 ctrl->edu_pending = true; in brcmnand_edu_trans()
1870 ctrl->edu_dram_addr = pa; in brcmnand_edu_trans()
1871 ctrl->edu_ext_addr = addr; in brcmnand_edu_trans()
1872 ctrl->edu_cmd = edu_cmd; in brcmnand_edu_trans()
1873 ctrl->edu_count = trans; in brcmnand_edu_trans()
1875 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_trans()
1877 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_trans()
1882 /* Start edu engine */ in brcmnand_edu_trans()
1884 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_trans()
1887 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { in brcmnand_edu_trans()
1888 dev_err(ctrl->dev, in brcmnand_edu_trans()
1894 dma_unmap_single(ctrl->dev, pa, len, dir); in brcmnand_edu_trans()
1896 /* for program page check NAND status */ in brcmnand_edu_trans()
1900 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_edu_trans()
1902 ret = -EIO; in brcmnand_edu_trans()
1907 dev_warn(ctrl->dev, "EDU still active: %#x\n", in brcmnand_edu_trans()
1911 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", in brcmnand_edu_trans()
1913 ret = -EIO; in brcmnand_edu_trans()
1916 ctrl->edu_pending = false; in brcmnand_edu_trans()
1925 * check for ECC errors here, subpage ECC errors are in brcmnand_edu_trans()
1926 * retained in ECC error address register in brcmnand_edu_trans()
1932 ret = -EUCLEAN; in brcmnand_edu_trans()
1934 ret = -EBADMSG; in brcmnand_edu_trans()
1943 * - Is this descriptor the beginning or end of a linked list?
1944 * - What is the (DMA) address of the next descriptor in the linked list?
1954 desc->next_desc = lower_32_bits(next_desc); in brcmnand_fill_dma_desc()
1955 desc->next_desc_ext = upper_32_bits(next_desc); in brcmnand_fill_dma_desc()
1956 desc->cmd_irq = (dma_cmd << 24) | in brcmnand_fill_dma_desc()
1960 desc->cmd_irq |= 0x01 << 12; in brcmnand_fill_dma_desc()
1962 desc->dram_addr = lower_32_bits(buf); in brcmnand_fill_dma_desc()
1963 desc->dram_addr_ext = upper_32_bits(buf); in brcmnand_fill_dma_desc()
1964 desc->tfr_len = len; in brcmnand_fill_dma_desc()
1965 desc->total_len = len; in brcmnand_fill_dma_desc()
1966 desc->flash_addr = lower_32_bits(addr); in brcmnand_fill_dma_desc()
1967 desc->flash_addr_ext = upper_32_bits(addr); in brcmnand_fill_dma_desc()
1968 desc->cs = host->cs; in brcmnand_fill_dma_desc()
1969 desc->status_valid = 0x01; in brcmnand_fill_dma_desc()
1974 * Kick the FLASH_DMA engine, with a given DMA descriptor
1978 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_run()
1983 if (ctrl->nand_version > 0x0602) { in brcmnand_dma_run()
1989 /* Start FLASH_DMA engine */ in brcmnand_dma_run()
1990 ctrl->dma_pending = true; in brcmnand_dma_run()
1994 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { in brcmnand_dma_run()
1995 dev_err(ctrl->dev, in brcmnand_dma_run()
2000 ctrl->dma_pending = false; in brcmnand_dma_run()
2007 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_trans()
2011 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_dma_trans()
2012 if (dma_mapping_error(ctrl->dev, buf_pa)) { in brcmnand_dma_trans()
2013 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); in brcmnand_dma_trans()
2014 return -ENOMEM; in brcmnand_dma_trans()
2017 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, in brcmnand_dma_trans()
2020 brcmnand_dma_run(host, ctrl->dma_pa); in brcmnand_dma_trans()
2022 dma_unmap_single(ctrl->dev, buf_pa, len, dir); in brcmnand_dma_trans()
2024 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) in brcmnand_dma_trans()
2025 return -EBADMSG; in brcmnand_dma_trans()
2026 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) in brcmnand_dma_trans()
2027 return -EUCLEAN; in brcmnand_dma_trans()
2040 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_by_pio()
2047 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ in brcmnand_read_by_pio()
2052 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_read_by_pio()
2057 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_read_by_pio()
2062 mtd->oobsize / trans, in brcmnand_read_by_pio()
2063 host->hwcfg.sector_size_1k); in brcmnand_read_by_pio()
2069 ret = -EBADMSG; in brcmnand_read_by_pio()
2076 ret = -EUCLEAN; in brcmnand_read_by_pio()
2084 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC
2087 * Because the HW ECC signals an ECC error if an erase paged has even a single
2088 * bitflip, we must check each ECC error to see if it is actually an erased
2091 * On a real error, return a negative error code (-EBADMSG for ECC error), and
2094 * bitflips-per-ECC-sector to the caller.
2100 struct mtd_oob_region ecc; in brcmstb_nand_verify_erased_page() local
2103 int page = addr >> chip->page_shift; in brcmstb_nand_verify_erased_page()
2111 /* read without ecc for verification */ in brcmstb_nand_verify_erased_page()
2112 ret = chip->ecc.read_page_raw(chip, buf, true, page); in brcmstb_nand_verify_erased_page()
2116 for (i = 0; i < chip->ecc.steps; i++) { in brcmstb_nand_verify_erased_page()
2117 ecc_chunk = buf + chip->ecc.size * i; in brcmstb_nand_verify_erased_page()
2119 mtd_ooblayout_ecc(mtd, i, &ecc); in brcmstb_nand_verify_erased_page()
2120 ecc_bytes = chip->oob_poi + ecc.offset; in brcmstb_nand_verify_erased_page()
2122 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, in brcmstb_nand_verify_erased_page()
2123 ecc_bytes, ecc.length, in brcmstb_nand_verify_erased_page()
2125 chip->ecc.strength); in brcmstb_nand_verify_erased_page()
2139 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read()
2145 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); in brcmnand_read()
2150 if (ctrl->dma_trans && !oob && flash_dma_buf_ok(buf)) { in brcmnand_read()
2151 err = ctrl->dma_trans(host, addr, buf, in brcmnand_read()
2159 return -EIO; in brcmnand_read()
2167 memset(oob, 0x99, mtd->oobsize); in brcmnand_read()
2177 * the DMA engine captures this error following DMA read in brcmnand_read()
2182 if ((ctrl->nand_version == 0x0700) || in brcmnand_read()
2183 (ctrl->nand_version == 0x0701)) { in brcmnand_read()
2194 if (ctrl->nand_version < 0x0702) { in brcmnand_read()
2202 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", in brcmnand_read()
2204 mtd->ecc_stats.failed++; in brcmnand_read()
2205 /* NAND layer expects zero on ECC errors */ in brcmnand_read()
2217 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", in brcmnand_read()
2219 mtd->ecc_stats.corrected += corrected; in brcmnand_read()
2220 /* Always exceed the software-imposed threshold */ in brcmnand_read()
2221 return max(mtd->bitflip_threshold, corrected); in brcmnand_read()
2232 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page()
2236 return brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page()
2237 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page()
2245 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page_raw()
2251 ret = brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page_raw()
2252 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page_raw()
2261 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob()
2262 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob()
2263 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob()
2272 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob_raw()
2273 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob_raw()
2274 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob_raw()
2283 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_write()
2284 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; in brcmnand_write()
2287 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); in brcmnand_write()
2290 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); in brcmnand_write()
2296 for (i = 0; i < ctrl->max_oob; i += 4) in brcmnand_write()
2300 if (ctrl->dma_trans(host, addr, (u32 *)buf, mtd->writesize, in brcmnand_write()
2303 ret = -EIO; in brcmnand_write()
2313 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_write()
2318 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_write()
2326 mtd->oobsize / trans, in brcmnand_write()
2327 host->hwcfg.sector_size_1k); in brcmnand_write()
2335 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_write()
2337 ret = -EIO; in brcmnand_write()
2351 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page()
2354 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page()
2364 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page_raw()
2368 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page_raw()
2377 (u64)page << chip->page_shift, NULL, in brcmnand_write_oob()
2378 chip->oob_poi); in brcmnand_write_oob()
2388 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, in brcmnand_write_oob_raw()
2389 (u8 *)chip->oob_poi); in brcmnand_write_oob_raw()
2396 * Per-CS setup (1 NAND device)
2402 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cfg()
2403 struct nand_chip *chip = &host->chip; in brcmnand_set_cfg()
2404 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_set_cfg()
2405 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2407 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2412 if (ctrl->block_sizes) { in brcmnand_set_cfg()
2415 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) in brcmnand_set_cfg()
2416 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { in brcmnand_set_cfg()
2421 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2422 cfg->block_size); in brcmnand_set_cfg()
2423 return -EINVAL; in brcmnand_set_cfg()
2426 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); in brcmnand_set_cfg()
2429 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && in brcmnand_set_cfg()
2430 cfg->block_size > ctrl->max_block_size)) { in brcmnand_set_cfg()
2431 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2432 cfg->block_size); in brcmnand_set_cfg()
2436 if (ctrl->page_sizes) { in brcmnand_set_cfg()
2439 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) in brcmnand_set_cfg()
2440 if (ctrl->page_sizes[i] == cfg->page_size) { in brcmnand_set_cfg()
2445 dev_warn(ctrl->dev, "invalid page size %u\n", in brcmnand_set_cfg()
2446 cfg->page_size); in brcmnand_set_cfg()
2447 return -EINVAL; in brcmnand_set_cfg()
2450 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); in brcmnand_set_cfg()
2453 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && in brcmnand_set_cfg()
2454 cfg->page_size > ctrl->max_page_size)) { in brcmnand_set_cfg()
2455 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); in brcmnand_set_cfg()
2456 return -EINVAL; in brcmnand_set_cfg()
2459 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { in brcmnand_set_cfg()
2460 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", in brcmnand_set_cfg()
2461 (unsigned long long)cfg->device_size); in brcmnand_set_cfg()
2462 return -EINVAL; in brcmnand_set_cfg()
2464 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); in brcmnand_set_cfg()
2466 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2467 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2468 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2469 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | in brcmnand_set_cfg()
2472 tmp |= (page_size << ctrl->page_size_shift) | in brcmnand_set_cfg()
2485 if (ctrl->nand_version >= 0x0302) { in brcmnand_set_cfg()
2486 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; in brcmnand_set_cfg()
2487 tmp |= cfg->spare_area_size; in brcmnand_set_cfg()
2491 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); in brcmnand_set_cfg()
2493 /* threshold = ceil(BCH-level * 0.75) */ in brcmnand_set_cfg()
2494 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); in brcmnand_set_cfg()
2503 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", in brcmnand_print_cfg()
2504 (unsigned long long)cfg->device_size >> 20, in brcmnand_print_cfg()
2505 cfg->block_size >> 10, in brcmnand_print_cfg()
2506 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, in brcmnand_print_cfg()
2507 cfg->page_size >= 1024 ? "KiB" : "B", in brcmnand_print_cfg()
2508 cfg->spare_area_size, cfg->device_width); in brcmnand_print_cfg()
2510 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ in brcmnand_print_cfg()
2511 if (is_hamming_ecc(host->ctrl, cfg)) in brcmnand_print_cfg()
2512 sprintf(buf, ", Hamming ECC"); in brcmnand_print_cfg()
2513 else if (cfg->sector_size_1k) in brcmnand_print_cfg()
2514 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); in brcmnand_print_cfg()
2516 sprintf(buf, ", BCH-%u", cfg->ecc_level); in brcmnand_print_cfg()
2521 * roundup(log2(size / page-size) / 8)
2523 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2528 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; in get_blk_adr_bytes()
2533 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmnand_setup_dev()
2534 struct nand_chip *chip = &host->chip; in brcmnand_setup_dev()
2536 nanddev_get_ecc_requirements(&chip->base); in brcmnand_setup_dev()
2537 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_setup_dev()
2538 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_setup_dev()
2546 "brcm,nand-oob-sector-size", in brcmnand_setup_dev()
2550 cfg->spare_area_size = mtd->oobsize / in brcmnand_setup_dev()
2551 (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2553 cfg->spare_area_size = oob_sector; in brcmnand_setup_dev()
2555 if (cfg->spare_area_size > ctrl->max_oob) in brcmnand_setup_dev()
2556 cfg->spare_area_size = ctrl->max_oob; in brcmnand_setup_dev()
2561 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2563 cfg->device_size = mtd->size; in brcmnand_setup_dev()
2564 cfg->block_size = mtd->erasesize; in brcmnand_setup_dev()
2565 cfg->page_size = mtd->writesize; in brcmnand_setup_dev()
2566 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; in brcmnand_setup_dev()
2567 cfg->col_adr_bytes = 2; in brcmnand_setup_dev()
2568 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); in brcmnand_setup_dev()
2570 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { in brcmnand_setup_dev()
2571 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", in brcmnand_setup_dev()
2572 chip->ecc.engine_type); in brcmnand_setup_dev()
2573 return -EINVAL; in brcmnand_setup_dev()
2576 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { in brcmnand_setup_dev()
2577 if (chip->ecc.strength == 1 && chip->ecc.size == 512) in brcmnand_setup_dev()
2578 /* Default to Hamming for 1-bit ECC, if unspecified */ in brcmnand_setup_dev()
2579 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in brcmnand_setup_dev()
2582 chip->ecc.algo = NAND_ECC_ALGO_BCH; in brcmnand_setup_dev()
2585 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING && in brcmnand_setup_dev()
2586 (chip->ecc.strength != 1 || chip->ecc.size != 512)) { in brcmnand_setup_dev()
2587 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", in brcmnand_setup_dev()
2588 chip->ecc.strength, chip->ecc.size); in brcmnand_setup_dev()
2589 return -EINVAL; in brcmnand_setup_dev()
2592 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && in brcmnand_setup_dev()
2593 (!chip->ecc.size || !chip->ecc.strength)) { in brcmnand_setup_dev()
2594 if (requirements->step_size && requirements->strength) { in brcmnand_setup_dev()
2595 /* use detected ECC parameters */ in brcmnand_setup_dev()
2596 chip->ecc.size = requirements->step_size; in brcmnand_setup_dev()
2597 chip->ecc.strength = requirements->strength; in brcmnand_setup_dev()
2598 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", in brcmnand_setup_dev()
2599 chip->ecc.size, chip->ecc.strength); in brcmnand_setup_dev()
2603 switch (chip->ecc.size) { in brcmnand_setup_dev()
2605 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) in brcmnand_setup_dev()
2606 cfg->ecc_level = 15; in brcmnand_setup_dev()
2608 cfg->ecc_level = chip->ecc.strength; in brcmnand_setup_dev()
2609 cfg->sector_size_1k = 0; in brcmnand_setup_dev()
2612 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { in brcmnand_setup_dev()
2613 dev_err(ctrl->dev, "1KB sectors not supported\n"); in brcmnand_setup_dev()
2614 return -EINVAL; in brcmnand_setup_dev()
2616 if (chip->ecc.strength & 0x1) { in brcmnand_setup_dev()
2617 dev_err(ctrl->dev, in brcmnand_setup_dev()
2618 "odd ECC not supported with 1KB sectors\n"); in brcmnand_setup_dev()
2619 return -EINVAL; in brcmnand_setup_dev()
2622 cfg->ecc_level = chip->ecc.strength >> 1; in brcmnand_setup_dev()
2623 cfg->sector_size_1k = 1; in brcmnand_setup_dev()
2626 dev_err(ctrl->dev, "unsupported ECC size: %d\n", in brcmnand_setup_dev()
2627 chip->ecc.size); in brcmnand_setup_dev()
2628 return -EINVAL; in brcmnand_setup_dev()
2631 cfg->ful_adr_bytes = cfg->blk_adr_bytes; in brcmnand_setup_dev()
2632 if (mtd->writesize > 512) in brcmnand_setup_dev()
2633 cfg->ful_adr_bytes += cfg->col_adr_bytes; in brcmnand_setup_dev()
2635 cfg->ful_adr_bytes += 1; in brcmnand_setup_dev()
2644 dev_info(ctrl->dev, "detected %s\n", msg); in brcmnand_setup_dev()
2647 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_setup_dev()
2652 /* We need to turn on Read from erased paged protected by ECC */ in brcmnand_setup_dev()
2653 if (ctrl->nand_version >= 0x0702) in brcmnand_setup_dev()
2656 if (ctrl->features & BRCMNAND_HAS_PREFETCH) in brcmnand_setup_dev()
2670 chip->options |= NAND_NO_SUBPAGE_WRITE; in brcmnand_attach_chip()
2676 chip->options |= NAND_USES_DMA; in brcmnand_attach_chip()
2678 if (chip->bbt_options & NAND_BBT_USE_FLASH) in brcmnand_attach_chip()
2679 chip->bbt_options |= NAND_BBT_NO_OOB; in brcmnand_attach_chip()
2682 return -ENXIO; in brcmnand_attach_chip()
2684 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; in brcmnand_attach_chip()
2687 mtd->bitflip_threshold = 1; in brcmnand_attach_chip()
2700 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_init_cs()
2701 struct platform_device *pdev = host->pdev; in brcmnand_init_cs()
2707 ret = of_property_read_u32(dn, "reg", &host->cs); in brcmnand_init_cs()
2709 dev_err(&pdev->dev, "can't get chip-select\n"); in brcmnand_init_cs()
2710 return -ENXIO; in brcmnand_init_cs()
2713 mtd = nand_to_mtd(&host->chip); in brcmnand_init_cs()
2714 chip = &host->chip; in brcmnand_init_cs()
2718 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", in brcmnand_init_cs()
2719 host->cs); in brcmnand_init_cs()
2720 if (!mtd->name) in brcmnand_init_cs()
2721 return -ENOMEM; in brcmnand_init_cs()
2723 mtd->owner = THIS_MODULE; in brcmnand_init_cs()
2724 mtd->dev.parent = &pdev->dev; in brcmnand_init_cs()
2726 chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl; in brcmnand_init_cs()
2727 chip->legacy.cmdfunc = brcmnand_cmdfunc; in brcmnand_init_cs()
2728 chip->legacy.waitfunc = brcmnand_waitfunc; in brcmnand_init_cs()
2729 chip->legacy.read_byte = brcmnand_read_byte; in brcmnand_init_cs()
2730 chip->legacy.read_buf = brcmnand_read_buf; in brcmnand_init_cs()
2731 chip->legacy.write_buf = brcmnand_write_buf; in brcmnand_init_cs()
2733 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in brcmnand_init_cs()
2734 chip->ecc.read_page = brcmnand_read_page; in brcmnand_init_cs()
2735 chip->ecc.write_page = brcmnand_write_page; in brcmnand_init_cs()
2736 chip->ecc.read_page_raw = brcmnand_read_page_raw; in brcmnand_init_cs()
2737 chip->ecc.write_page_raw = brcmnand_write_page_raw; in brcmnand_init_cs()
2738 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; in brcmnand_init_cs()
2739 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; in brcmnand_init_cs()
2740 chip->ecc.read_oob = brcmnand_read_oob; in brcmnand_init_cs()
2741 chip->ecc.write_oob = brcmnand_write_oob; in brcmnand_init_cs()
2743 chip->controller = &ctrl->controller; in brcmnand_init_cs()
2747 * NAND READID command only works in 8bit mode. We force in brcmnand_init_cs()
2748 * 8bit mode here to ensure that NAND READID commands works. in brcmnand_init_cs()
2750 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_init_cs()
2768 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_save_restore_cs_config()
2769 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_save_restore_cs_config()
2770 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2772 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2774 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); in brcmnand_save_restore_cs_config()
2775 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); in brcmnand_save_restore_cs_config()
2778 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); in brcmnand_save_restore_cs_config()
2781 host->hwcfg.config_ext); in brcmnand_save_restore_cs_config()
2782 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); in brcmnand_save_restore_cs_config()
2783 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); in brcmnand_save_restore_cs_config()
2784 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); in brcmnand_save_restore_cs_config()
2786 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); in brcmnand_save_restore_cs_config()
2788 host->hwcfg.config_ext = in brcmnand_save_restore_cs_config()
2790 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); in brcmnand_save_restore_cs_config()
2791 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); in brcmnand_save_restore_cs_config()
2792 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); in brcmnand_save_restore_cs_config()
2801 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_suspend()
2804 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); in brcmnand_suspend()
2805 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); in brcmnand_suspend()
2806 ctrl->corr_stat_threshold = in brcmnand_suspend()
2810 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); in brcmnand_suspend()
2812 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_suspend()
2823 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); in brcmnand_resume()
2828 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2829 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); in brcmnand_resume()
2834 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); in brcmnand_resume()
2835 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); in brcmnand_resume()
2837 ctrl->corr_stat_threshold); in brcmnand_resume()
2838 if (ctrl->soc) { in brcmnand_resume()
2839 /* Clear/re-enable interrupt */ in brcmnand_resume()
2840 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2841 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_resume()
2844 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_resume()
2845 struct nand_chip *chip = &host->chip; in brcmnand_resume()
2849 /* Reset the chip, required by some chips after power-up */ in brcmnand_resume()
2863 { .compatible = "brcm,brcmnand-v2.1" },
2864 { .compatible = "brcm,brcmnand-v2.2" },
2865 { .compatible = "brcm,brcmnand-v4.0" },
2866 { .compatible = "brcm,brcmnand-v5.0" },
2867 { .compatible = "brcm,brcmnand-v6.0" },
2868 { .compatible = "brcm,brcmnand-v6.1" },
2869 { .compatible = "brcm,brcmnand-v6.2" },
2870 { .compatible = "brcm,brcmnand-v7.0" },
2871 { .compatible = "brcm,brcmnand-v7.1" },
2872 { .compatible = "brcm,brcmnand-v7.2" },
2873 { .compatible = "brcm,brcmnand-v7.3" },
2883 struct device *dev = &pdev->dev; in brcmnand_edu_setup()
2884 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_edu_setup()
2888 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu"); in brcmnand_edu_setup()
2890 ctrl->edu_base = devm_ioremap_resource(dev, res); in brcmnand_edu_setup()
2891 if (IS_ERR(ctrl->edu_base)) in brcmnand_edu_setup()
2892 return PTR_ERR(ctrl->edu_base); in brcmnand_edu_setup()
2894 ctrl->edu_offsets = edu_regs; in brcmnand_edu_setup()
2903 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); in brcmnand_edu_setup()
2904 if (ctrl->edu_irq < 0) { in brcmnand_edu_setup()
2908 ret = devm_request_irq(dev, ctrl->edu_irq, in brcmnand_edu_setup()
2910 "brcmnand-edu", ctrl); in brcmnand_edu_setup()
2912 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", in brcmnand_edu_setup()
2913 ctrl->edu_irq, ret); in brcmnand_edu_setup()
2918 ctrl->edu_irq); in brcmnand_edu_setup()
2927 struct device *dev = &pdev->dev; in brcmnand_probe()
2928 struct device_node *dn = dev->of_node, *child; in brcmnand_probe()
2933 /* We only support device-tree instantiation */ in brcmnand_probe()
2935 return -ENODEV; in brcmnand_probe()
2938 return -ENODEV; in brcmnand_probe()
2942 return -ENOMEM; in brcmnand_probe()
2945 ctrl->dev = dev; in brcmnand_probe()
2947 init_completion(&ctrl->done); in brcmnand_probe()
2948 init_completion(&ctrl->dma_done); in brcmnand_probe()
2949 init_completion(&ctrl->edu_done); in brcmnand_probe()
2950 nand_controller_init(&ctrl->controller); in brcmnand_probe()
2951 ctrl->controller.ops = &brcmnand_controller_ops; in brcmnand_probe()
2952 INIT_LIST_HEAD(&ctrl->host_list); in brcmnand_probe()
2954 /* NAND register range */ in brcmnand_probe()
2956 ctrl->nand_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
2957 if (IS_ERR(ctrl->nand_base)) in brcmnand_probe()
2958 return PTR_ERR(ctrl->nand_base); in brcmnand_probe()
2960 /* Enable clock before using NAND registers */ in brcmnand_probe()
2961 ctrl->clk = devm_clk_get(dev, "nand"); in brcmnand_probe()
2962 if (!IS_ERR(ctrl->clk)) { in brcmnand_probe()
2963 ret = clk_prepare_enable(ctrl->clk); in brcmnand_probe()
2967 ret = PTR_ERR(ctrl->clk); in brcmnand_probe()
2968 if (ret == -EPROBE_DEFER) in brcmnand_probe()
2971 ctrl->clk = NULL; in brcmnand_probe()
2974 /* Initialize NAND revision */ in brcmnand_probe()
2980 * Most chips have this cache at a fixed offset within 'nand' block. in brcmnand_probe()
2983 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); in brcmnand_probe()
2985 ctrl->nand_fc = devm_ioremap_resource(dev, res); in brcmnand_probe()
2986 if (IS_ERR(ctrl->nand_fc)) { in brcmnand_probe()
2987 ret = PTR_ERR(ctrl->nand_fc); in brcmnand_probe()
2991 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
2992 ctrl->reg_offsets[BRCMNAND_FC_BASE]; in brcmnand_probe()
2996 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); in brcmnand_probe()
2998 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
2999 if (IS_ERR(ctrl->flash_dma_base)) { in brcmnand_probe()
3000 ret = PTR_ERR(ctrl->flash_dma_base); in brcmnand_probe()
3007 ret = -EIO; in brcmnand_probe()
3008 if (ctrl->nand_version >= 0x0700) in brcmnand_probe()
3009 ret = dma_set_mask_and_coherent(&pdev->dev, in brcmnand_probe()
3012 ret = dma_set_mask_and_coherent(&pdev->dev, in brcmnand_probe()
3017 /* linked-list and stop on error */ in brcmnand_probe()
3022 ctrl->dma_desc = dmam_alloc_coherent(dev, in brcmnand_probe()
3023 sizeof(*ctrl->dma_desc), in brcmnand_probe()
3024 &ctrl->dma_pa, GFP_KERNEL); in brcmnand_probe()
3025 if (!ctrl->dma_desc) { in brcmnand_probe()
3026 ret = -ENOMEM; in brcmnand_probe()
3030 ctrl->dma_irq = platform_get_irq(pdev, 1); in brcmnand_probe()
3031 if ((int)ctrl->dma_irq < 0) { in brcmnand_probe()
3033 ret = -ENODEV; in brcmnand_probe()
3037 ret = devm_request_irq(dev, ctrl->dma_irq, in brcmnand_probe()
3042 ctrl->dma_irq, ret); in brcmnand_probe()
3048 ctrl->dma_trans = brcmnand_dma_trans; in brcmnand_probe()
3056 ctrl->dma_trans = brcmnand_edu_trans; in brcmnand_probe()
3065 if (ctrl->features & BRCMNAND_HAS_WP) { in brcmnand_probe()
3074 ctrl->irq = platform_get_irq(pdev, 0); in brcmnand_probe()
3075 if ((int)ctrl->irq < 0) { in brcmnand_probe()
3076 dev_err(dev, "no IRQ defined\n"); in brcmnand_probe()
3077 ret = -ENODEV; in brcmnand_probe()
3086 ctrl->soc = soc; in brcmnand_probe()
3088 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, in brcmnand_probe()
3092 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
3093 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_probe()
3096 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, in brcmnand_probe()
3101 ctrl->irq, ret); in brcmnand_probe()
3112 ret = -ENOMEM; in brcmnand_probe()
3115 host->pdev = pdev; in brcmnand_probe()
3116 host->ctrl = ctrl; in brcmnand_probe()
3121 continue; /* Try all chip-selects */ in brcmnand_probe()
3124 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3128 /* No chip-selects could initialize properly */ in brcmnand_probe()
3129 if (list_empty(&ctrl->host_list)) { in brcmnand_probe()
3130 ret = -ENODEV; in brcmnand_probe()
3137 clk_disable_unprepare(ctrl->clk); in brcmnand_probe()
3145 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_remove()
3150 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_remove()
3151 chip = &host->chip; in brcmnand_remove()
3157 clk_disable_unprepare(ctrl->clk); in brcmnand_remove()
3159 dev_set_drvdata(&pdev->dev, NULL); in brcmnand_remove()
3168 MODULE_DESCRIPTION("NAND driver for Broadcom chips");