Lines Matching +full:non +full:- +full:programmable

1 # SPDX-License-Identifier: GPL-2.0-only
13 	  support any device that is CFI-compliant, you need to enable this
18 	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 	  This option enables JEDEC-style probing of flash chips which are not
24 	  CFI-targeted flash drivers for any chips which are identified which
26 	  covers most AMD/Fujitsu-compatible chips and also non-CFI
53 	  are expected to be wired to the CPU in 'host-endian' form.
83 	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
90 	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
97 	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
104 	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
111 	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
118 	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
126 	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
129 	  If your flash chips are not interleaved - i.e. you only have one
133 	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
136 	  If your flash chips are interleaved in pairs - i.e. you have two
140 	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
143 	  If your flash chips are interleaved in fours - i.e. you have four
147 	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
150 	  If your flash chips are interleaved in eights - i.e. you have eight
154 	bool "Protection Registers aka one-time programmable (OTP) bits"
160 	  A subset of them are pre-programmed at the factory with a
161 	  unique set of values. The rest is user-programmable.
163 	  The user-programmable Protection Registers contain one-time
164 	  programmable (OTP) bits; when programmed, register bits cannot be
184 	  sets which a CFI-compliant chip may claim to implement. This code
194 	  sets which a CFI-compliant chip may claim to implement. This code
204 	  sets which a CFI-compliant chip may claim to implement. This code
230 	  with this driver will return -ENODEV upon access.