21 static bool no_dma = 0;
22 static bool fixed_timeout = 0;
27 #define TIFM_MMCSD_RESET      0x0002
28 #define TIFM_MMCSD_CLKMASK    0x03ff
29 #define TIFM_MMCSD_POWER      0x0800
30 #define TIFM_MMCSD_4BBUS      0x8000
31 #define TIFM_MMCSD_RXDE       0x8000   /* rx dma enable */
32 #define TIFM_MMCSD_TXDE       0x0080   /* tx dma enable */
33 #define TIFM_MMCSD_BUFINT     0x0c00   /* set bits: AE, AF */
34 #define TIFM_MMCSD_DPE        0x0020   /* data timeout counted in kilocycles */
35 #define TIFM_MMCSD_INAB       0x0080   /* abort / initialize command */
36 #define TIFM_MMCSD_READ       0x8000
38 #define TIFM_MMCSD_ERRMASK    0x01e0   /* set bits: CCRC, CTO, DCRC, DTO */
39 #define TIFM_MMCSD_EOC        0x0001   /* end of command phase  */
40 #define TIFM_MMCSD_CD         0x0002   /* card detect           */
41 #define TIFM_MMCSD_CB         0x0004   /* card enter busy state */
42 #define TIFM_MMCSD_BRS        0x0008   /* block received/sent   */
43 #define TIFM_MMCSD_EOFB       0x0010   /* card exit busy state  */
44 #define TIFM_MMCSD_DTO        0x0020   /* data time-out         */
45 #define TIFM_MMCSD_DCRC       0x0040   /* data crc error        */
46 #define TIFM_MMCSD_CTO        0x0080   /* command time-out      */
47 #define TIFM_MMCSD_CCRC       0x0100   /* command crc error     */
48 #define TIFM_MMCSD_AF         0x0400   /* fifo almost full      */
49 #define TIFM_MMCSD_AE         0x0800   /* fifo almost empty     */
50 #define TIFM_MMCSD_OCRB       0x1000   /* OCR busy              */
51 #define TIFM_MMCSD_CIRQ       0x2000   /* card irq (cmd40/sdio) */
52 #define TIFM_MMCSD_CERR       0x4000   /* card status error     */
54 #define TIFM_MMCSD_ODTO       0x0040   /* open drain / extended timeout */
55 #define TIFM_MMCSD_CARD_RO    0x0200   /* card is read-only     */
57 #define TIFM_MMCSD_FIFO_SIZE  0x0020
59 #define TIFM_MMCSD_RSP_R0     0x0000
60 #define TIFM_MMCSD_RSP_R1     0x0100
61 #define TIFM_MMCSD_RSP_R2     0x0200
62 #define TIFM_MMCSD_RSP_R3     0x0300
63 #define TIFM_MMCSD_RSP_R4     0x0400
64 #define TIFM_MMCSD_RSP_R5     0x0500
65 #define TIFM_MMCSD_RSP_R6     0x0600
67 #define TIFM_MMCSD_RSP_BUSY   0x0800
69 #define TIFM_MMCSD_CMD_BC     0x0000
70 #define TIFM_MMCSD_CMD_BCR    0x1000
71 #define TIFM_MMCSD_CMD_AC     0x2000
72 #define TIFM_MMCSD_CMD_ADTC   0x3000
74 #define TIFM_MMCSD_MAX_BLOCK_SIZE  0x0800UL
79 	CMD_READY    = 0x0001,
80 	FIFO_READY   = 0x0002,
81 	BRS_READY    = 0x0004,
82 	SCMD_ACTIVE  = 0x0008,
83 	SCMD_READY   = 0x0010,
84 	CARD_BUSY    = 0x0020,
85 	DATA_CARRY   = 0x0040
117 	unsigned int pos = 0, val;  in tifm_sd_read_fifo()
121 		buf[pos++] = host->bounce_buf_data[0];  in tifm_sd_read_fifo()
127 		buf[pos++] = val & 0xff;  in tifm_sd_read_fifo()
129 			host->bounce_buf_data[0] = (val >> 8) & 0xff;  in tifm_sd_read_fifo()
133 		buf[pos++] = (val >> 8) & 0xff;  in tifm_sd_read_fifo()
143 	unsigned int pos = 0, val;  in tifm_sd_write_fifo()
147 		val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);  in tifm_sd_write_fifo()
155 			host->bounce_buf_data[0] = val & 0xff;  in tifm_sd_write_fifo()
159 		val |= (buf[pos++] << 8) & 0xff00;  in tifm_sd_write_fifo()
178 			host->block_pos = 0;  in tifm_sd_transfer_data()
183 					writel(host->bounce_buf_data[0],  in tifm_sd_transfer_data()
234 			host->block_pos = 0;  in tifm_sd_bounce_block()
283 		host->block_pos = 0;  in tifm_sd_set_dma_data()
311 		dma_off = 0;  in tifm_sd_set_dma_data()
325 	return 0;  in tifm_sd_set_dma_data()
330 	unsigned int rc = 0;  in tifm_sd_op_flags()
382 	dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",  in tifm_sd_exec()
385 	writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);  in tifm_sd_exec()
386 	writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);  in tifm_sd_exec()
392 	cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)  in tifm_sd_fetch_resp()
393 		       | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);  in tifm_sd_fetch_resp()
394 	cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)  in tifm_sd_fetch_resp()
395 		       | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);  in tifm_sd_fetch_resp()
396 	cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)  in tifm_sd_fetch_resp()
397 		       | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);  in tifm_sd_fetch_resp()
398 	cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)  in tifm_sd_fetch_resp()
399 		       | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);  in tifm_sd_fetch_resp()
478 	unsigned int fifo_status = 0;  in tifm_sd_data_event()
506 	unsigned int host_status = 0;  in tifm_sd_card_event()
507 	int cmd_error = 0;  in tifm_sd_card_event()
604 	if (data_timeout < 0xffff) {  in tifm_sd_set_data_timeout()
611 		if (data_timeout > 0xffff)  in tifm_sd_set_data_timeout()
612 			data_timeout = 0;	/* set to unlimited */  in tifm_sd_set_data_timeout()
640 	host->cmd_flags = 0;  in tifm_sd_request()
641 	host->block_pos = 0;  in tifm_sd_request()
642 	host->sg_pos = 0;  in tifm_sd_request()
647 		host->no_dma = no_dma ? 1 : 0;  in tifm_sd_request()
846 		host->clk_div = 0;  in tifm_sd_ios()
865 	int rc = 0;  in tifm_sd_ro()
886 	unsigned int host_status = 0;  in tifm_sd_initialize_host()
889 	writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);  in tifm_sd_initialize_host()
899 			rc = 0;  in tifm_sd_initialize_host()
911 	writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);  in tifm_sd_initialize_host()
925 			rc = 0;  in tifm_sd_initialize_host()
941 	return 0;  in tifm_sd_initialize_host()
973 	timer_setup(&host->timer, tifm_sd_abort, 0);  in tifm_sd_probe()
994 		return 0;  in tifm_sd_probe()
1008 	writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);  in tifm_sd_remove()
1017 		writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);  in tifm_sd_remove()
1034 	return 0;  in tifm_sd_suspend()