3  * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
65 	{ .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
66 	{ .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
67 	{ .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
68 	{ .compatible = "fsl,p1010-esdhc",   .data = &p1010_esdhc_clk},
69 	{ .compatible = "fsl,mpc8379-esdhc" },
70 	{ .compatible = "fsl,mpc8536-esdhc" },
71 	{ .compatible = "fsl,esdhc" },
94  * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
99  * @value: 32bit eSDHC register value on spec_reg address
101  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
103  * address, register function, bit position and function between eSDHC spec
112 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_readl_fixup()  local
116 	 * The bit of ADMA flag in eSDHC is not compatible with standard  in esdhc_readl_fixup()
118 	 * supported by eSDHC.  in esdhc_readl_fixup()
119 	 * And for many FSL eSDHC controller, the reset value of field  in esdhc_readl_fixup()
124 		if (esdhc->vendor_ver > VENDOR_V_22) {  in esdhc_readl_fixup()
162 	(esdhc->quirk_ignore_data_inhibit == true)) {  in esdhc_readl_fixup()
175 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_readw_fixup()  local
186 	/* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect  in esdhc_readw_fixup()
190 	    (esdhc->quirk_incorrect_hostver))  in esdhc_readw_fixup()
220  *			written into eSDHC register.
225  * @old_value: 32bit eSDHC register value on spec_reg address
227  * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
229  * address, register function, bit position and function between eSDHC spec
295 	 * eSDHC doesn't have a standard power control register, so we do  in esdhc_writeb_fixup()
421 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_be_writew()  local
436 		    esdhc->in_sw_tuning) {  in esdhc_be_writew()
447 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_le_writew()  local
462 		    esdhc->in_sw_tuning) {  in esdhc_le_writew()
502 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_of_adma_workaround()  local
509 		     (esdhc->vendor_ver == VENDOR_V_23);  in esdhc_of_adma_workaround()
530 	if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||  in esdhc_of_enable_dma()
531 	    of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc"))  in esdhc_of_enable_dma()
548 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_of_get_max_clock()  local
550 	if (esdhc->peripheral_clock)  in esdhc_of_get_max_clock()
551 		return esdhc->peripheral_clock;  in esdhc_of_get_max_clock()
559 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_of_get_min_clock()  local
562 	if (esdhc->peripheral_clock)  in esdhc_of_get_min_clock()
563 		clock = esdhc->peripheral_clock;  in esdhc_of_get_min_clock()
572 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_clock_enable()  local
579 	 * IPGEN/HCKEN/PEREN bits exist on eSDHC whose vendor version  in esdhc_clock_enable()
582 	if (esdhc->vendor_ver <= VENDOR_V_22)  in esdhc_clock_enable()
600 	while (esdhc->vendor_ver > VENDOR_V_22) {  in esdhc_clock_enable()
643 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_of_set_clock()  local
656 	if (esdhc->vendor_ver < VENDOR_V_23)  in esdhc_of_set_clock()
661 	    esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)  in esdhc_of_set_clock()
662 		clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk;  in esdhc_of_set_clock()
663 	else if (esdhc->clk_fixup)  in esdhc_of_set_clock()
664 		clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];  in esdhc_of_set_clock()
676 	esdhc->div_ratio = pre_div * div;  in esdhc_of_set_clock()
679 	if (esdhc->quirk_limited_clk_division &&  in esdhc_of_set_clock()
683 		if (esdhc->div_ratio <= 4) {  in esdhc_of_set_clock()
686 		} else if (esdhc->div_ratio <= 8) {  in esdhc_of_set_clock()
689 		} else if (esdhc->div_ratio <= 12) {  in esdhc_of_set_clock()
696 		esdhc->div_ratio = pre_div * div;  in esdhc_of_set_clock()
699 	host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;  in esdhc_of_set_clock()
721 	while (esdhc->vendor_ver > VENDOR_V_22) {  in esdhc_of_set_clock()
797 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_reset()  local
804 	if (esdhc->quirk_delay_before_data_reset &&  in esdhc_reset()
810 	 * Save bus-width for eSDHC whose vendor version is 2.2  in esdhc_reset()
814 	    (esdhc->vendor_ver <= VENDOR_V_22)) {  in esdhc_reset()
822 	 * Restore bus-width setting and interrupt registers for eSDHC  in esdhc_reset()
826 	    (esdhc->vendor_ver <= VENDOR_V_22)) {  in esdhc_reset()
837 	 * Some bits have to be cleaned manually for eSDHC whose spec  in esdhc_reset()
841 	    (esdhc->spec_ver >= SDHCI_SPEC_300)) {  in esdhc_reset()
850 		if (esdhc->quirk_unreliable_pulse_detection) {  in esdhc_reset()
994 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_prepare_sw_tuning()  local
997 	if (esdhc->quirk_tuning_erratum_type1) {  in esdhc_prepare_sw_tuning()
998 		*window_start = 5 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
999 		*window_end = 3 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1016 	if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) {  in esdhc_prepare_sw_tuning()
1017 		*window_start = 8 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1018 		*window_end = 4 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1020 		*window_start = 5 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1021 		*window_end = 3 * esdhc->div_ratio;  in esdhc_prepare_sw_tuning()
1030 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_execute_sw_tuning()  local
1046 	esdhc->in_sw_tuning = true;  in esdhc_execute_sw_tuning()
1048 	esdhc->in_sw_tuning = false;  in esdhc_execute_sw_tuning()
1056 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_execute_tuning()  local
1066 	clk = esdhc->peripheral_clock / 3;  in esdhc_execute_tuning()
1073 	 * The eSDHC controller takes the data timeout value into account  in esdhc_execute_tuning()
1086 		if (esdhc->quirk_limited_clk_division &&  in esdhc_execute_tuning()
1101 		 * tuning may succeed although eSDHC might not have  in esdhc_execute_tuning()
1104 		if (esdhc->quirk_tuning_erratum_type2 &&  in esdhc_execute_tuning()
1109 			    (4 * esdhc->div_ratio + 2))  in esdhc_execute_tuning()
1118 		    (esdhc->quirk_tuning_erratum_type1 ||  in esdhc_execute_tuning()
1119 		     esdhc->quirk_tuning_erratum_type2)) {  in esdhc_execute_tuning()
1141 				clk = host->max_clk / (esdhc->div_ratio + 1);  in esdhc_execute_tuning()
1210 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_irq()  local
1213 	if (esdhc->quirk_trans_complete_erratum) {  in esdhc_irq()
1336 	struct sdhci_esdhc *esdhc;  in esdhc_init()  local
1343 	esdhc = sdhci_pltfm_priv(pltfm_host);  in esdhc_init()
1346 	esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>  in esdhc_init()
1348 	esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;  in esdhc_init()
1350 		esdhc->quirk_incorrect_hostver = true;  in esdhc_init()
1352 		esdhc->quirk_incorrect_hostver = false;  in esdhc_init()
1355 		esdhc->quirk_limited_clk_division = true;  in esdhc_init()
1357 		esdhc->quirk_limited_clk_division = false;  in esdhc_init()
1360 		esdhc->quirk_unreliable_pulse_detection = true;  in esdhc_init()
1362 		esdhc->quirk_unreliable_pulse_detection = false;  in esdhc_init()
1366 		esdhc->clk_fixup = match->data;  in esdhc_init()
1369 	if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {  in esdhc_init()
1370 		esdhc->quirk_delay_before_data_reset = true;  in esdhc_init()
1371 		esdhc->quirk_trans_complete_erratum = true;  in esdhc_init()
1377 		 * esdhc->peripheral_clock would be assigned with a value  in esdhc_init()
1378 		 * which is eSDHC base clock when use periperal clock.  in esdhc_init()
1380 		 * API is peripheral clock while the eSDHC base clock is  in esdhc_init()
1383 		if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||  in esdhc_init()
1384 		    of_device_is_compatible(np, "fsl,ls1028a-esdhc") ||  in esdhc_init()
1385 		    of_device_is_compatible(np, "fsl,ls1088a-esdhc"))  in esdhc_init()
1386 			esdhc->peripheral_clock = clk_get_rate(clk) / 2;  in esdhc_init()
1388 			esdhc->peripheral_clock = clk_get_rate(clk);  in esdhc_init()
1400 	if (esdhc->peripheral_clock)  in esdhc_init()
1419 	struct sdhci_esdhc *esdhc;  in sdhci_esdhc_probe()  local
1445 	esdhc = sdhci_pltfm_priv(pltfm_host);  in sdhci_esdhc_probe()
1447 		esdhc->quirk_tuning_erratum_type1 = true;  in sdhci_esdhc_probe()
1449 		esdhc->quirk_tuning_erratum_type1 = false;  in sdhci_esdhc_probe()
1452 		esdhc->quirk_tuning_erratum_type2 = true;  in sdhci_esdhc_probe()
1454 		esdhc->quirk_tuning_erratum_type2 = false;  in sdhci_esdhc_probe()
1456 	if (esdhc->vendor_ver == VENDOR_V_22)  in sdhci_esdhc_probe()
1459 	if (esdhc->vendor_ver > VENDOR_V_22)  in sdhci_esdhc_probe()
1462 	if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {  in sdhci_esdhc_probe()
1467 	if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||  in sdhci_esdhc_probe()
1468 	    of_device_is_compatible(np, "fsl,p5020-esdhc") ||  in sdhci_esdhc_probe()
1469 	    of_device_is_compatible(np, "fsl,p4080-esdhc") ||  in sdhci_esdhc_probe()
1470 	    of_device_is_compatible(np, "fsl,p1020-esdhc") ||  in sdhci_esdhc_probe()
1471 	    of_device_is_compatible(np, "fsl,t1040-esdhc"))  in sdhci_esdhc_probe()
1474 	if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))  in sdhci_esdhc_probe()
1477 	esdhc->quirk_ignore_data_inhibit = false;  in sdhci_esdhc_probe()
1478 	if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {  in sdhci_esdhc_probe()
1484 		esdhc->quirk_ignore_data_inhibit = true;  in sdhci_esdhc_probe()
1506 		.name = "sdhci-esdhc",
1517 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");