49 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
52 #define VERSAL_OCLK_PHASE {0,  60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
616 		/* For 50MHz clock, 30 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
620 		/* For 100MHz clock, 15 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
625 		/* For 200MHz clock, 8 Taps are available */  in sdhci_zynqmp_sdcardclk_set_phase()
684 		/* For 50MHz clock, 120 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
688 		/* For 100MHz clock, 60 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
689 		tap_max = 60;  in sdhci_zynqmp_sampleclk_set_phase()
693 		/* For 200MHz clock, 30 Taps are available */  in sdhci_zynqmp_sampleclk_set_phase()
743 		/* For 50MHz clock, 30 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
747 		/* For 100MHz clock, 15 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
752 		/* For 200MHz clock, 8 Taps are available */  in sdhci_versal_sdcardclk_set_phase()
809 		/* For 50MHz clock, 120 Taps are available */  in sdhci_versal_sampleclk_set_phase()
813 		/* For 100MHz clock, 60 Taps are available */  in sdhci_versal_sampleclk_set_phase()
814 		tap_max = 60;  in sdhci_versal_sampleclk_set_phase()
818 		/* For 200MHz clock, 30 Taps are available */  in sdhci_versal_sampleclk_set_phase()
933  * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin.  This
951 	u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_arasan_update_baseclkfreq()  local
964 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);  in sdhci_arasan_update_baseclkfreq()