Lines Matching +full:no +full:- +full:mmc
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
11 #include <linux/mmc/mmc.h>
20 #include "sdhci-pltfm.h"
119 #define INVALID_TUNING_PHASE -1
133 /* Max load for eMMC Vdd-io supply */
137 msm_host->var_ops->msm_readl_relaxed(host, offset)
140 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
264 struct mmc_host *mmc; member
294 return msm_host->offset; in sdhci_priv_msm_offset()
307 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
313 return readl_relaxed(host->ioaddr + offset); in sdhci_msm_v5_variant_readl_relaxed()
322 writel_relaxed(val, msm_host->core_mem + offset); in sdhci_msm_mci_variant_writel_relaxed()
328 writel_relaxed(val, host->ioaddr + offset); in sdhci_msm_v5_variant_writel_relaxed()
334 struct mmc_ios ios = host->mmc->ios; in msm_get_clock_rate_for_bus_mode()
344 host->flags & SDHCI_HS400_TUNING) in msm_get_clock_rate_for_bus_mode()
354 struct mmc_ios curr_ios = host->mmc->ios; in msm_set_clock_rate_for_bus_mode()
355 struct clk *core_clk = msm_host->bulk_clks[0].clk; in msm_set_clock_rate_for_bus_mode()
359 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), clock); in msm_set_clock_rate_for_bus_mode()
362 mmc_hostname(host->mmc), clock, in msm_set_clock_rate_for_bus_mode()
366 msm_host->clk_rate = clock; in msm_set_clock_rate_for_bus_mode()
368 mmc_hostname(host->mmc), clk_get_rate(core_clk), in msm_set_clock_rate_for_bus_mode()
377 struct mmc_host *mmc = host->mmc; in msm_dll_poll_ck_out_en() local
382 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
383 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
386 if (--wait_cnt == 0) { in msm_dll_poll_ck_out_en()
387 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", in msm_dll_poll_ck_out_en()
388 mmc_hostname(mmc), poll); in msm_dll_poll_ck_out_en()
389 return -ETIMEDOUT; in msm_dll_poll_ck_out_en()
393 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
394 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
409 struct mmc_host *mmc = host->mmc; in msm_config_cm_dll_phase() local
414 return -EINVAL; in msm_config_cm_dll_phase()
416 spin_lock_irqsave(&host->lock, flags); in msm_config_cm_dll_phase()
418 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
421 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
432 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
435 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
437 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
439 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
446 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
449 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
453 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", in msm_config_cm_dll_phase()
454 mmc_hostname(mmc), phase); in msm_config_cm_dll_phase()
456 spin_unlock_irqrestore(&host->lock, flags); in msm_config_cm_dll_phase()
463 * setting for SD3.0 UHS-I card read operation (in SDR104
479 struct mmc_host *mmc = host->mmc; in msm_find_most_appropriate_phase() local
482 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", in msm_find_most_appropriate_phase()
483 mmc_hostname(mmc), total_phases); in msm_find_most_appropriate_phase()
484 return -EINVAL; in msm_find_most_appropriate_phase()
502 return -EINVAL; in msm_find_most_appropriate_phase()
504 /* Check if phase-0 is present in first valid window? */ in msm_find_most_appropriate_phase()
535 return -EINVAL; in msm_find_most_appropriate_phase()
559 i--; in msm_find_most_appropriate_phase()
564 ret = -EINVAL; in msm_find_most_appropriate_phase()
565 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", in msm_find_most_appropriate_phase()
566 mmc_hostname(mmc), ret); in msm_find_most_appropriate_phase()
579 if (host->clock <= 112000000) in msm_cm_dll_set_freq()
581 else if (host->clock <= 125000000) in msm_cm_dll_set_freq()
583 else if (host->clock <= 137000000) in msm_cm_dll_set_freq()
585 else if (host->clock <= 150000000) in msm_cm_dll_set_freq()
587 else if (host->clock <= 162000000) in msm_cm_dll_set_freq()
589 else if (host->clock <= 175000000) in msm_cm_dll_set_freq()
591 else if (host->clock <= 187000000) in msm_cm_dll_set_freq()
593 else if (host->clock <= 200000000) in msm_cm_dll_set_freq()
596 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
599 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
605 struct mmc_host *mmc = host->mmc; in msm_init_cm_dll() local
612 msm_host->offset; in msm_init_cm_dll()
614 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) in msm_init_cm_dll()
615 xo_clk = clk_get_rate(msm_host->xo_clk); in msm_init_cm_dll()
617 spin_lock_irqsave(&host->lock, flags); in msm_init_cm_dll()
624 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
626 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
628 if (msm_host->dll_config) in msm_init_cm_dll()
629 writel_relaxed(msm_host->dll_config, in msm_init_cm_dll()
630 host->ioaddr + msm_offset->core_dll_config); in msm_init_cm_dll()
632 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
633 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
634 msm_offset->core_dll_config); in msm_init_cm_dll()
636 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
637 msm_offset->core_dll_config); in msm_init_cm_dll()
639 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
640 msm_offset->core_dll_config_2); in msm_init_cm_dll()
642 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
643 msm_offset->core_dll_config_2); in msm_init_cm_dll()
646 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
647 msm_offset->core_dll_config); in msm_init_cm_dll()
649 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
650 msm_offset->core_dll_config); in msm_init_cm_dll()
652 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
653 msm_offset->core_dll_config); in msm_init_cm_dll()
655 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
656 msm_offset->core_dll_config); in msm_init_cm_dll()
658 if (!msm_host->dll_config) in msm_init_cm_dll()
661 if (msm_host->use_14lpp_dll_reset && in msm_init_cm_dll()
662 !IS_ERR_OR_NULL(msm_host->xo_clk)) { in msm_init_cm_dll()
665 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
666 msm_offset->core_dll_config_2); in msm_init_cm_dll()
669 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), in msm_init_cm_dll()
672 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), in msm_init_cm_dll()
675 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
676 msm_offset->core_dll_config_2); in msm_init_cm_dll()
680 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
681 msm_offset->core_dll_config_2); in msm_init_cm_dll()
686 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
687 msm_offset->core_dll_config); in msm_init_cm_dll()
689 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
690 msm_offset->core_dll_config); in msm_init_cm_dll()
692 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
693 msm_offset->core_dll_config); in msm_init_cm_dll()
695 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
696 msm_offset->core_dll_config); in msm_init_cm_dll()
698 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
699 if (!msm_host->dll_config) in msm_init_cm_dll()
701 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
702 msm_offset->core_dll_config_2); in msm_init_cm_dll()
704 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
705 msm_offset->core_dll_config_2); in msm_init_cm_dll()
712 if (msm_host->uses_tassadar_dll) { in msm_init_cm_dll()
715 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
716 msm_offset->core_dll_usr_ctl); in msm_init_cm_dll()
718 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
719 msm_offset->core_dll_config_3); in msm_init_cm_dll()
721 if (msm_host->clk_rate < 150000000) in msm_init_cm_dll()
725 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
726 msm_offset->core_dll_config_3); in msm_init_cm_dll()
729 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
730 msm_offset->core_dll_config); in msm_init_cm_dll()
732 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
733 msm_offset->core_dll_config); in msm_init_cm_dll()
735 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
736 msm_offset->core_dll_config); in msm_init_cm_dll()
738 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
739 msm_offset->core_dll_config); in msm_init_cm_dll()
742 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & in msm_init_cm_dll()
745 if (--wait_cnt == 0) { in msm_init_cm_dll()
746 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", in msm_init_cm_dll()
747 mmc_hostname(mmc)); in msm_init_cm_dll()
748 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
749 return -ETIMEDOUT; in msm_init_cm_dll()
754 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
764 msm_host->offset; in msm_hc_select_default()
766 if (!msm_host->use_cdclp533) { in msm_hc_select_default()
767 config = readl_relaxed(host->ioaddr + in msm_hc_select_default()
768 msm_offset->core_vendor_spec3); in msm_hc_select_default()
770 writel_relaxed(config, host->ioaddr + in msm_hc_select_default()
771 msm_offset->core_vendor_spec3); in msm_hc_select_default()
774 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
777 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
786 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
789 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
802 struct mmc_ios ios = host->mmc->ios; in msm_hc_select_hs400()
806 msm_host->offset; in msm_hc_select_hs400()
809 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
813 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
818 if ((msm_host->tuning_done || ios.enhanced_strobe) && in msm_hc_select_hs400()
819 !msm_host->calibration_done) { in msm_hc_select_hs400()
820 config = readl_relaxed(host->ioaddr + in msm_hc_select_hs400()
821 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
824 writel_relaxed(config, host->ioaddr + in msm_hc_select_hs400()
825 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
827 if (!msm_host->clk_rate && !msm_host->use_cdclp533) { in msm_hc_select_hs400()
833 rc = readl_relaxed_poll_timeout(host->ioaddr + in msm_hc_select_hs400()
834 msm_offset->core_dll_status, in msm_hc_select_hs400()
840 if (rc == -ETIMEDOUT) in msm_hc_select_hs400()
842 mmc_hostname(host->mmc), dll_lock); in msm_hc_select_hs400()
852 * sdhci_msm_hc_select_mode :- In general all timing modes are
857 * HS200 - SDR104 (Since they both are equivalent in functionality)
858 * HS400 - This involves multiple configurations
859 * Initially SDR104 - when tuning is required as HS200
866 * HS400 - divided clock (free running MCLK/2)
867 * All other modes - default (free running MCLK)
871 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_hc_select_mode()
874 host->flags & SDHCI_HS400_TUNING) in sdhci_msm_hc_select_mode()
887 msm_host->offset; in sdhci_msm_cdclp533_calibration()
889 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
900 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_cdclp533_calibration()
904 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
906 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
908 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
910 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
912 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
914 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
916 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
918 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
920 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
922 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
926 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
927 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); in sdhci_msm_cdclp533_calibration()
928 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
929 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); in sdhci_msm_cdclp533_calibration()
930 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); in sdhci_msm_cdclp533_calibration()
931 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); in sdhci_msm_cdclp533_calibration()
932 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); in sdhci_msm_cdclp533_calibration()
933 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); in sdhci_msm_cdclp533_calibration()
934 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); in sdhci_msm_cdclp533_calibration()
938 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
940 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
942 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
944 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
946 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
948 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
950 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
952 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
954 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, in sdhci_msm_cdclp533_calibration()
959 if (ret == -ETIMEDOUT) { in sdhci_msm_cdclp533_calibration()
961 mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
965 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) in sdhci_msm_cdclp533_calibration()
969 mmc_hostname(host->mmc), __func__, ret); in sdhci_msm_cdclp533_calibration()
970 ret = -EINVAL; in sdhci_msm_cdclp533_calibration()
974 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
976 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
978 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cdclp533_calibration()
985 struct mmc_host *mmc = host->mmc; in sdhci_msm_cm_dll_sdc4_calibration() local
993 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1002 if (msm_host->updated_ddr_cfg) in sdhci_msm_cm_dll_sdc4_calibration()
1003 ddr_cfg_offset = msm_offset->core_ddr_config; in sdhci_msm_cm_dll_sdc4_calibration()
1005 ddr_cfg_offset = msm_offset->core_ddr_config_old; in sdhci_msm_cm_dll_sdc4_calibration()
1006 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); in sdhci_msm_cm_dll_sdc4_calibration()
1008 if (mmc->ios.enhanced_strobe) { in sdhci_msm_cm_dll_sdc4_calibration()
1009 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1010 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1012 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1013 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1016 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1018 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1020 ret = readl_relaxed_poll_timeout(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1021 msm_offset->core_dll_status, in sdhci_msm_cm_dll_sdc4_calibration()
1026 if (ret == -ETIMEDOUT) { in sdhci_msm_cm_dll_sdc4_calibration()
1028 mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1035 * and MCLK must be switched on for at-least 1us before DATA in sdhci_msm_cm_dll_sdc4_calibration()
1040 if (!msm_host->use_14lpp_dll_reset) { in sdhci_msm_cm_dll_sdc4_calibration()
1041 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1042 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1044 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1045 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1054 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cm_dll_sdc4_calibration()
1063 struct mmc_host *mmc = host->mmc; in sdhci_msm_hs400_dll_calibration() local
1067 msm_host->offset; in sdhci_msm_hs400_dll_calibration()
1069 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_hs400_dll_calibration()
1079 if (!mmc->ios.enhanced_strobe) { in sdhci_msm_hs400_dll_calibration()
1082 msm_host->saved_tuning_phase); in sdhci_msm_hs400_dll_calibration()
1085 config = readl_relaxed(host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1086 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1088 writel_relaxed(config, host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1089 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1092 if (msm_host->use_cdclp533) in sdhci_msm_hs400_dll_calibration()
1097 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_hs400_dll_calibration()
1104 struct mmc_ios *ios = &host->mmc->ios; in sdhci_msm_is_tuning_needed()
1110 if (host->clock <= CORE_FREQ_100MHZ || in sdhci_msm_is_tuning_needed()
1111 !(ios->timing == MMC_TIMING_MMC_HS400 || in sdhci_msm_is_tuning_needed()
1112 ios->timing == MMC_TIMING_MMC_HS200 || in sdhci_msm_is_tuning_needed()
1113 ios->timing == MMC_TIMING_UHS_SDR104) || in sdhci_msm_is_tuning_needed()
1114 ios->enhanced_strobe) in sdhci_msm_is_tuning_needed()
1139 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_restore_sdr_dll_config()
1147 u32 config, oldconfig = readl_relaxed(host->ioaddr + in sdhci_msm_set_cdr()
1148 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1160 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_cdr()
1161 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1165 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) in sdhci_msm_execute_tuning() argument
1167 struct sdhci_host *host = mmc_priv(mmc); in sdhci_msm_execute_tuning()
1171 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_execute_tuning()
1176 msm_host->use_cdr = false; in sdhci_msm_execute_tuning()
1181 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ in sdhci_msm_execute_tuning()
1182 msm_host->use_cdr = true; in sdhci_msm_execute_tuning()
1188 msm_host->tuning_done = 0; in sdhci_msm_execute_tuning()
1192 * - select MCLK/2 in VENDOR_SPEC in sdhci_msm_execute_tuning()
1193 * - program MCLK to 400MHz (or nearest supported) in GCC in sdhci_msm_execute_tuning()
1195 if (host->flags & SDHCI_HS400_TUNING) { in sdhci_msm_execute_tuning()
1198 host->flags &= ~SDHCI_HS400_TUNING; in sdhci_msm_execute_tuning()
1214 rc = mmc_send_tuning(mmc, opcode, NULL); in sdhci_msm_execute_tuning()
1218 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_msm_execute_tuning()
1219 mmc_hostname(mmc), phase); in sdhci_msm_execute_tuning()
1226 * All phases valid is _almost_ as bad as no phases in sdhci_msm_execute_tuning()
1232 dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n", in sdhci_msm_execute_tuning()
1233 mmc_hostname(mmc)); in sdhci_msm_execute_tuning()
1234 if (--tuning_seq_cnt) { in sdhci_msm_execute_tuning()
1254 msm_host->saved_tuning_phase = phase; in sdhci_msm_execute_tuning()
1255 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", in sdhci_msm_execute_tuning()
1256 mmc_hostname(mmc), phase); in sdhci_msm_execute_tuning()
1258 if (--tuning_seq_cnt) in sdhci_msm_execute_tuning()
1261 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", in sdhci_msm_execute_tuning()
1262 mmc_hostname(mmc)); in sdhci_msm_execute_tuning()
1263 rc = -EIO; in sdhci_msm_execute_tuning()
1267 msm_host->tuning_done = true; in sdhci_msm_execute_tuning()
1272 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1283 if (host->clock > CORE_FREQ_100MHZ && in sdhci_msm_hs400()
1284 (msm_host->tuning_done || ios->enhanced_strobe) && in sdhci_msm_hs400()
1285 !msm_host->calibration_done) { in sdhci_msm_hs400()
1288 msm_host->calibration_done = true; in sdhci_msm_hs400()
1291 mmc_hostname(host->mmc), ret); in sdhci_msm_hs400()
1298 struct mmc_host *mmc = host->mmc; in sdhci_msm_set_uhs_signaling() local
1304 msm_host->offset; in sdhci_msm_set_uhs_signaling()
1336 if (host->clock <= CORE_FREQ_100MHZ) { in sdhci_msm_set_uhs_signaling()
1345 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1346 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1348 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1349 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1351 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1352 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1354 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1355 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1361 msm_host->calibration_done = false; in sdhci_msm_set_uhs_signaling()
1364 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", in sdhci_msm_set_uhs_signaling()
1365 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); in sdhci_msm_set_uhs_signaling()
1368 if (mmc->ios.timing == MMC_TIMING_MMC_HS400) in sdhci_msm_set_uhs_signaling()
1369 sdhci_msm_hs400(host, &mmc->ios); in sdhci_msm_set_uhs_signaling()
1374 struct platform_device *pdev = msm_host->pdev; in sdhci_msm_set_pincfg()
1378 ret = pinctrl_pm_select_default_state(&pdev->dev); in sdhci_msm_set_pincfg()
1380 ret = pinctrl_pm_select_sleep_state(&pdev->dev); in sdhci_msm_set_pincfg()
1385 static int sdhci_msm_set_vmmc(struct mmc_host *mmc) in sdhci_msm_set_vmmc() argument
1387 if (IS_ERR(mmc->supply.vmmc)) in sdhci_msm_set_vmmc()
1390 return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); in sdhci_msm_set_vmmc()
1394 struct mmc_host *mmc, bool level) in msm_toggle_vqmmc() argument
1399 if (msm_host->vqmmc_enabled == level) in msm_toggle_vqmmc()
1404 if (msm_host->caps_0 & CORE_3_0V_SUPPORT) in msm_toggle_vqmmc()
1406 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT) in msm_toggle_vqmmc()
1409 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in msm_toggle_vqmmc()
1410 ret = mmc_regulator_set_vqmmc(mmc, &ios); in msm_toggle_vqmmc()
1412 dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n", in msm_toggle_vqmmc()
1413 mmc_hostname(mmc), ret); in msm_toggle_vqmmc()
1417 ret = regulator_enable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1419 ret = regulator_disable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1423 dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n", in msm_toggle_vqmmc()
1424 mmc_hostname(mmc), level ? "en":"dis", ret); in msm_toggle_vqmmc()
1426 msm_host->vqmmc_enabled = level; in msm_toggle_vqmmc()
1432 struct mmc_host *mmc, bool hpm) in msm_config_vqmmc_mode() argument
1437 ret = regulator_set_load(mmc->supply.vqmmc, load); in msm_config_vqmmc_mode()
1439 dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n", in msm_config_vqmmc_mode()
1440 mmc_hostname(mmc), ret); in msm_config_vqmmc_mode()
1445 struct mmc_host *mmc, bool level) in sdhci_msm_set_vqmmc() argument
1450 if (IS_ERR(mmc->supply.vqmmc) || in sdhci_msm_set_vqmmc()
1451 (mmc->ios.power_mode == MMC_POWER_UNDEFINED)) in sdhci_msm_set_vqmmc()
1463 always_on = !mmc_card_is_removable(mmc) && in sdhci_msm_set_vqmmc()
1464 mmc->card && mmc_card_mmc(mmc->card); in sdhci_msm_set_vqmmc()
1467 ret = msm_config_vqmmc_mode(msm_host, mmc, level); in sdhci_msm_set_vqmmc()
1469 ret = msm_toggle_vqmmc(msm_host, mmc, level); in sdhci_msm_set_vqmmc()
1476 init_waitqueue_head(&msm_host->pwr_irq_wait); in sdhci_msm_init_pwr_irq_wait()
1482 wake_up(&msm_host->pwr_irq_wait); in sdhci_msm_complete_pwr_irq_wait()
1501 msm_host->offset; in sdhci_msm_check_power_status()
1504 mmc_hostname(host->mmc), __func__, req_type, in sdhci_msm_check_power_status()
1505 msm_host->curr_pwr_state, msm_host->curr_io_level); in sdhci_msm_check_power_status()
1510 * Since sdhci-msm-v5, this bit has been removed and SW must consider in sdhci_msm_check_power_status()
1513 if (!msm_host->mci_removed) in sdhci_msm_check_power_status()
1515 msm_offset->core_generics); in sdhci_msm_check_power_status()
1522 * The IRQ for request type IO High/LOW will be generated when - in sdhci_msm_check_power_status()
1525 * which indicates 3.3V IO voltage. So, when MMC core layer tries in sdhci_msm_check_power_status()
1527 * IRQ doesn't get triggered as there is no state change in this bit. in sdhci_msm_check_power_status()
1530 * for host->pwr to handle a case where IO voltage high request is in sdhci_msm_check_power_status()
1533 if ((req_type & REQ_IO_HIGH) && !host->pwr) { in sdhci_msm_check_power_status()
1535 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1538 if ((req_type & msm_host->curr_pwr_state) || in sdhci_msm_check_power_status()
1539 (req_type & msm_host->curr_io_level)) in sdhci_msm_check_power_status()
1544 * In this case, no power irq will be triggerred and we should in sdhci_msm_check_power_status()
1548 if (!wait_event_timeout(msm_host->pwr_irq_wait, in sdhci_msm_check_power_status()
1549 msm_host->pwr_irq_flag, in sdhci_msm_check_power_status()
1551 dev_warn(&msm_host->pdev->dev, in sdhci_msm_check_power_status()
1553 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1555 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), in sdhci_msm_check_power_status()
1564 msm_host->offset; in sdhci_msm_dump_pwr_ctrl_regs()
1567 mmc_hostname(host->mmc), in sdhci_msm_dump_pwr_ctrl_regs()
1568 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), in sdhci_msm_dump_pwr_ctrl_regs()
1569 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), in sdhci_msm_dump_pwr_ctrl_regs()
1570 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); in sdhci_msm_dump_pwr_ctrl_regs()
1577 struct mmc_host *mmc = host->mmc; in sdhci_msm_handle_pwr_irq() local
1582 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_handle_pwr_irq()
1585 msm_offset->core_pwrctl_status); in sdhci_msm_handle_pwr_irq()
1589 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1599 msm_offset->core_pwrctl_status)) { in sdhci_msm_handle_pwr_irq()
1602 mmc_hostname(host->mmc), irq_status); in sdhci_msm_handle_pwr_irq()
1608 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1609 retry--; in sdhci_msm_handle_pwr_irq()
1624 ret = sdhci_msm_set_vmmc(mmc); in sdhci_msm_handle_pwr_irq()
1626 ret = sdhci_msm_set_vqmmc(msm_host, mmc, in sdhci_msm_handle_pwr_irq()
1647 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { in sdhci_msm_handle_pwr_irq()
1648 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios); in sdhci_msm_handle_pwr_irq()
1650 …dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x… in sdhci_msm_handle_pwr_irq()
1651 mmc_hostname(mmc), ret, in sdhci_msm_handle_pwr_irq()
1652 mmc->ios.signal_voltage, mmc->ios.vdd, in sdhci_msm_handle_pwr_irq()
1664 msm_offset->core_pwrctl_ctl); in sdhci_msm_handle_pwr_irq()
1670 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in sdhci_msm_handle_pwr_irq()
1683 config = readl_relaxed(host->ioaddr + in sdhci_msm_handle_pwr_irq()
1684 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1688 (msm_host->caps_0 & CORE_3_0V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1691 (msm_host->caps_0 & CORE_1_8V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1695 writel_relaxed(new_config, host->ioaddr + in sdhci_msm_handle_pwr_irq()
1696 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1700 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
1702 msm_host->curr_io_level = io_level; in sdhci_msm_handle_pwr_irq()
1704 dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n", in sdhci_msm_handle_pwr_irq()
1705 mmc_hostname(msm_host->mmc), __func__, irq, irq_status, in sdhci_msm_handle_pwr_irq()
1716 msm_host->pwr_irq_flag = 1; in sdhci_msm_pwr_irq()
1727 struct clk *core_clk = msm_host->bulk_clks[0].clk; in sdhci_msm_get_max_clock()
1738 * __sdhci_msm_set_clock - sdhci_msm clock control.
1749 * Keep actual_clock as zero - in __sdhci_msm_set_clock()
1750 * - since there is no divider used so no need of having actual_clock. in __sdhci_msm_set_clock()
1751 * - MSM controller uses SDCLK for data timeout calculation. If in __sdhci_msm_set_clock()
1752 * actual_clock is zero, host->clock is taken for calculation. in __sdhci_msm_set_clock()
1754 host->mmc->actual_clock = 0; in __sdhci_msm_set_clock()
1764 * clock with no divider value programmed. in __sdhci_msm_set_clock()
1770 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1777 msm_host->clk_rate = clock; in sdhci_msm_set_clock()
1802 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_msm_cqe_irq()
1806 static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery) in sdhci_msm_cqe_disable() argument
1808 struct sdhci_host *host = mmc_priv(mmc); in sdhci_msm_cqe_disable()
1814 * on 16-byte descriptors in 64bit mode. in sdhci_msm_cqe_disable()
1816 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_disable()
1817 host->desc_sz = 16; in sdhci_msm_cqe_disable()
1819 spin_lock_irqsave(&host->lock, flags); in sdhci_msm_cqe_disable()
1832 spin_unlock_irqrestore(&host->lock, flags); in sdhci_msm_cqe_disable()
1834 sdhci_cqe_disable(mmc, recovery); in sdhci_msm_cqe_disable()
1856 if (host->caps & SDHCI_CAN_64BIT) in sdhci_msm_cqe_add_host()
1857 host->alloc_desc_sz = 16; in sdhci_msm_cqe_add_host()
1866 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret); in sdhci_msm_cqe_add_host()
1870 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_msm_cqe_add_host()
1871 cq_host->ops = &sdhci_msm_cqhci_ops; in sdhci_msm_cqe_add_host()
1873 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_msm_cqe_add_host()
1875 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_msm_cqe_add_host()
1877 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n", in sdhci_msm_cqe_add_host()
1878 mmc_hostname(host->mmc), ret); in sdhci_msm_cqe_add_host()
1893 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_add_host()
1894 host->desc_sz = 12; in sdhci_msm_cqe_add_host()
1900 dev_info(&pdev->dev, "%s: CQE init: success\n", in sdhci_msm_cqe_add_host()
1901 mmc_hostname(host->mmc)); in sdhci_msm_cqe_add_host()
1928 if (host->pwr && (val & SDHCI_RESET_ALL)) in __sdhci_msm_check_write()
1935 msm_host->transfer_mode = val; in __sdhci_msm_check_write()
1938 if (!msm_host->use_cdr) in __sdhci_msm_check_write()
1940 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && in __sdhci_msm_check_write()
1950 msm_host->pwr_irq_flag = 0; in __sdhci_msm_check_write()
1966 writew_relaxed(val, host->ioaddr + reg); in sdhci_msm_writew()
1979 writeb_relaxed(val, host->ioaddr + reg); in sdhci_msm_writeb()
1987 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_set_regulator_caps() local
1988 struct regulator *supply = mmc->supply.vqmmc; in sdhci_msm_set_regulator_caps()
1990 struct sdhci_host *host = mmc_priv(mmc); in sdhci_msm_set_regulator_caps()
1991 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_set_regulator_caps()
1993 if (!IS_ERR(mmc->supply.vqmmc)) { in sdhci_msm_set_regulator_caps()
2001 mmc_hostname(mmc)); in sdhci_msm_set_regulator_caps()
2009 u32 io_level = msm_host->curr_io_level; in sdhci_msm_set_regulator_caps()
2011 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_regulator_caps()
2012 msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2021 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2023 msm_host->caps_0 |= caps; in sdhci_msm_set_regulator_caps()
2024 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps); in sdhci_msm_set_regulator_caps()
2029 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) in sdhci_msm_reset()
2030 cqhci_deactivate(host->mmc); in sdhci_msm_reset()
2038 ret = mmc_regulator_get_supply(msm_host->mmc); in sdhci_msm_register_vreg()
2047 static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc, in sdhci_msm_start_signal_voltage_switch() argument
2050 struct sdhci_host *host = mmc_priv(mmc); in sdhci_msm_start_signal_voltage_switch()
2057 if (host->version < SDHCI_SPEC_300) in sdhci_msm_start_signal_voltage_switch()
2062 switch (ios->signal_voltage) { in sdhci_msm_start_signal_voltage_switch()
2064 if (!(host->flags & SDHCI_SIGNALING_330)) in sdhci_msm_start_signal_voltage_switch()
2065 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2071 if (!(host->flags & SDHCI_SIGNALING_180)) in sdhci_msm_start_signal_voltage_switch()
2072 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2079 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2093 dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n", in sdhci_msm_start_signal_voltage_switch()
2094 mmc_hostname(mmc)); in sdhci_msm_start_signal_voltage_switch()
2096 return -EAGAIN; in sdhci_msm_start_signal_voltage_switch()
2101 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2107 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_dump_vendor_regs()
2109 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n"); in sdhci_msm_dump_vendor_regs()
2113 readl_relaxed(host->ioaddr + msm_offset->core_dll_status), in sdhci_msm_dump_vendor_regs()
2114 readl_relaxed(host->ioaddr + msm_offset->core_dll_config), in sdhci_msm_dump_vendor_regs()
2115 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2)); in sdhci_msm_dump_vendor_regs()
2118 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3), in sdhci_msm_dump_vendor_regs()
2119 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl), in sdhci_msm_dump_vendor_regs()
2120 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config)); in sdhci_msm_dump_vendor_regs()
2123 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec), in sdhci_msm_dump_vendor_regs()
2124 readl_relaxed(host->ioaddr + in sdhci_msm_dump_vendor_regs()
2125 msm_offset->core_vendor_spec_func2), in sdhci_msm_dump_vendor_regs()
2126 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3)); in sdhci_msm_dump_vendor_regs()
2165 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2166 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2167 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2168 {.compatible = "qcom,sm8250-sdhci", .data = &sm8250_sdhci_var},
2169 {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2202 struct device_node *node = pdev->dev.of_node; in sdhci_msm_get_of_property()
2206 if (of_property_read_u32(node, "qcom,ddr-config", in sdhci_msm_get_of_property()
2207 &msm_host->ddr_config)) in sdhci_msm_get_of_property()
2208 msm_host->ddr_config = DDR_CONFIG_POR_VAL; in sdhci_msm_get_of_property()
2210 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config); in sdhci_msm_get_of_property()
2226 struct device_node *node = pdev->dev.of_node; in sdhci_msm_probe()
2232 host->sdma_boundary = 0; in sdhci_msm_probe()
2235 msm_host->mmc = host->mmc; in sdhci_msm_probe()
2236 msm_host->pdev = pdev; in sdhci_msm_probe()
2238 ret = mmc_of_parse(host->mmc); in sdhci_msm_probe()
2246 var_info = of_device_get_match_data(&pdev->dev); in sdhci_msm_probe()
2248 msm_host->mci_removed = var_info->mci_removed; in sdhci_msm_probe()
2249 msm_host->restore_dll_config = var_info->restore_dll_config; in sdhci_msm_probe()
2250 msm_host->var_ops = var_info->var_ops; in sdhci_msm_probe()
2251 msm_host->offset = var_info->offset; in sdhci_msm_probe()
2252 msm_host->uses_tassadar_dll = var_info->uses_tassadar_dll; in sdhci_msm_probe()
2254 msm_offset = msm_host->offset; in sdhci_msm_probe()
2259 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; in sdhci_msm_probe()
2262 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); in sdhci_msm_probe()
2263 if (!IS_ERR(msm_host->bus_clk)) { in sdhci_msm_probe()
2265 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); in sdhci_msm_probe()
2268 ret = clk_prepare_enable(msm_host->bus_clk); in sdhci_msm_probe()
2274 clk = devm_clk_get(&pdev->dev, "iface"); in sdhci_msm_probe()
2277 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2280 msm_host->bulk_clks[1].clk = clk; in sdhci_msm_probe()
2282 /* Setup SDC MMC clock */ in sdhci_msm_probe()
2283 clk = devm_clk_get(&pdev->dev, "core"); in sdhci_msm_probe()
2286 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2289 msm_host->bulk_clks[0].clk = clk; in sdhci_msm_probe()
2292 ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); in sdhci_msm_probe()
2296 msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core"); in sdhci_msm_probe()
2297 if (IS_ERR(msm_host->opp_table)) { in sdhci_msm_probe()
2298 ret = PTR_ERR(msm_host->opp_table); in sdhci_msm_probe()
2303 ret = dev_pm_opp_of_add_table(&pdev->dev); in sdhci_msm_probe()
2304 if (ret && ret != -ENODEV) { in sdhci_msm_probe()
2305 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); in sdhci_msm_probe()
2310 ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX); in sdhci_msm_probe()
2312 dev_warn(&pdev->dev, "core clock boost failed\n"); in sdhci_msm_probe()
2314 clk = devm_clk_get(&pdev->dev, "cal"); in sdhci_msm_probe()
2317 msm_host->bulk_clks[2].clk = clk; in sdhci_msm_probe()
2319 clk = devm_clk_get(&pdev->dev, "sleep"); in sdhci_msm_probe()
2322 msm_host->bulk_clks[3].clk = clk; in sdhci_msm_probe()
2324 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2325 msm_host->bulk_clks); in sdhci_msm_probe()
2333 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); in sdhci_msm_probe()
2334 if (IS_ERR(msm_host->xo_clk)) { in sdhci_msm_probe()
2335 ret = PTR_ERR(msm_host->xo_clk); in sdhci_msm_probe()
2336 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); in sdhci_msm_probe()
2339 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2340 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1); in sdhci_msm_probe()
2341 if (IS_ERR(msm_host->core_mem)) { in sdhci_msm_probe()
2342 ret = PTR_ERR(msm_host->core_mem); in sdhci_msm_probe()
2349 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_probe()
2351 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2354 msm_offset->core_hc_mode); in sdhci_msm_probe()
2356 msm_offset->core_hc_mode); in sdhci_msm_probe()
2359 msm_offset->core_hc_mode); in sdhci_msm_probe()
2362 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); in sdhci_msm_probe()
2363 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", in sdhci_msm_probe()
2368 msm_offset->core_mci_version); in sdhci_msm_probe()
2372 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", in sdhci_msm_probe()
2376 msm_host->use_14lpp_dll_reset = true; in sdhci_msm_probe()
2383 msm_host->use_cdclp533 = true; in sdhci_msm_probe()
2390 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); in sdhci_msm_probe()
2392 writel_relaxed(config, host->ioaddr + in sdhci_msm_probe()
2393 msm_offset->core_vendor_spec_capabilities0); in sdhci_msm_probe()
2397 msm_host->updated_ddr_cfg = true; in sdhci_msm_probe()
2419 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); in sdhci_msm_probe()
2420 if (msm_host->pwr_irq < 0) { in sdhci_msm_probe()
2421 ret = msm_host->pwr_irq; in sdhci_msm_probe()
2428 msm_offset->core_pwrctl_mask); in sdhci_msm_probe()
2430 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, in sdhci_msm_probe()
2432 dev_name(&pdev->dev), host); in sdhci_msm_probe()
2434 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); in sdhci_msm_probe()
2438 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_msm_probe()
2440 pm_runtime_get_noresume(&pdev->dev); in sdhci_msm_probe()
2441 pm_runtime_set_active(&pdev->dev); in sdhci_msm_probe()
2442 pm_runtime_enable(&pdev->dev); in sdhci_msm_probe()
2443 pm_runtime_set_autosuspend_delay(&pdev->dev, in sdhci_msm_probe()
2445 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_msm_probe()
2447 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_msm_probe()
2449 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; in sdhci_msm_probe()
2450 if (of_property_read_bool(node, "supports-cqe")) in sdhci_msm_probe()
2457 pm_runtime_mark_last_busy(&pdev->dev); in sdhci_msm_probe()
2458 pm_runtime_put_autosuspend(&pdev->dev); in sdhci_msm_probe()
2463 pm_runtime_disable(&pdev->dev); in sdhci_msm_probe()
2464 pm_runtime_set_suspended(&pdev->dev); in sdhci_msm_probe()
2465 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_probe()
2467 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2468 msm_host->bulk_clks); in sdhci_msm_probe()
2470 dev_pm_opp_of_remove_table(&pdev->dev); in sdhci_msm_probe()
2472 dev_pm_opp_put_clkname(msm_host->opp_table); in sdhci_msm_probe()
2474 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_probe()
2475 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_probe()
2486 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == in sdhci_msm_remove()
2491 dev_pm_opp_of_remove_table(&pdev->dev); in sdhci_msm_remove()
2492 dev_pm_opp_put_clkname(msm_host->opp_table); in sdhci_msm_remove()
2493 pm_runtime_get_sync(&pdev->dev); in sdhci_msm_remove()
2494 pm_runtime_disable(&pdev->dev); in sdhci_msm_remove()
2495 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_remove()
2497 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_remove()
2498 msm_host->bulk_clks); in sdhci_msm_remove()
2499 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_remove()
2500 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_remove()
2513 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_suspend()
2514 msm_host->bulk_clks); in sdhci_msm_runtime_suspend()
2526 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_resume()
2527 msm_host->bulk_clks); in sdhci_msm_runtime_resume()
2531 * Whenever core-clock is gated dynamically, it's needed to in sdhci_msm_runtime_resume()
2534 if (msm_host->restore_dll_config && msm_host->clk_rate) in sdhci_msm_runtime_resume()
2537 dev_pm_opp_set_rate(dev, msm_host->clk_rate); in sdhci_msm_runtime_resume()