Lines Matching +full:0 +full:x240a
20 STATE_IDLE = 0,
31 EVENT_CMD_COMPLETE = 0,
46 TRANS_MODE_PIO = 0,
123 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
256 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
270 #define DW_MMC_240A 0x240a
271 #define DW_MMC_280A 0x280a
273 #define SDMMC_CTRL 0x000
274 #define SDMMC_PWREN 0x004
275 #define SDMMC_CLKDIV 0x008
276 #define SDMMC_CLKSRC 0x00c
277 #define SDMMC_CLKENA 0x010
278 #define SDMMC_TMOUT 0x014
279 #define SDMMC_CTYPE 0x018
280 #define SDMMC_BLKSIZ 0x01c
281 #define SDMMC_BYTCNT 0x020
282 #define SDMMC_INTMASK 0x024
283 #define SDMMC_CMDARG 0x028
284 #define SDMMC_CMD 0x02c
285 #define SDMMC_RESP0 0x030
286 #define SDMMC_RESP1 0x034
287 #define SDMMC_RESP2 0x038
288 #define SDMMC_RESP3 0x03c
289 #define SDMMC_MINTSTS 0x040
290 #define SDMMC_RINTSTS 0x044
291 #define SDMMC_STATUS 0x048
292 #define SDMMC_FIFOTH 0x04c
293 #define SDMMC_CDETECT 0x050
294 #define SDMMC_WRTPRT 0x054
295 #define SDMMC_GPIO 0x058
296 #define SDMMC_TCBCNT 0x05c
297 #define SDMMC_TBBCNT 0x060
298 #define SDMMC_DEBNCE 0x064
299 #define SDMMC_USRID 0x068
300 #define SDMMC_VERID 0x06c
301 #define SDMMC_HCON 0x070
302 #define SDMMC_UHS_REG 0x074
303 #define SDMMC_RST_N 0x078
304 #define SDMMC_BMOD 0x080
305 #define SDMMC_PLDMND 0x084
306 #define SDMMC_DBADDR 0x088
307 #define SDMMC_IDSTS 0x08c
308 #define SDMMC_IDINTEN 0x090
309 #define SDMMC_DSCADDR 0x094
310 #define SDMMC_BUFADDR 0x098
311 #define SDMMC_CDTHRCTL 0x100
312 #define SDMMC_UHS_REG_EXT 0x108
313 #define SDMMC_DDR_REG 0x10c
314 #define SDMMC_ENABLE_SHIFT 0x110
319 #define SDMMC_DBADDRL 0x088
320 #define SDMMC_DBADDRU 0x08c
321 #define SDMMC_IDSTS64 0x090
322 #define SDMMC_IDINTEN64 0x094
323 #define SDMMC_DSCADDRL 0x098
324 #define SDMMC_DSCADDRU 0x09c
325 #define SDMMC_BUFADDRL 0x0A0
326 #define SDMMC_BUFADDRU 0x0A4
330 * Lower than 2.40a : data register offest is 0x100
332 #define DATA_OFFSET 0x100
333 #define DATA_240A_OFFSET 0x200
350 #define SDMMC_CTRL_RESET BIT(0)
353 #define SDMMC_CLKEN_ENABLE BIT(0)
356 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
357 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
358 #define SDMMC_TMOUT_RESP_MSK 0xFF
361 #define SDMMC_CTYPE_4BIT BIT(0)
362 #define SDMMC_CTYPE_1BIT 0
381 #define SDMMC_INT_CD BIT(0)
382 #define SDMMC_INT_ERROR 0xbfc2
400 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
402 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
406 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
407 ((r) & 0xFFF) << 16 | \
408 ((t) & 0xFFF))
410 #define DMA_INTERFACE_IDMA (0x0)
411 #define DMA_INTERFACE_DWDMA (0x1)
412 #define DMA_INTERFACE_GDMA (0x2)
413 #define DMA_INTERFACE_NODMA (0x3)
414 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
415 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
416 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
417 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
425 #define SDMMC_IDMAC_INT_TI BIT(0)
429 #define SDMMC_IDMAC_SWRESET BIT(0)
431 #define SDMMC_RST_HWACTIVE 0x1
433 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
435 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
437 #define SDMMC_CARD_RD_THR_EN BIT(0)
440 #define SDMMC_UHS_18V BIT(0)
444 #define SDMMC_ENABLE_PHASE BIT(0)
533 #define DW_MMC_CARD_PRESENT 0