68 	 * Set the drive phase offset based on speed mode to achieve hold times.  in dw_mci_rk3288_set_ios()
94 		int phase;  in dw_mci_rk3288_set_ios()  local
97 		 * In almost all cases a 90 degree phase offset will provide  in dw_mci_rk3288_set_ios()
102 		phase = 90;  in dw_mci_rk3288_set_ios()
108 			 * bus width is 8 we need to double the phase offset  in dw_mci_rk3288_set_ios()
112 				phase = 180;  in dw_mci_rk3288_set_ios()
124 			phase = 180;  in dw_mci_rk3288_set_ios()
128 		clk_set_phase(priv->drv_clk, phase);  in dw_mci_rk3288_set_ios()
163 	/* Try each phase and extract good ranges */  in dw_mci_rk3288_execute_tuning()
213 		dev_info(host->dev, "All phases work, using default phase %d.",  in dw_mci_rk3288_execute_tuning()
230 		dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",  in dw_mci_rk3288_execute_tuning()
239 	dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",  in dw_mci_rk3288_execute_tuning()
249 	dev_info(host->dev, "Successfully tuned phase to %d\n",  in dw_mci_rk3288_execute_tuning()
274 	if (of_property_read_u32(np, "rockchip,default-sample-phase",  in dw_mci_rk3288_parse_dt()