Lines Matching +full:0 +full:x17
105 #define STMPE_ICR_LSB_GIM (1 << 0)
109 #define STMPE_SYS_CTRL_INT_HI (1 << 0)
114 #define STMPE801_ID 0x0108
117 #define STMPE801_REG_CHIP_ID 0x00
118 #define STMPE801_REG_VERSION_ID 0x02
119 #define STMPE801_REG_SYS_CTRL 0x04
120 #define STMPE801_REG_GPIO_INT_EN 0x08
121 #define STMPE801_REG_GPIO_INT_STA 0x09
122 #define STMPE801_REG_GPIO_MP_STA 0x10
123 #define STMPE801_REG_GPIO_SET_PIN 0x11
124 #define STMPE801_REG_GPIO_DIR 0x12
129 #define STMPE811_ID 0x0811
131 #define STMPE811_IRQ_TOUCH_DET 0
141 #define STMPE811_REG_CHIP_ID 0x00
142 #define STMPE811_REG_SYS_CTRL 0x03
143 #define STMPE811_REG_SYS_CTRL2 0x04
144 #define STMPE811_REG_SPI_CFG 0x08
145 #define STMPE811_REG_INT_CTRL 0x09
146 #define STMPE811_REG_INT_EN 0x0A
147 #define STMPE811_REG_INT_STA 0x0B
148 #define STMPE811_REG_GPIO_INT_EN 0x0C
149 #define STMPE811_REG_GPIO_INT_STA 0x0D
150 #define STMPE811_REG_GPIO_SET_PIN 0x10
151 #define STMPE811_REG_GPIO_CLR_PIN 0x11
152 #define STMPE811_REG_GPIO_MP_STA 0x12
153 #define STMPE811_REG_GPIO_DIR 0x13
154 #define STMPE811_REG_GPIO_ED 0x14
155 #define STMPE811_REG_GPIO_RE 0x15
156 #define STMPE811_REG_GPIO_FE 0x16
157 #define STMPE811_REG_GPIO_AF 0x17
161 #define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
169 #define STMPE1600_ID 0x0016
172 #define STMPE1600_REG_CHIP_ID 0x00
173 #define STMPE1600_REG_SYS_CTRL 0x03
174 #define STMPE1600_REG_IEGPIOR_LSB 0x08
175 #define STMPE1600_REG_IEGPIOR_MSB 0x09
176 #define STMPE1600_REG_ISGPIOR_LSB 0x0A
177 #define STMPE1600_REG_ISGPIOR_MSB 0x0B
178 #define STMPE1600_REG_GPMR_LSB 0x10
179 #define STMPE1600_REG_GPMR_MSB 0x11
180 #define STMPE1600_REG_GPSR_LSB 0x12
181 #define STMPE1600_REG_GPSR_MSB 0x13
182 #define STMPE1600_REG_GPDR_LSB 0x14
183 #define STMPE1600_REG_GPDR_MSB 0x15
184 #define STMPE1600_REG_GPPIR_LSB 0x16
185 #define STMPE1600_REG_GPPIR_MSB 0x17
198 #define STMPE1601_IRQ_WAKEUP 0
201 #define STMPE1601_REG_SYS_CTRL 0x02
202 #define STMPE1601_REG_SYS_CTRL2 0x03
203 #define STMPE1601_REG_ICR_MSB 0x10
204 #define STMPE1601_REG_ICR_LSB 0x11
205 #define STMPE1601_REG_IER_MSB 0x12
206 #define STMPE1601_REG_IER_LSB 0x13
207 #define STMPE1601_REG_ISR_MSB 0x14
208 #define STMPE1601_REG_ISR_LSB 0x15
209 #define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16
210 #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
211 #define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
212 #define STMPE1601_REG_INT_STA_GPIO_LSB 0x19
213 #define STMPE1601_REG_CHIP_ID 0x80
214 #define STMPE1601_REG_GPIO_SET_MSB 0x82
215 #define STMPE1601_REG_GPIO_SET_LSB 0x83
216 #define STMPE1601_REG_GPIO_CLR_MSB 0x84
217 #define STMPE1601_REG_GPIO_CLR_LSB 0x85
218 #define STMPE1601_REG_GPIO_MP_MSB 0x86
219 #define STMPE1601_REG_GPIO_MP_LSB 0x87
220 #define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88
221 #define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
222 #define STMPE1601_REG_GPIO_ED_MSB 0x8A
223 #define STMPE1601_REG_GPIO_ED_LSB 0x8B
224 #define STMPE1601_REG_GPIO_RE_MSB 0x8C
225 #define STMPE1601_REG_GPIO_RE_LSB 0x8D
226 #define STMPE1601_REG_GPIO_FE_MSB 0x8E
227 #define STMPE1601_REG_GPIO_FE_LSB 0x8F
228 #define STMPE1601_REG_GPIO_PU_MSB 0x90
229 #define STMPE1601_REG_GPIO_PU_LSB 0x91
230 #define STMPE1601_REG_GPIO_AF_U_MSB 0x92
234 #define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)
237 #define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
243 #define STMPE1801_ID 0xc110
249 #define STMPE1801_IRQ_WAKEUP 0
251 #define STMPE1801_REG_CHIP_ID 0x00
252 #define STMPE1801_REG_SYS_CTRL 0x02
253 #define STMPE1801_REG_INT_CTRL_LOW 0x04
254 #define STMPE1801_REG_INT_EN_MASK_LOW 0x06
255 #define STMPE1801_REG_INT_STA_LOW 0x08
256 #define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A
257 #define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B
258 #define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C
259 #define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D
260 #define STMPE1801_REG_INT_STA_GPIO_MID 0x0E
261 #define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F
262 #define STMPE1801_REG_GPIO_SET_LOW 0x10
263 #define STMPE1801_REG_GPIO_SET_MID 0x11
264 #define STMPE1801_REG_GPIO_SET_HIGH 0x12
265 #define STMPE1801_REG_GPIO_CLR_LOW 0x13
266 #define STMPE1801_REG_GPIO_CLR_MID 0x14
267 #define STMPE1801_REG_GPIO_CLR_HIGH 0x15
268 #define STMPE1801_REG_GPIO_MP_LOW 0x16
269 #define STMPE1801_REG_GPIO_MP_MID 0x17
270 #define STMPE1801_REG_GPIO_MP_HIGH 0x18
271 #define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19
272 #define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A
273 #define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B
274 #define STMPE1801_REG_GPIO_RE_LOW 0x1C
275 #define STMPE1801_REG_GPIO_RE_MID 0x1D
276 #define STMPE1801_REG_GPIO_RE_HIGH 0x1E
277 #define STMPE1801_REG_GPIO_FE_LOW 0x1F
278 #define STMPE1801_REG_GPIO_FE_MID 0x20
279 #define STMPE1801_REG_GPIO_FE_HIGH 0x21
280 #define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22
281 #define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
282 #define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
299 #define STMPE24XX_IRQ_WAKEUP 0
302 #define STMPE24XX_REG_SYS_CTRL 0x02
303 #define STMPE24XX_REG_SYS_CTRL2 0x03
304 #define STMPE24XX_REG_ICR_MSB 0x10
305 #define STMPE24XX_REG_ICR_LSB 0x11
306 #define STMPE24XX_REG_IER_MSB 0x12
307 #define STMPE24XX_REG_IER_LSB 0x13
308 #define STMPE24XX_REG_ISR_MSB 0x14
309 #define STMPE24XX_REG_ISR_LSB 0x15
310 #define STMPE24XX_REG_IEGPIOR_MSB 0x16
311 #define STMPE24XX_REG_IEGPIOR_CSB 0x17
312 #define STMPE24XX_REG_IEGPIOR_LSB 0x18
313 #define STMPE24XX_REG_ISGPIOR_MSB 0x19
314 #define STMPE24XX_REG_ISGPIOR_CSB 0x1A
315 #define STMPE24XX_REG_ISGPIOR_LSB 0x1B
316 #define STMPE24XX_REG_CHIP_ID 0x80
317 #define STMPE24XX_REG_GPSR_MSB 0x83
318 #define STMPE24XX_REG_GPSR_CSB 0x84
319 #define STMPE24XX_REG_GPSR_LSB 0x85
320 #define STMPE24XX_REG_GPCR_MSB 0x86
321 #define STMPE24XX_REG_GPCR_CSB 0x87
322 #define STMPE24XX_REG_GPCR_LSB 0x88
323 #define STMPE24XX_REG_GPDR_MSB 0x89
324 #define STMPE24XX_REG_GPDR_CSB 0x8A
325 #define STMPE24XX_REG_GPDR_LSB 0x8B
326 #define STMPE24XX_REG_GPEDR_MSB 0x8C
327 #define STMPE24XX_REG_GPEDR_CSB 0x8D
328 #define STMPE24XX_REG_GPEDR_LSB 0x8E
329 #define STMPE24XX_REG_GPRER_MSB 0x8F
330 #define STMPE24XX_REG_GPRER_CSB 0x90
331 #define STMPE24XX_REG_GPRER_LSB 0x91
332 #define STMPE24XX_REG_GPFER_MSB 0x92
333 #define STMPE24XX_REG_GPFER_CSB 0x93
334 #define STMPE24XX_REG_GPFER_LSB 0x94
335 #define STMPE24XX_REG_GPPUR_MSB 0x95
336 #define STMPE24XX_REG_GPPUR_CSB 0x96
337 #define STMPE24XX_REG_GPPUR_LSB 0x97
338 #define STMPE24XX_REG_GPPDR_MSB 0x98
339 #define STMPE24XX_REG_GPPDR_CSB 0x99
340 #define STMPE24XX_REG_GPPDR_LSB 0x9A
341 #define STMPE24XX_REG_GPAFR_U_MSB 0x9B
342 #define STMPE24XX_REG_GPMR_MSB 0xA2
343 #define STMPE24XX_REG_GPMR_CSB 0xA3
344 #define STMPE24XX_REG_GPMR_LSB 0xA4
348 #define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0)