Lines Matching +full:0 +full:x200
36 .id = 0x00,
40 .id = 0x01,
44 .reg = 0x228,
48 .reg = 0x2e8,
49 .shift = 0,
50 .mask = 0xff,
51 .def = 0x4e,
54 .id = 0x02,
58 .reg = 0x228,
62 .reg = 0x2f4,
63 .shift = 0,
64 .mask = 0xff,
65 .def = 0x4e,
68 .id = 0x03,
72 .reg = 0x228,
76 .reg = 0x2e8,
78 .mask = 0xff,
79 .def = 0x4e,
82 .id = 0x04,
86 .reg = 0x228,
90 .reg = 0x2f4,
92 .mask = 0xff,
93 .def = 0x4e,
96 .id = 0x05,
100 .reg = 0x228,
104 .reg = 0x2ec,
105 .shift = 0,
106 .mask = 0xff,
107 .def = 0x4e,
110 .id = 0x06,
114 .reg = 0x228,
118 .reg = 0x2f8,
119 .shift = 0,
120 .mask = 0xff,
121 .def = 0x4e,
124 .id = 0x07,
128 .reg = 0x228,
132 .reg = 0x2ec,
134 .mask = 0xff,
135 .def = 0x4e,
138 .id = 0x08,
142 .reg = 0x228,
146 .reg = 0x2f8,
148 .mask = 0xff,
149 .def = 0x4e,
152 .id = 0x09,
156 .reg = 0x228,
160 .reg = 0x300,
161 .shift = 0,
162 .mask = 0xff,
163 .def = 0x17,
166 .id = 0x0a,
170 .reg = 0x228,
174 .reg = 0x308,
175 .shift = 0,
176 .mask = 0xff,
177 .def = 0x09,
180 .id = 0x0b,
184 .reg = 0x228,
188 .reg = 0x308,
190 .mask = 0xff,
191 .def = 0x09,
194 .id = 0x0c,
198 .reg = 0x228,
202 .reg = 0x328,
203 .shift = 0,
204 .mask = 0xff,
205 .def = 0x50,
208 .id = 0x0d,
212 .reg = 0x228,
216 .reg = 0x364,
217 .shift = 0,
218 .mask = 0xff,
219 .def = 0x2c,
222 .id = 0x0e,
226 .reg = 0x228,
230 .reg = 0x2e0,
231 .shift = 0,
232 .mask = 0xff,
233 .def = 0x10,
236 .id = 0x0f,
240 .reg = 0x228,
244 .reg = 0x2e4,
245 .shift = 0,
246 .mask = 0xff,
247 .def = 0x04,
250 .id = 0x10,
254 .reg = 0x228,
258 .reg = 0x2f0,
259 .shift = 0,
260 .mask = 0xff,
261 .def = 0xff,
264 .id = 0x11,
268 .reg = 0x228,
272 .reg = 0x2fc,
273 .shift = 0,
274 .mask = 0xff,
275 .def = 0xff,
278 .id = 0x12,
282 .reg = 0x228,
286 .reg = 0x334,
287 .shift = 0,
288 .mask = 0xff,
289 .def = 0x0a,
292 .id = 0x13,
296 .reg = 0x228,
300 .reg = 0x33c,
301 .shift = 0,
302 .mask = 0xff,
303 .def = 0x0a,
306 .id = 0x14,
310 .reg = 0x228,
314 .reg = 0x30c,
315 .shift = 0,
316 .mask = 0xff,
317 .def = 0x0a,
320 .id = 0x15,
324 .reg = 0x228,
328 .reg = 0x318,
329 .shift = 0,
330 .mask = 0xff,
331 .def = 0xff,
334 .id = 0x16,
338 .reg = 0x228,
342 .reg = 0x310,
343 .shift = 0,
344 .mask = 0xff,
345 .def = 0x05,
348 .id = 0x17,
352 .reg = 0x228,
356 .reg = 0x310,
358 .mask = 0xff,
359 .def = 0x50,
362 .id = 0x18,
366 .reg = 0x228,
370 .reg = 0x334,
372 .mask = 0xff,
373 .def = 0x13,
376 .id = 0x19,
380 .reg = 0x228,
384 .reg = 0x33c,
386 .mask = 0xff,
387 .def = 0x13,
390 .id = 0x1a,
394 .reg = 0x228,
398 .reg = 0x328,
400 .mask = 0xff,
401 .def = 0x80,
404 .id = 0x1b,
408 .reg = 0x228,
412 .reg = 0x32c,
413 .shift = 0,
414 .mask = 0xff,
415 .def = 0x42,
418 .id = 0x1c,
422 .reg = 0x228,
426 .reg = 0x32c,
428 .mask = 0xff,
429 .def = 0xff,
432 .id = 0x1d,
436 .reg = 0x228,
440 .reg = 0x344,
441 .shift = 0,
442 .mask = 0xff,
443 .def = 0x10,
446 .id = 0x1e,
450 .reg = 0x228,
454 .reg = 0x344,
456 .mask = 0xff,
457 .def = 0x12,
460 .id = 0x1f,
464 .reg = 0x228,
468 .reg = 0x350,
469 .shift = 0,
470 .mask = 0xff,
471 .def = 0x33,
474 .id = 0x20,
478 .reg = 0x22c,
479 .bit = 0,
482 .reg = 0x338,
483 .shift = 0,
484 .mask = 0xff,
485 .def = 0x13,
488 .id = 0x21,
492 .reg = 0x22c,
496 .reg = 0x340,
497 .shift = 0,
498 .mask = 0xff,
499 .def = 0x13,
502 .id = 0x22,
506 .reg = 0x22c,
510 .reg = 0x354,
511 .shift = 0,
512 .mask = 0xff,
513 .def = 0xff,
516 .id = 0x23,
520 .reg = 0x22c,
524 .reg = 0x354,
526 .mask = 0xff,
527 .def = 0xd0,
530 .id = 0x24,
534 .reg = 0x22c,
538 .reg = 0x358,
539 .shift = 0,
540 .mask = 0xff,
541 .def = 0x2a,
544 .id = 0x25,
548 .reg = 0x22c,
552 .reg = 0x358,
554 .mask = 0xff,
555 .def = 0x74,
558 .id = 0x26,
562 .reg = 0x324,
563 .shift = 0,
564 .mask = 0xff,
565 .def = 0x04,
568 .id = 0x27,
572 .reg = 0x320,
573 .shift = 0,
574 .mask = 0xff,
575 .def = 0x04,
578 .id = 0x28,
582 .reg = 0x22c,
586 .reg = 0x300,
588 .mask = 0xff,
589 .def = 0x6c,
592 .id = 0x29,
596 .reg = 0x22c,
600 .reg = 0x304,
601 .shift = 0,
602 .mask = 0xff,
603 .def = 0x6c,
606 .id = 0x2a,
610 .reg = 0x22c,
614 .reg = 0x304,
616 .mask = 0xff,
617 .def = 0x6c,
620 .id = 0x2b,
624 .reg = 0x22c,
628 .reg = 0x330,
629 .shift = 0,
630 .mask = 0xff,
631 .def = 0x13,
634 .id = 0x2c,
638 .reg = 0x22c,
642 .reg = 0x364,
644 .mask = 0xff,
645 .def = 0x12,
648 .id = 0x2d,
652 .reg = 0x22c,
656 .reg = 0x368,
657 .shift = 0,
658 .mask = 0xff,
659 .def = 0xb2,
662 .id = 0x2e,
666 .reg = 0x22c,
670 .reg = 0x368,
672 .mask = 0xff,
673 .def = 0xb2,
676 .id = 0x2f,
680 .reg = 0x22c,
684 .reg = 0x36c,
685 .shift = 0,
686 .mask = 0xff,
687 .def = 0x12,
690 .id = 0x30,
694 .reg = 0x22c,
698 .reg = 0x30c,
700 .mask = 0xff,
701 .def = 0x9,
704 .id = 0x31,
708 .reg = 0x22c,
712 .reg = 0x2e0,
714 .mask = 0xff,
715 .def = 0x0c,
718 .id = 0x32,
722 .reg = 0x22c,
726 .reg = 0x2e4,
728 .mask = 0xff,
729 .def = 0x0e,
732 .id = 0x33,
736 .reg = 0x22c,
740 .reg = 0x338,
742 .mask = 0xff,
743 .def = 0x0a,
746 .id = 0x34,
750 .reg = 0x22c,
754 .reg = 0x340,
756 .mask = 0xff,
757 .def = 0x0a,
760 .id = 0x35,
764 .reg = 0x22c,
768 .reg = 0x318,
770 .mask = 0xff,
771 .def = 0xff,
774 .id = 0x36,
778 .reg = 0x22c,
782 .reg = 0x314,
783 .shift = 0,
784 .mask = 0xff,
785 .def = 0x10,
788 .id = 0x37,
792 .reg = 0x22c,
796 .reg = 0x31c,
797 .shift = 0,
798 .mask = 0xff,
799 .def = 0xff,
802 .id = 0x38,
806 .reg = 0x324,
808 .mask = 0xff,
809 .def = 0x0e,
812 .id = 0x39,
816 .reg = 0x320,
818 .mask = 0xff,
819 .def = 0x0e,
822 .id = 0x3a,
826 .reg = 0x22c,
830 .reg = 0x330,
832 .mask = 0xff,
833 .def = 0xff,
836 .id = 0x3b,
840 .reg = 0x22c,
844 .reg = 0x348,
845 .shift = 0,
846 .mask = 0xff,
847 .def = 0x10,
850 .id = 0x3c,
854 .reg = 0x22c,
858 .reg = 0x348,
860 .mask = 0xff,
861 .def = 0x06,
864 .id = 0x3d,
868 .reg = 0x22c,
872 .reg = 0x350,
874 .mask = 0xff,
875 .def = 0x33,
878 .id = 0x3e,
882 .reg = 0x22c,
886 .reg = 0x35c,
887 .shift = 0,
888 .mask = 0xff,
889 .def = 0xff,
892 .id = 0x3f,
896 .reg = 0x22c,
900 .reg = 0x35c,
902 .mask = 0xff,
903 .def = 0xff,
906 .id = 0x40,
910 .reg = 0x230,
911 .bit = 0,
914 .reg = 0x360,
915 .shift = 0,
916 .mask = 0xff,
917 .def = 0x42,
920 .id = 0x41,
924 .reg = 0x230,
928 .reg = 0x360,
930 .mask = 0xff,
931 .def = 0x2a,
937 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
938 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
939 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
940 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
941 { .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
942 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
943 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
944 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
945 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
946 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
947 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
948 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
949 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
950 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
951 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
952 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
994 TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
995 TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
996 TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
997 TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
998 TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
999 TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
1000 TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
1001 TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
1002 TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
1003 TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
1004 TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1005 TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
1006 TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
1007 TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
1008 TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
1009 TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
1010 TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
1011 TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),
1019 .client_id_mask = 0x7f,