Lines Matching +full:timing +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
31 #define EMC_INTSTATUS 0x000
32 #define EMC_INTMASK 0x004
33 #define EMC_DBG 0x008
34 #define EMC_CFG 0x00c
35 #define EMC_REFCTRL 0x020
36 #define EMC_TIMING_CONTROL 0x028
37 #define EMC_RC 0x02c
38 #define EMC_RFC 0x030
39 #define EMC_RAS 0x034
40 #define EMC_RP 0x038
41 #define EMC_R2W 0x03c
42 #define EMC_W2R 0x040
43 #define EMC_R2P 0x044
44 #define EMC_W2P 0x048
45 #define EMC_RD_RCD 0x04c
46 #define EMC_WR_RCD 0x050
47 #define EMC_RRD 0x054
48 #define EMC_REXT 0x058
49 #define EMC_WDV 0x05c
50 #define EMC_QUSE 0x060
51 #define EMC_QRST 0x064
52 #define EMC_QSAFE 0x068
53 #define EMC_RDV 0x06c
54 #define EMC_REFRESH 0x070
55 #define EMC_BURST_REFRESH_NUM 0x074
56 #define EMC_PDEX2WR 0x078
57 #define EMC_PDEX2RD 0x07c
58 #define EMC_PCHG2PDEN 0x080
59 #define EMC_ACT2PDEN 0x084
60 #define EMC_AR2PDEN 0x088
61 #define EMC_RW2PDEN 0x08c
62 #define EMC_TXSR 0x090
63 #define EMC_TCKE 0x094
64 #define EMC_TFAW 0x098
65 #define EMC_TRPAB 0x09c
66 #define EMC_TCLKSTABLE 0x0a0
67 #define EMC_TCLKSTOP 0x0a4
68 #define EMC_TREFBW 0x0a8
69 #define EMC_QUSE_EXTRA 0x0ac
70 #define EMC_ODT_WRITE 0x0b0
71 #define EMC_ODT_READ 0x0b4
72 #define EMC_WEXT 0x0b8
73 #define EMC_CTT 0x0bc
74 #define EMC_MRS_WAIT_CNT 0x0c8
75 #define EMC_MRS 0x0cc
76 #define EMC_EMRS 0x0d0
77 #define EMC_SELF_REF 0x0e0
78 #define EMC_MRW 0x0e8
79 #define EMC_XM2DQSPADCTRL3 0x0f8
80 #define EMC_FBIO_SPARE 0x100
81 #define EMC_FBIO_CFG5 0x104
82 #define EMC_FBIO_CFG6 0x114
83 #define EMC_CFG_RSV 0x120
84 #define EMC_AUTO_CAL_CONFIG 0x2a4
85 #define EMC_AUTO_CAL_INTERVAL 0x2a8
86 #define EMC_AUTO_CAL_STATUS 0x2ac
87 #define EMC_STATUS 0x2b4
88 #define EMC_CFG_2 0x2b8
89 #define EMC_CFG_DIG_DLL 0x2bc
90 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
91 #define EMC_CTT_DURATION 0x2d8
92 #define EMC_CTT_TERM_CTRL 0x2dc
93 #define EMC_ZCAL_INTERVAL 0x2e0
94 #define EMC_ZCAL_WAIT_CNT 0x2e4
95 #define EMC_ZQ_CAL 0x2ec
96 #define EMC_XM2CMDPADCTRL 0x2f0
97 #define EMC_XM2DQSPADCTRL2 0x2fc
98 #define EMC_XM2DQPADCTRL2 0x304
99 #define EMC_XM2CLKPADCTRL 0x308
100 #define EMC_XM2COMPPADCTRL 0x30c
101 #define EMC_XM2VTTGENPADCTRL 0x310
102 #define EMC_XM2VTTGENPADCTRL2 0x314
103 #define EMC_XM2QUSEPADCTRL 0x318
104 #define EMC_DLL_XFORM_DQS0 0x328
105 #define EMC_DLL_XFORM_DQS1 0x32c
106 #define EMC_DLL_XFORM_DQS2 0x330
107 #define EMC_DLL_XFORM_DQS3 0x334
108 #define EMC_DLL_XFORM_DQS4 0x338
109 #define EMC_DLL_XFORM_DQS5 0x33c
110 #define EMC_DLL_XFORM_DQS6 0x340
111 #define EMC_DLL_XFORM_DQS7 0x344
112 #define EMC_DLL_XFORM_QUSE0 0x348
113 #define EMC_DLL_XFORM_QUSE1 0x34c
114 #define EMC_DLL_XFORM_QUSE2 0x350
115 #define EMC_DLL_XFORM_QUSE3 0x354
116 #define EMC_DLL_XFORM_QUSE4 0x358
117 #define EMC_DLL_XFORM_QUSE5 0x35c
118 #define EMC_DLL_XFORM_QUSE6 0x360
119 #define EMC_DLL_XFORM_QUSE7 0x364
120 #define EMC_DLL_XFORM_DQ0 0x368
121 #define EMC_DLL_XFORM_DQ1 0x36c
122 #define EMC_DLL_XFORM_DQ2 0x370
123 #define EMC_DLL_XFORM_DQ3 0x374
124 #define EMC_DLI_TRIM_TXDQS0 0x3a8
125 #define EMC_DLI_TRIM_TXDQS1 0x3ac
126 #define EMC_DLI_TRIM_TXDQS2 0x3b0
127 #define EMC_DLI_TRIM_TXDQS3 0x3b4
128 #define EMC_DLI_TRIM_TXDQS4 0x3b8
129 #define EMC_DLI_TRIM_TXDQS5 0x3bc
130 #define EMC_DLI_TRIM_TXDQS6 0x3c0
131 #define EMC_DLI_TRIM_TXDQS7 0x3c4
132 #define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8
133 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
134 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0
135 #define EMC_SEL_DPD_CTRL 0x3d8
136 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
137 #define EMC_DYN_SELF_REF_CONTROL 0x3e0
138 #define EMC_TXSRDLL 0x3e4
145 #define EMC_SELF_REF_CMD_ENABLED BIT(0)
147 #define DRAM_DEV_SEL_ALL (0 << 30)
153 #define EMC_ZQ_CAL_CMD BIT(0)
160 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
182 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
184 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK 0x3ff
187 (0x3ff << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
189 #define EMC_REFCTRL_DEV_SEL_MASK 0x3
192 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
193 #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
198 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
202 #define EMC_TIMING_UPDATE BIT(0)
221 [0] = EMC_RC,
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
372 return 0; in emc_seq_update_timing()
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
387 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
391 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
399 struct emc_timing *timing = NULL; in emc_find_timing() local
402 for (i = 0; i < emc->num_timings; i++) { in emc_find_timing()
403 if (emc->timings[i].rate >= rate) { in emc_find_timing()
404 timing = &emc->timings[i]; in emc_find_timing()
409 if (!timing) { in emc_find_timing()
410 dev_err(emc->dev, "no timing for rate %lu\n", rate); in emc_find_timing()
414 return timing; in emc_find_timing()
417 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
423 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { in emc_dqs_preset()
424 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
428 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
434 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { in emc_dqs_preset()
435 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
439 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
445 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { in emc_dqs_preset()
446 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
450 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
462 struct tegra_mc *mc = emc->mc; in emc_prepare_mc_clk_cfg()
467 for (i = 0; i < mc->num_timings; i++) { in emc_prepare_mc_clk_cfg()
468 if (mc->timings[i].rate != rate) in emc_prepare_mc_clk_cfg()
471 if (mc->timings[i].emem_data[misc0_index] & BIT(27)) in emc_prepare_mc_clk_cfg()
476 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same); in emc_prepare_mc_clk_cfg()
479 return -EINVAL; in emc_prepare_mc_clk_cfg()
484 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_prepare_timing_change() local
488 unsigned int pre_wait = 0; in emc_prepare_timing_change()
497 if (!timing || emc->bad_state) in emc_prepare_timing_change()
498 return -EINVAL; in emc_prepare_timing_change()
500 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
501 __func__, timing->rate, rate); in emc_prepare_timing_change()
503 emc->bad_state = true; in emc_prepare_timing_change()
507 dev_err(emc->dev, "mc clock preparation failed: %d\n", err); in emc_prepare_timing_change()
511 emc->vref_cal_toggle = false; in emc_prepare_timing_change()
512 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
513 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
514 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_prepare_timing_change()
516 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1)) in emc_prepare_timing_change()
518 else if (timing->emc_mode_1 & 0x1) in emc_prepare_timing_change()
523 emc->dll_on = !!(timing->emc_mode_1 & 0x1); in emc_prepare_timing_change()
525 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL)) in emc_prepare_timing_change()
526 emc->zcal_long = true; in emc_prepare_timing_change()
528 emc->zcal_long = false; in emc_prepare_timing_change()
530 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_prepare_timing_change()
533 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_prepare_timing_change()
535 /* disable dynamic self-refresh */ in emc_prepare_timing_change()
536 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
537 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
538 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
544 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
546 ((val & MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK) > 0x50)) { in emc_prepare_timing_change()
549 MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE | 0x50; in emc_prepare_timing_change()
550 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
551 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in emc_prepare_timing_change()
554 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK) in emc_prepare_timing_change()
555 mc_writel(emc->mc, in emc_prepare_timing_change()
556 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK, in emc_prepare_timing_change()
560 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) { in emc_prepare_timing_change()
573 /* disable auto-calibration if VREF mode is switching */ in emc_prepare_timing_change()
574 if (timing->emc_auto_cal_interval) { in emc_prepare_timing_change()
575 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL); in emc_prepare_timing_change()
576 val ^= timing->data[74]; in emc_prepare_timing_change()
579 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_prepare_timing_change()
582 emc->regs + EMC_AUTO_CAL_STATUS, val, in emc_prepare_timing_change()
585 dev_err(emc->dev, in emc_prepare_timing_change()
586 "auto-cal finish timeout: %d\n", err); in emc_prepare_timing_change()
590 emc->vref_cal_toggle = true; in emc_prepare_timing_change()
595 for (i = 0; i < ARRAY_SIZE(timing->data); i++) { in emc_prepare_timing_change()
598 writel_relaxed(timing->data[i], in emc_prepare_timing_change()
599 emc->regs + emc_timing_registers[i]); in emc_prepare_timing_change()
602 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate); in emc_prepare_timing_change()
610 if (emc->zcal_long) in emc_prepare_timing_change()
611 cnt -= dram_num * 256; in emc_prepare_timing_change()
613 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK; in emc_prepare_timing_change()
617 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; in emc_prepare_timing_change()
621 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT); in emc_prepare_timing_change()
625 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL); in emc_prepare_timing_change()
633 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK; in emc_prepare_timing_change()
644 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE); in emc_prepare_timing_change()
649 emc->regs + EMC_DBG); in emc_prepare_timing_change()
650 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
651 emc->regs + EMC_CFG); in emc_prepare_timing_change()
652 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
655 /* disable auto-refresh to save time after clock change */ in emc_prepare_timing_change()
657 emc->regs + EMC_REFCTRL); in emc_prepare_timing_change()
659 /* turn off DLL and enter self-refresh on DDR3 */ in emc_prepare_timing_change()
662 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
663 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
667 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
671 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); in emc_prepare_timing_change()
673 /* enable write-active MUX, update unshadowed pad control */ in emc_prepare_timing_change()
674 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
675 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL); in emc_prepare_timing_change()
677 /* restore periodic QRST and disable write-active MUX */ in emc_prepare_timing_change()
678 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
679 if (qrst_used || timing->emc_cfg_periodic_qrst != val) { in emc_prepare_timing_change()
680 if (timing->emc_cfg_periodic_qrst) in emc_prepare_timing_change()
681 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
683 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
685 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
687 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
689 /* exit self-refresh on DDR3 */ in emc_prepare_timing_change()
692 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
694 /* set DRAM-mode registers */ in emc_prepare_timing_change()
696 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
697 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
698 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
700 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
701 writel_relaxed(timing->emc_mode_2, in emc_prepare_timing_change()
702 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
704 if (timing->emc_mode_reset != emc->emc_mode_reset || in emc_prepare_timing_change()
706 val = timing->emc_mode_reset; in emc_prepare_timing_change()
713 writel_relaxed(val, emc->regs + EMC_MRS); in emc_prepare_timing_change()
716 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
717 writel_relaxed(timing->emc_mode_2, in emc_prepare_timing_change()
718 emc->regs + EMC_MRW); in emc_prepare_timing_change()
720 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
721 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
722 emc->regs + EMC_MRW); in emc_prepare_timing_change()
725 emc->emc_mode_1 = timing->emc_mode_1; in emc_prepare_timing_change()
726 emc->emc_mode_2 = timing->emc_mode_2; in emc_prepare_timing_change()
727 emc->emc_mode_reset = timing->emc_mode_reset; in emc_prepare_timing_change()
730 if (emc->zcal_long) { in emc_prepare_timing_change()
732 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
736 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
740 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE); in emc_prepare_timing_change()
746 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
748 return 0; in emc_prepare_timing_change()
754 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_complete_timing_change() local
759 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
763 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); in emc_complete_timing_change()
767 /* re-enable auto-refresh */ in emc_complete_timing_change()
768 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_complete_timing_change()
770 emc->regs + EMC_REFCTRL); in emc_complete_timing_change()
772 /* restore auto-calibration */ in emc_complete_timing_change()
773 if (emc->vref_cal_toggle) in emc_complete_timing_change()
774 writel_relaxed(timing->emc_auto_cal_interval, in emc_complete_timing_change()
775 emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_complete_timing_change()
777 /* restore dynamic self-refresh */ in emc_complete_timing_change()
778 if (timing->emc_cfg_dyn_self_ref) { in emc_complete_timing_change()
779 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE; in emc_complete_timing_change()
780 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
784 if (emc->zcal_long) in emc_complete_timing_change()
785 writel_relaxed(timing->emc_zcal_cnt_long, in emc_complete_timing_change()
786 emc->regs + EMC_ZCAL_WAIT_CNT); in emc_complete_timing_change()
791 /* update restored timing */ in emc_complete_timing_change()
794 emc->bad_state = false; in emc_complete_timing_change()
797 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE); in emc_complete_timing_change()
805 if (!emc->bad_state) { in emc_unprepare_timing_change()
807 dev_err(emc->dev, "timing configuration can't be reverted\n"); in emc_unprepare_timing_change()
808 emc->bad_state = true; in emc_unprepare_timing_change()
811 return 0; in emc_unprepare_timing_change()
827 disable_irq(emc->irq); in emc_clk_change_notify()
828 err = emc_prepare_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
829 enable_irq(emc->irq); in emc_clk_change_notify()
833 err = emc_unprepare_timing_change(emc, cnd->old_rate); in emc_clk_change_notify()
837 err = emc_complete_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
848 struct emc_timing *timing, in load_one_timing_from_dt() argument
854 err = of_property_read_u32(node, "clock-frequency", &value); in load_one_timing_from_dt()
856 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", in load_one_timing_from_dt()
861 timing->rate = value; in load_one_timing_from_dt()
863 err = of_property_read_u32_array(node, "nvidia,emc-configuration", in load_one_timing_from_dt()
864 timing->data, in load_one_timing_from_dt()
867 dev_err(emc->dev, in load_one_timing_from_dt()
868 "timing %pOF: failed to read emc timing data: %d\n", in load_one_timing_from_dt()
874 timing->prop = of_property_read_bool(node, dtprop); in load_one_timing_from_dt()
877 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
879 dev_err(emc->dev, \ in load_one_timing_from_dt()
880 "timing %pOFn: failed to read " #prop ": %d\n", \ in load_one_timing_from_dt()
885 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") in load_one_timing_from_dt()
886 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1") in load_one_timing_from_dt()
887 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2") in load_one_timing_from_dt()
888 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset") in load_one_timing_from_dt()
889 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") in load_one_timing_from_dt()
890 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref") in load_one_timing_from_dt()
891 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst") in load_one_timing_from_dt()
896 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate); in load_one_timing_from_dt()
898 return 0; in load_one_timing_from_dt()
906 if (a->rate < b->rate) in cmp_timings()
907 return -1; in cmp_timings()
909 if (a->rate > b->rate) in cmp_timings()
912 return 0; in cmp_timings()
917 struct tegra_mc *mc = emc->mc; in emc_check_mc_timings()
920 if (emc->num_timings != mc->num_timings) { in emc_check_mc_timings()
921 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n", in emc_check_mc_timings()
922 emc->num_timings, mc->num_timings); in emc_check_mc_timings()
923 return -EINVAL; in emc_check_mc_timings()
926 for (i = 0; i < mc->num_timings; i++) { in emc_check_mc_timings()
927 if (emc->timings[i].rate != mc->timings[i].rate) { in emc_check_mc_timings()
928 dev_err(emc->dev, in emc_check_mc_timings()
929 "emc/mc timing rate mismatch: %lu %lu\n", in emc_check_mc_timings()
930 emc->timings[i].rate, mc->timings[i].rate); in emc_check_mc_timings()
931 return -EINVAL; in emc_check_mc_timings()
935 return 0; in emc_check_mc_timings()
942 struct emc_timing *timing; in emc_load_timings_from_dt() local
948 dev_err(emc->dev, "no memory timings in: %pOF\n", node); in emc_load_timings_from_dt()
949 return -EINVAL; in emc_load_timings_from_dt()
952 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in emc_load_timings_from_dt()
954 if (!emc->timings) in emc_load_timings_from_dt()
955 return -ENOMEM; in emc_load_timings_from_dt()
957 emc->num_timings = child_count; in emc_load_timings_from_dt()
958 timing = emc->timings; in emc_load_timings_from_dt()
961 err = load_one_timing_from_dt(emc, timing++, child); in emc_load_timings_from_dt()
968 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in emc_load_timings_from_dt()
975 dev_info(emc->dev, in emc_load_timings_from_dt()
977 emc->num_timings, in emc_load_timings_from_dt()
979 emc->timings[0].rate / 1000000, in emc_load_timings_from_dt()
980 emc->timings[emc->num_timings - 1].rate / 1000000); in emc_load_timings_from_dt()
982 return 0; in emc_load_timings_from_dt()
993 for_each_child_of_node(dev->of_node, np) { in emc_find_node_by_ram_code()
994 err = of_property_read_u32(np, "nvidia,ram-code", &value); in emc_find_node_by_ram_code()
1001 dev_err(dev, "no memory timings for RAM code %u found in device-tree\n", in emc_find_node_by_ram_code()
1013 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
1016 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
1034 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
1037 writel_relaxed(intmask, emc->regs + EMC_INTMASK); in emc_setup_hw()
1038 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
1041 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
1046 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
1048 return 0; in emc_setup_hw()
1056 struct emc_timing *timing = NULL; in emc_round_rate() local
1060 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
1062 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
1063 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
1066 if (emc->timings[i].rate > max_rate) { in emc_round_rate()
1067 i = max(i, 1u) - 1; in emc_round_rate()
1069 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1073 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1076 timing = &emc->timings[i]; in emc_round_rate()
1080 if (!timing) { in emc_round_rate()
1081 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", in emc_round_rate()
1083 return -EINVAL; in emc_round_rate()
1086 return timing->rate; in emc_round_rate()
1093 * to control the EMC frequency. The top-level directory can be found here:
1099 * - available_rates: This file contains a list of valid, space-separated
1102 * - min_rate: Writing a value to this file sets the given frequency as the
1107 * - max_rate: Similarily to the min_rate file, writing a value to this file
1118 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1119 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1127 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show()
1131 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1132 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1138 return 0; in tegra_emc_debug_available_rates_show()
1145 inode->i_private); in tegra_emc_debug_available_rates_open()
1159 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1161 return 0; in tegra_emc_debug_min_rate_get()
1170 return -EINVAL; in tegra_emc_debug_min_rate_set()
1172 err = clk_set_min_rate(emc->clk, rate); in tegra_emc_debug_min_rate_set()
1173 if (err < 0) in tegra_emc_debug_min_rate_set()
1176 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1178 return 0; in tegra_emc_debug_min_rate_set()
1189 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1191 return 0; in tegra_emc_debug_max_rate_get()
1200 return -EINVAL; in tegra_emc_debug_max_rate_set()
1202 err = clk_set_max_rate(emc->clk, rate); in tegra_emc_debug_max_rate_set()
1203 if (err < 0) in tegra_emc_debug_max_rate_set()
1206 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1208 return 0; in tegra_emc_debug_max_rate_set()
1217 struct device *dev = emc->dev; in tegra_emc_debugfs_init()
1221 emc->debugfs.min_rate = ULONG_MAX; in tegra_emc_debugfs_init()
1222 emc->debugfs.max_rate = 0; in tegra_emc_debugfs_init()
1224 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
1225 if (emc->timings[i].rate < emc->debugfs.min_rate) in tegra_emc_debugfs_init()
1226 emc->debugfs.min_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1228 if (emc->timings[i].rate > emc->debugfs.max_rate) in tegra_emc_debugfs_init()
1229 emc->debugfs.max_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1232 if (!emc->num_timings) { in tegra_emc_debugfs_init()
1233 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra_emc_debugfs_init()
1234 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra_emc_debugfs_init()
1237 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra_emc_debugfs_init()
1238 emc->debugfs.max_rate); in tegra_emc_debugfs_init()
1239 if (err < 0) { in tegra_emc_debugfs_init()
1240 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in tegra_emc_debugfs_init()
1241 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra_emc_debugfs_init()
1242 emc->clk); in tegra_emc_debugfs_init()
1245 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra_emc_debugfs_init()
1246 if (!emc->debugfs.root) { in tegra_emc_debugfs_init()
1247 dev_err(emc->dev, "failed to create debugfs directory\n"); in tegra_emc_debugfs_init()
1251 debugfs_create_file("available_rates", 0444, emc->debugfs.root, in tegra_emc_debugfs_init()
1253 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1255 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1266 if (of_get_child_count(pdev->dev.of_node) == 0) { in tegra_emc_probe()
1267 dev_info(&pdev->dev, in tegra_emc_probe()
1268 "device-tree node doesn't have memory timings\n"); in tegra_emc_probe()
1269 return -ENODEV; in tegra_emc_probe()
1272 np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); in tegra_emc_probe()
1274 dev_err(&pdev->dev, "could not get memory controller node\n"); in tegra_emc_probe()
1275 return -ENOENT; in tegra_emc_probe()
1281 return -ENOENT; in tegra_emc_probe()
1283 np = emc_find_node_by_ram_code(&pdev->dev); in tegra_emc_probe()
1285 return -EINVAL; in tegra_emc_probe()
1287 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1290 return -ENOMEM; in tegra_emc_probe()
1293 emc->mc = platform_get_drvdata(mc); in tegra_emc_probe()
1294 if (!emc->mc) in tegra_emc_probe()
1295 return -EPROBE_DEFER; in tegra_emc_probe()
1297 emc->clk_nb.notifier_call = emc_clk_change_notify; in tegra_emc_probe()
1298 emc->dev = &pdev->dev; in tegra_emc_probe()
1305 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1306 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1307 return PTR_ERR(emc->regs); in tegra_emc_probe()
1313 err = platform_get_irq(pdev, 0); in tegra_emc_probe()
1314 if (err < 0) { in tegra_emc_probe()
1315 dev_err(&pdev->dev, "interrupt not specified: %d\n", err); in tegra_emc_probe()
1318 emc->irq = err; in tegra_emc_probe()
1320 err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0, in tegra_emc_probe()
1321 dev_name(&pdev->dev), emc); in tegra_emc_probe()
1323 dev_err(&pdev->dev, "failed to request irq: %d\n", err); in tegra_emc_probe()
1329 emc->clk = devm_clk_get(&pdev->dev, "emc"); in tegra_emc_probe()
1330 if (IS_ERR(emc->clk)) { in tegra_emc_probe()
1331 err = PTR_ERR(emc->clk); in tegra_emc_probe()
1332 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); in tegra_emc_probe()
1336 err = clk_notifier_register(emc->clk, &emc->clk_nb); in tegra_emc_probe()
1338 dev_err(&pdev->dev, "failed to register clk notifier: %d\n", in tegra_emc_probe()
1346 return 0; in tegra_emc_probe()
1360 err = clk_rate_exclusive_get(emc->clk); in tegra_emc_suspend()
1362 dev_err(emc->dev, "failed to acquire clk: %d\n", err); in tegra_emc_suspend()
1367 if (WARN(emc->bad_state, "hardware in a bad state\n")) in tegra_emc_suspend()
1368 return -EINVAL; in tegra_emc_suspend()
1370 emc->bad_state = true; in tegra_emc_suspend()
1372 return 0; in tegra_emc_suspend()
1380 emc->bad_state = false; in tegra_emc_resume()
1382 clk_rate_exclusive_put(emc->clk); in tegra_emc_resume()
1384 return 0; in tegra_emc_resume()
1393 { .compatible = "nvidia,tegra30-emc", },
1400 .name = "tegra30-emc",