Lines Matching full:emc
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
377 struct tegra_emc *emc = data; in tegra_emc_isr() local
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
387 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
391 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
396 static struct emc_timing *emc_find_timing(struct tegra_emc *emc, in emc_find_timing() argument
402 for (i = 0; i < emc->num_timings; i++) { in emc_find_timing()
403 if (emc->timings[i].rate >= rate) { in emc_find_timing()
404 timing = &emc->timings[i]; in emc_find_timing()
410 dev_err(emc->dev, "no timing for rate %lu\n", rate); in emc_find_timing()
417 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
424 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
428 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
435 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
439 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
446 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
450 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
460 static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate) in emc_prepare_mc_clk_cfg() argument
462 struct tegra_mc *mc = emc->mc; in emc_prepare_mc_clk_cfg()
476 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same); in emc_prepare_mc_clk_cfg()
482 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
484 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_prepare_timing_change()
497 if (!timing || emc->bad_state) in emc_prepare_timing_change()
500 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
503 emc->bad_state = true; in emc_prepare_timing_change()
505 err = emc_prepare_mc_clk_cfg(emc, rate); in emc_prepare_timing_change()
507 dev_err(emc->dev, "mc clock preparation failed: %d\n", err); in emc_prepare_timing_change()
511 emc->vref_cal_toggle = false; in emc_prepare_timing_change()
512 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
513 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
514 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_prepare_timing_change()
516 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1)) in emc_prepare_timing_change()
523 emc->dll_on = !!(timing->emc_mode_1 & 0x1); in emc_prepare_timing_change()
525 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL)) in emc_prepare_timing_change()
526 emc->zcal_long = true; in emc_prepare_timing_change()
528 emc->zcal_long = false; in emc_prepare_timing_change()
530 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_prepare_timing_change()
533 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_prepare_timing_change()
536 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
537 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
538 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
544 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
550 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
551 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in emc_prepare_timing_change()
554 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK) in emc_prepare_timing_change()
555 mc_writel(emc->mc, in emc_prepare_timing_change()
556 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK, in emc_prepare_timing_change()
560 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) { in emc_prepare_timing_change()
566 err = emc_seq_update_timing(emc); in emc_prepare_timing_change()
575 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL); in emc_prepare_timing_change()
579 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_prepare_timing_change()
582 emc->regs + EMC_AUTO_CAL_STATUS, val, in emc_prepare_timing_change()
585 dev_err(emc->dev, in emc_prepare_timing_change()
590 emc->vref_cal_toggle = true; in emc_prepare_timing_change()
599 emc->regs + emc_timing_registers[i]); in emc_prepare_timing_change()
602 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate); in emc_prepare_timing_change()
610 if (emc->zcal_long) in emc_prepare_timing_change()
621 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT); in emc_prepare_timing_change()
625 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL); in emc_prepare_timing_change()
644 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE); in emc_prepare_timing_change()
649 emc->regs + EMC_DBG); in emc_prepare_timing_change()
650 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
651 emc->regs + EMC_CFG); in emc_prepare_timing_change()
652 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
657 emc->regs + EMC_REFCTRL); in emc_prepare_timing_change()
663 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
667 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
671 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); in emc_prepare_timing_change()
674 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
675 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL); in emc_prepare_timing_change()
678 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
681 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
683 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
685 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
687 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
692 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
696 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
698 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
700 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
702 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
704 if (timing->emc_mode_reset != emc->emc_mode_reset || in emc_prepare_timing_change()
713 writel_relaxed(val, emc->regs + EMC_MRS); in emc_prepare_timing_change()
716 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
718 emc->regs + EMC_MRW); in emc_prepare_timing_change()
720 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
722 emc->regs + EMC_MRW); in emc_prepare_timing_change()
725 emc->emc_mode_1 = timing->emc_mode_1; in emc_prepare_timing_change()
726 emc->emc_mode_2 = timing->emc_mode_2; in emc_prepare_timing_change()
727 emc->emc_mode_reset = timing->emc_mode_reset; in emc_prepare_timing_change()
730 if (emc->zcal_long) { in emc_prepare_timing_change()
732 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
736 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
740 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE); in emc_prepare_timing_change()
743 * Read and discard an arbitrary MC register (Note: EMC registers in emc_prepare_timing_change()
746 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
751 static int emc_complete_timing_change(struct tegra_emc *emc, in emc_complete_timing_change() argument
754 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_complete_timing_change()
759 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
763 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); in emc_complete_timing_change()
768 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_complete_timing_change()
770 emc->regs + EMC_REFCTRL); in emc_complete_timing_change()
773 if (emc->vref_cal_toggle) in emc_complete_timing_change()
775 emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_complete_timing_change()
779 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE; in emc_complete_timing_change()
780 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
784 if (emc->zcal_long) in emc_complete_timing_change()
786 emc->regs + EMC_ZCAL_WAIT_CNT); in emc_complete_timing_change()
792 err = emc_seq_update_timing(emc); in emc_complete_timing_change()
794 emc->bad_state = false; in emc_complete_timing_change()
797 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE); in emc_complete_timing_change()
802 static int emc_unprepare_timing_change(struct tegra_emc *emc, in emc_unprepare_timing_change() argument
805 if (!emc->bad_state) { in emc_unprepare_timing_change()
807 dev_err(emc->dev, "timing configuration can't be reverted\n"); in emc_unprepare_timing_change()
808 emc->bad_state = true; in emc_unprepare_timing_change()
817 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); in emc_clk_change_notify() local
827 disable_irq(emc->irq); in emc_clk_change_notify()
828 err = emc_prepare_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
829 enable_irq(emc->irq); in emc_clk_change_notify()
833 err = emc_unprepare_timing_change(emc, cnd->old_rate); in emc_clk_change_notify()
837 err = emc_complete_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
847 static int load_one_timing_from_dt(struct tegra_emc *emc, in load_one_timing_from_dt() argument
856 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", in load_one_timing_from_dt()
863 err = of_property_read_u32_array(node, "nvidia,emc-configuration", in load_one_timing_from_dt()
867 dev_err(emc->dev, in load_one_timing_from_dt()
868 "timing %pOF: failed to read emc timing data: %d\n", in load_one_timing_from_dt()
879 dev_err(emc->dev, \ in load_one_timing_from_dt()
885 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") in load_one_timing_from_dt()
886 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1") in load_one_timing_from_dt()
887 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2") in load_one_timing_from_dt()
888 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset") in load_one_timing_from_dt()
889 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") in load_one_timing_from_dt()
890 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref") in load_one_timing_from_dt()
891 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst") in load_one_timing_from_dt()
896 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate); in load_one_timing_from_dt()
915 static int emc_check_mc_timings(struct tegra_emc *emc) in emc_check_mc_timings() argument
917 struct tegra_mc *mc = emc->mc; in emc_check_mc_timings()
920 if (emc->num_timings != mc->num_timings) { in emc_check_mc_timings()
921 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n", in emc_check_mc_timings()
922 emc->num_timings, mc->num_timings); in emc_check_mc_timings()
927 if (emc->timings[i].rate != mc->timings[i].rate) { in emc_check_mc_timings()
928 dev_err(emc->dev, in emc_check_mc_timings()
929 "emc/mc timing rate mismatch: %lu %lu\n", in emc_check_mc_timings()
930 emc->timings[i].rate, mc->timings[i].rate); in emc_check_mc_timings()
938 static int emc_load_timings_from_dt(struct tegra_emc *emc, in emc_load_timings_from_dt() argument
948 dev_err(emc->dev, "no memory timings in: %pOF\n", node); in emc_load_timings_from_dt()
952 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in emc_load_timings_from_dt()
954 if (!emc->timings) in emc_load_timings_from_dt()
957 emc->num_timings = child_count; in emc_load_timings_from_dt()
958 timing = emc->timings; in emc_load_timings_from_dt()
961 err = load_one_timing_from_dt(emc, timing++, child); in emc_load_timings_from_dt()
968 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in emc_load_timings_from_dt()
971 err = emc_check_mc_timings(emc); in emc_load_timings_from_dt()
975 dev_info(emc->dev, in emc_load_timings_from_dt()
977 emc->num_timings, in emc_load_timings_from_dt()
979 emc->timings[0].rate / 1000000, in emc_load_timings_from_dt()
980 emc->timings[emc->num_timings - 1].rate / 1000000); in emc_load_timings_from_dt()
1007 static int emc_setup_hw(struct tegra_emc *emc) in emc_setup_hw() argument
1013 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
1016 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
1018 /* enable EMC and CAR to handshake on PLL divider/source changes */ in emc_setup_hw()
1034 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
1037 writel_relaxed(intmask, emc->regs + EMC_INTMASK); in emc_setup_hw()
1038 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
1041 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
1046 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
1057 struct tegra_emc *emc = arg; in emc_round_rate() local
1060 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
1062 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
1063 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
1066 if (emc->timings[i].rate > max_rate) { in emc_round_rate()
1069 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1073 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1076 timing = &emc->timings[i]; in emc_round_rate()
1081 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", in emc_round_rate()
1093 * to control the EMC frequency. The top-level directory can be found here:
1095 * /sys/kernel/debug/emc
1100 * EMC frequencies.
1104 * configured EMC frequency, this will cause the frequency to be
1109 * the value is lower than the currently configured EMC frequency, this
1114 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
1118 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1119 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1127 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show() local
1131 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1132 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1157 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_get() local
1159 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1166 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_set() local
1169 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
1172 err = clk_set_min_rate(emc->clk, rate); in tegra_emc_debug_min_rate_set()
1176 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1187 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_get() local
1189 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1196 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_set() local
1199 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
1202 err = clk_set_max_rate(emc->clk, rate); in tegra_emc_debug_max_rate_set()
1206 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1215 static void tegra_emc_debugfs_init(struct tegra_emc *emc) in tegra_emc_debugfs_init() argument
1217 struct device *dev = emc->dev; in tegra_emc_debugfs_init()
1221 emc->debugfs.min_rate = ULONG_MAX; in tegra_emc_debugfs_init()
1222 emc->debugfs.max_rate = 0; in tegra_emc_debugfs_init()
1224 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
1225 if (emc->timings[i].rate < emc->debugfs.min_rate) in tegra_emc_debugfs_init()
1226 emc->debugfs.min_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1228 if (emc->timings[i].rate > emc->debugfs.max_rate) in tegra_emc_debugfs_init()
1229 emc->debugfs.max_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1232 if (!emc->num_timings) { in tegra_emc_debugfs_init()
1233 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra_emc_debugfs_init()
1234 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra_emc_debugfs_init()
1237 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra_emc_debugfs_init()
1238 emc->debugfs.max_rate); in tegra_emc_debugfs_init()
1241 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra_emc_debugfs_init()
1242 emc->clk); in tegra_emc_debugfs_init()
1245 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra_emc_debugfs_init()
1246 if (!emc->debugfs.root) { in tegra_emc_debugfs_init()
1247 dev_err(emc->dev, "failed to create debugfs directory\n"); in tegra_emc_debugfs_init()
1251 debugfs_create_file("available_rates", 0444, emc->debugfs.root, in tegra_emc_debugfs_init()
1252 emc, &tegra_emc_debug_available_rates_fops); in tegra_emc_debugfs_init()
1253 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1254 emc, &tegra_emc_debug_min_rate_fops); in tegra_emc_debugfs_init()
1255 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1256 emc, &tegra_emc_debug_max_rate_fops); in tegra_emc_debugfs_init()
1263 struct tegra_emc *emc; in tegra_emc_probe() local
1287 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1288 if (!emc) { in tegra_emc_probe()
1293 emc->mc = platform_get_drvdata(mc); in tegra_emc_probe()
1294 if (!emc->mc) in tegra_emc_probe()
1297 emc->clk_nb.notifier_call = emc_clk_change_notify; in tegra_emc_probe()
1298 emc->dev = &pdev->dev; in tegra_emc_probe()
1300 err = emc_load_timings_from_dt(emc, np); in tegra_emc_probe()
1305 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1306 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1307 return PTR_ERR(emc->regs); in tegra_emc_probe()
1309 err = emc_setup_hw(emc); in tegra_emc_probe()
1318 emc->irq = err; in tegra_emc_probe()
1320 err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0, in tegra_emc_probe()
1321 dev_name(&pdev->dev), emc); in tegra_emc_probe()
1327 tegra20_clk_set_emc_round_callback(emc_round_rate, emc); in tegra_emc_probe()
1329 emc->clk = devm_clk_get(&pdev->dev, "emc"); in tegra_emc_probe()
1330 if (IS_ERR(emc->clk)) { in tegra_emc_probe()
1331 err = PTR_ERR(emc->clk); in tegra_emc_probe()
1332 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); in tegra_emc_probe()
1336 err = clk_notifier_register(emc->clk, &emc->clk_nb); in tegra_emc_probe()
1343 platform_set_drvdata(pdev, emc); in tegra_emc_probe()
1344 tegra_emc_debugfs_init(emc); in tegra_emc_probe()
1356 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_suspend() local
1360 err = clk_rate_exclusive_get(emc->clk); in tegra_emc_suspend()
1362 dev_err(emc->dev, "failed to acquire clk: %d\n", err); in tegra_emc_suspend()
1367 if (WARN(emc->bad_state, "hardware in a bad state\n")) in tegra_emc_suspend()
1370 emc->bad_state = true; in tegra_emc_suspend()
1377 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_resume() local
1379 emc_setup_hw(emc); in tegra_emc_resume()
1380 emc->bad_state = false; in tegra_emc_resume()
1382 clk_rate_exclusive_put(emc->clk); in tegra_emc_resume()
1393 { .compatible = "nvidia,tegra30-emc", },
1400 .name = "tegra30-emc",