Lines Matching +full:reg +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
20 .reg = 0x228,
24 .reg = 0x2e8,
25 .shift = 0,
34 .reg = 0x228,
38 .reg = 0x2f4,
39 .shift = 0,
48 .reg = 0x228,
52 .reg = 0x2e8,
53 .shift = 16,
62 .reg = 0x228,
66 .reg = 0x2f4,
67 .shift = 16,
76 .reg = 0x228,
80 .reg = 0x2ec,
81 .shift = 0,
90 .reg = 0x228,
94 .reg = 0x2f8,
95 .shift = 0,
104 .reg = 0x228,
108 .reg = 0x2e0,
109 .shift = 0,
118 .reg = 0x228,
122 .reg = 0x2e4,
123 .shift = 0,
132 .reg = 0x228,
136 .reg = 0x2f0,
137 .shift = 0,
146 .reg = 0x228,
150 .reg = 0x2fc,
151 .shift = 0,
160 .reg = 0x228,
164 .reg = 0x318,
165 .shift = 0,
174 .reg = 0x228,
178 .reg = 0x310,
179 .shift = 0,
188 .reg = 0x228,
192 .reg = 0x310,
193 .shift = 16,
202 .reg = 0x228,
206 .reg = 0x328,
207 .shift = 0,
216 .reg = 0x228,
220 .reg = 0x344,
221 .shift = 0,
230 .reg = 0x228,
234 .reg = 0x344,
235 .shift = 16,
244 .reg = 0x228,
248 .reg = 0x350,
249 .shift = 0,
258 .reg = 0x320,
259 .shift = 0,
268 .reg = 0x22c,
272 .reg = 0x328,
273 .shift = 16,
282 .reg = 0x22c,
286 .reg = 0x2e0,
287 .shift = 16,
296 .reg = 0x22c,
300 .reg = 0x2e4,
301 .shift = 16,
310 .reg = 0x22c,
314 .reg = 0x318,
315 .shift = 16,
324 .reg = 0x22c,
328 .reg = 0x314,
329 .shift = 0,
338 .reg = 0x320,
339 .shift = 16,
348 .reg = 0x22c,
352 .reg = 0x348,
353 .shift = 0,
362 .reg = 0x22c,
366 .reg = 0x348,
367 .shift = 16,
376 .reg = 0x22c,
380 .reg = 0x350,
381 .shift = 16,
390 .reg = 0x230,
394 .reg = 0x370,
395 .shift = 0,
404 .reg = 0x230,
408 .reg = 0x374,
409 .shift = 0,
418 .reg = 0x230,
422 .reg = 0x374,
423 .shift = 16,
432 .reg = 0x230,
436 .reg = 0x37c,
437 .shift = 0,
446 .reg = 0x230,
450 .reg = 0x37c,
451 .shift = 16,
460 .reg = 0x230,
464 .reg = 0x380,
465 .shift = 0,
474 .reg = 0x230,
478 .reg = 0x380,
479 .shift = 16,
488 .reg = 0x230,
492 .reg = 0x384,
493 .shift = 0,
502 .reg = 0x230,
506 .reg = 0x388,
507 .shift = 0,
516 .reg = 0x230,
520 .reg = 0x388,
521 .shift = 16,
530 .reg = 0x230,
534 .reg = 0x390,
535 .shift = 0,
544 .reg = 0x230,
548 .reg = 0x390,
549 .shift = 16,
558 .reg = 0x230,
562 .reg = 0x3a4,
563 .shift = 0,
572 .reg = 0x230,
576 .reg = 0x3a4,
577 .shift = 16,
586 /* read-only */
587 .reg = 0x230,
591 .reg = 0x3c8,
592 .shift = 0,
601 /* read-only */
602 .reg = 0x230,
606 .reg = 0x3c8,
607 .shift = 16,
616 .reg = 0x230,
620 .reg = 0x2f0,
621 .shift = 16,
630 .reg = 0x234,
634 .reg = 0x3b8,
635 .shift = 0,
644 .reg = 0x234,
648 .reg = 0x3bc,
649 .shift = 0,
658 .reg = 0x234,
662 .reg = 0x3c0,
663 .shift = 0,
672 .reg = 0x234,
676 .reg = 0x3c4,
677 .shift = 0,
686 .reg = 0x234,
690 .reg = 0x3b8,
691 .shift = 16,
700 .reg = 0x234,
704 .reg = 0x3bc,
705 .shift = 16,
714 .reg = 0x234,
718 .reg = 0x3c0,
719 .shift = 16,
728 .reg = 0x234,
732 .reg = 0x3c4,
733 .shift = 16,
742 .reg = 0x234,
746 .reg = 0x394,
747 .shift = 0,
756 .reg = 0x234,
760 .reg = 0x394,
761 .shift = 16,
770 .reg = 0x234,
774 .reg = 0x398,
775 .shift = 0,
784 .reg = 0x234,
788 .reg = 0x3c8,
789 .shift = 0,
798 .reg = 0x234,
802 .reg = 0x3d8,
803 .shift = 0,
812 .reg = 0x234,
816 .reg = 0x3d8,
817 .shift = 16,
826 .reg = 0x234,
830 .reg = 0x3dc,
831 .shift = 0,
840 .reg = 0x234,
844 .reg = 0x3dc,
845 .shift = 16,
854 .reg = 0x234,
858 .reg = 0x3e4,
859 .shift = 0,
868 .reg = 0x234,
872 .reg = 0x3e4,
873 .shift = 16,
882 .reg = 0xb98,
886 .reg = 0x3e0,
887 .shift = 0,
896 .reg = 0xb98,
900 .reg = 0xb98,
901 .shift = 16,
910 .reg = 0xb98,
914 .reg = 0x3a0,
915 .shift = 0,
924 .reg = 0xb98,
928 .reg = 0x3a0,
929 .shift = 16,
938 .reg = 0xb98,
942 .reg = 0x3ec,
943 .shift = 0,
952 .reg = 0xb98,
956 .reg = 0x3ec,
957 .shift = 16,
966 .reg = 0xb98,
970 .reg = 0x3f0,
971 .shift = 0,
980 .reg = 0xb98,
984 .reg = 0x3f0,
985 .shift = 16,
994 /* read-only */
995 .reg = 0xb98,
999 .reg = 0x3e8,
1000 .shift = 0,
1009 /* read-only */
1010 .reg = 0xb98,
1014 .reg = 0x3e8,
1015 .shift = 16,
1023 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1024 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1025 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1026 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1027 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1028 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1029 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1030 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1031 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1032 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1033 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1034 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1035 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1036 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1037 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1038 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1039 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1040 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1041 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1042 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1043 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1044 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1045 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1046 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1047 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1048 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1049 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1050 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1051 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },