Lines Matching +full:0 +full:x200
12 .id = 0x00,
16 .id = 0x01,
20 .reg = 0x228,
24 .reg = 0x2e8,
25 .shift = 0,
26 .mask = 0xff,
27 .def = 0xc2,
30 .id = 0x02,
34 .reg = 0x228,
38 .reg = 0x2f4,
39 .shift = 0,
40 .mask = 0xff,
41 .def = 0xc6,
44 .id = 0x03,
48 .reg = 0x228,
52 .reg = 0x2e8,
54 .mask = 0xff,
55 .def = 0x50,
58 .id = 0x04,
62 .reg = 0x228,
66 .reg = 0x2f4,
68 .mask = 0xff,
69 .def = 0x50,
72 .id = 0x05,
76 .reg = 0x228,
80 .reg = 0x2ec,
81 .shift = 0,
82 .mask = 0xff,
83 .def = 0x50,
86 .id = 0x06,
90 .reg = 0x228,
94 .reg = 0x2f8,
95 .shift = 0,
96 .mask = 0xff,
97 .def = 0x50,
100 .id = 0x0e,
104 .reg = 0x228,
108 .reg = 0x2e0,
109 .shift = 0,
110 .mask = 0xff,
111 .def = 0x13,
114 .id = 0x0f,
118 .reg = 0x228,
122 .reg = 0x2e4,
123 .shift = 0,
124 .mask = 0xff,
125 .def = 0x04,
128 .id = 0x10,
132 .reg = 0x228,
136 .reg = 0x2f0,
137 .shift = 0,
138 .mask = 0xff,
139 .def = 0x50,
142 .id = 0x11,
146 .reg = 0x228,
150 .reg = 0x2fc,
151 .shift = 0,
152 .mask = 0xff,
153 .def = 0x50,
156 .id = 0x15,
160 .reg = 0x228,
164 .reg = 0x318,
165 .shift = 0,
166 .mask = 0xff,
167 .def = 0x24,
170 .id = 0x16,
174 .reg = 0x228,
178 .reg = 0x310,
179 .shift = 0,
180 .mask = 0xff,
181 .def = 0x1e,
184 .id = 0x17,
188 .reg = 0x228,
192 .reg = 0x310,
194 .mask = 0xff,
195 .def = 0x50,
198 .id = 0x1c,
202 .reg = 0x228,
206 .reg = 0x328,
207 .shift = 0,
208 .mask = 0xff,
209 .def = 0x23,
212 .id = 0x1d,
216 .reg = 0x228,
220 .reg = 0x344,
221 .shift = 0,
222 .mask = 0xff,
223 .def = 0x49,
226 .id = 0x1e,
230 .reg = 0x228,
234 .reg = 0x344,
236 .mask = 0xff,
237 .def = 0x1a,
240 .id = 0x1f,
244 .reg = 0x228,
248 .reg = 0x350,
249 .shift = 0,
250 .mask = 0xff,
251 .def = 0x65,
254 .id = 0x27,
258 .reg = 0x320,
259 .shift = 0,
260 .mask = 0xff,
261 .def = 0x04,
264 .id = 0x2b,
268 .reg = 0x22c,
272 .reg = 0x328,
274 .mask = 0xff,
275 .def = 0x80,
278 .id = 0x31,
282 .reg = 0x22c,
286 .reg = 0x2e0,
288 .mask = 0xff,
289 .def = 0x80,
292 .id = 0x32,
296 .reg = 0x22c,
300 .reg = 0x2e4,
302 .mask = 0xff,
303 .def = 0x80,
306 .id = 0x35,
310 .reg = 0x22c,
314 .reg = 0x318,
316 .mask = 0xff,
317 .def = 0x80,
320 .id = 0x36,
324 .reg = 0x22c,
328 .reg = 0x314,
329 .shift = 0,
330 .mask = 0xff,
331 .def = 0x80,
334 .id = 0x39,
338 .reg = 0x320,
340 .mask = 0xff,
341 .def = 0x80,
344 .id = 0x3b,
348 .reg = 0x22c,
352 .reg = 0x348,
353 .shift = 0,
354 .mask = 0xff,
355 .def = 0x80,
358 .id = 0x3c,
362 .reg = 0x22c,
366 .reg = 0x348,
368 .mask = 0xff,
369 .def = 0x80,
372 .id = 0x3d,
376 .reg = 0x22c,
380 .reg = 0x350,
382 .mask = 0xff,
383 .def = 0x65,
386 .id = 0x44,
390 .reg = 0x230,
394 .reg = 0x370,
395 .shift = 0,
396 .mask = 0xff,
397 .def = 0x18,
400 .id = 0x46,
404 .reg = 0x230,
408 .reg = 0x374,
409 .shift = 0,
410 .mask = 0xff,
411 .def = 0x80,
414 .id = 0x47,
418 .reg = 0x230,
422 .reg = 0x374,
424 .mask = 0xff,
425 .def = 0x80,
428 .id = 0x4a,
432 .reg = 0x230,
436 .reg = 0x37c,
437 .shift = 0,
438 .mask = 0xff,
439 .def = 0x7a,
442 .id = 0x4b,
446 .reg = 0x230,
450 .reg = 0x37c,
452 .mask = 0xff,
453 .def = 0x80,
456 .id = 0x4c,
460 .reg = 0x230,
464 .reg = 0x380,
465 .shift = 0,
466 .mask = 0xff,
467 .def = 0x39,
470 .id = 0x4d,
474 .reg = 0x230,
478 .reg = 0x380,
480 .mask = 0xff,
481 .def = 0x80,
484 .id = 0x4e,
488 .reg = 0x230,
492 .reg = 0x384,
493 .shift = 0,
494 .mask = 0xff,
495 .def = 0x18,
498 .id = 0x50,
502 .reg = 0x230,
506 .reg = 0x388,
507 .shift = 0,
508 .mask = 0xff,
509 .def = 0x80,
512 .id = 0x51,
516 .reg = 0x230,
520 .reg = 0x388,
522 .mask = 0xff,
523 .def = 0x80,
526 .id = 0x54,
530 .reg = 0x230,
534 .reg = 0x390,
535 .shift = 0,
536 .mask = 0xff,
537 .def = 0x9b,
540 .id = 0x55,
544 .reg = 0x230,
548 .reg = 0x390,
550 .mask = 0xff,
551 .def = 0x80,
554 .id = 0x56,
558 .reg = 0x230,
562 .reg = 0x3a4,
563 .shift = 0,
564 .mask = 0xff,
565 .def = 0x04,
568 .id = 0x57,
572 .reg = 0x230,
576 .reg = 0x3a4,
578 .mask = 0xff,
579 .def = 0x80,
582 .id = 0x58,
587 .reg = 0x230,
591 .reg = 0x3c8,
592 .shift = 0,
593 .mask = 0xff,
594 .def = 0x1a,
597 .id = 0x59,
602 .reg = 0x230,
606 .reg = 0x3c8,
608 .mask = 0xff,
609 .def = 0x80,
612 .id = 0x5a,
616 .reg = 0x230,
620 .reg = 0x2f0,
622 .mask = 0xff,
623 .def = 0x50,
626 .id = 0x60,
630 .reg = 0x234,
631 .bit = 0,
634 .reg = 0x3b8,
635 .shift = 0,
636 .mask = 0xff,
637 .def = 0x49,
640 .id = 0x61,
644 .reg = 0x234,
648 .reg = 0x3bc,
649 .shift = 0,
650 .mask = 0xff,
651 .def = 0x49,
654 .id = 0x62,
658 .reg = 0x234,
662 .reg = 0x3c0,
663 .shift = 0,
664 .mask = 0xff,
665 .def = 0x49,
668 .id = 0x63,
672 .reg = 0x234,
676 .reg = 0x3c4,
677 .shift = 0,
678 .mask = 0xff,
679 .def = 0x49,
682 .id = 0x64,
686 .reg = 0x234,
690 .reg = 0x3b8,
692 .mask = 0xff,
693 .def = 0x80,
696 .id = 0x65,
700 .reg = 0x234,
704 .reg = 0x3bc,
706 .mask = 0xff,
707 .def = 0x80,
710 .id = 0x66,
714 .reg = 0x234,
718 .reg = 0x3c0,
720 .mask = 0xff,
721 .def = 0x80,
724 .id = 0x67,
728 .reg = 0x234,
732 .reg = 0x3c4,
734 .mask = 0xff,
735 .def = 0x80,
738 .id = 0x6c,
742 .reg = 0x234,
746 .reg = 0x394,
747 .shift = 0,
748 .mask = 0xff,
749 .def = 0x1a,
752 .id = 0x6d,
756 .reg = 0x234,
760 .reg = 0x394,
762 .mask = 0xff,
763 .def = 0x80,
766 .id = 0x72,
770 .reg = 0x234,
774 .reg = 0x398,
775 .shift = 0,
776 .mask = 0xff,
777 .def = 0x80,
780 .id = 0x73,
784 .reg = 0x234,
788 .reg = 0x3c8,
789 .shift = 0,
790 .mask = 0xff,
791 .def = 0x50,
794 .id = 0x78,
798 .reg = 0x234,
802 .reg = 0x3d8,
803 .shift = 0,
804 .mask = 0xff,
805 .def = 0x23,
808 .id = 0x79,
812 .reg = 0x234,
816 .reg = 0x3d8,
818 .mask = 0xff,
819 .def = 0x80,
822 .id = 0x7a,
826 .reg = 0x234,
830 .reg = 0x3dc,
831 .shift = 0,
832 .mask = 0xff,
833 .def = 0xff,
836 .id = 0x7b,
840 .reg = 0x234,
844 .reg = 0x3dc,
846 .mask = 0xff,
847 .def = 0x80,
850 .id = 0x7e,
854 .reg = 0x234,
858 .reg = 0x3e4,
859 .shift = 0,
860 .mask = 0xff,
861 .def = 0x23,
864 .id = 0x7f,
868 .reg = 0x234,
872 .reg = 0x3e4,
874 .mask = 0xff,
875 .def = 0x80,
878 .id = 0x80,
882 .reg = 0xb98,
883 .bit = 0,
886 .reg = 0x3e0,
887 .shift = 0,
888 .mask = 0xff,
889 .def = 0x2e,
892 .id = 0x81,
896 .reg = 0xb98,
900 .reg = 0xb98,
902 .mask = 0xff,
903 .def = 0x80,
906 .id = 0x82,
910 .reg = 0xb98,
914 .reg = 0x3a0,
915 .shift = 0,
916 .mask = 0xff,
917 .def = 0xff,
920 .id = 0x83,
924 .reg = 0xb98,
928 .reg = 0x3a0,
930 .mask = 0xff,
931 .def = 0x80,
934 .id = 0x84,
938 .reg = 0xb98,
942 .reg = 0x3ec,
943 .shift = 0,
944 .mask = 0xff,
945 .def = 0xff,
948 .id = 0x85,
952 .reg = 0xb98,
956 .reg = 0x3ec,
958 .mask = 0xff,
959 .def = 0xff,
962 .id = 0x86,
966 .reg = 0xb98,
970 .reg = 0x3f0,
971 .shift = 0,
972 .mask = 0xff,
973 .def = 0x9b,
976 .id = 0x87,
980 .reg = 0xb98,
984 .reg = 0x3f0,
986 .mask = 0xff,
987 .def = 0x80,
990 .id = 0x88,
995 .reg = 0xb98,
999 .reg = 0x3e8,
1000 .shift = 0,
1001 .mask = 0xff,
1002 .def = 0x1a,
1005 .id = 0x89,
1010 .reg = 0xb98,
1014 .reg = 0x3e8,
1016 .mask = 0xff,
1017 .def = 0x80,
1023 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1024 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1025 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1026 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1027 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1028 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1029 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1030 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1031 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1032 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1033 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1034 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1035 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1036 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1037 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1038 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1039 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1040 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1041 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1042 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1043 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1044 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1045 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1046 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1047 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1048 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1049 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1050 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1051 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1090 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1091 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1092 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1093 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1094 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1095 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1096 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1097 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1098 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1099 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1100 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1101 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1102 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1103 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1104 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1105 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1106 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1107 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1108 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1109 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1110 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1111 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1112 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1113 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1114 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1115 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1116 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1117 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1118 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1119 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1127 .client_id_mask = 0xff,