Lines Matching +full:reg +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra124-mc.h>
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
51 .reg = 0x228,
55 .reg = 0x2e8,
56 .shift = 16,
65 .reg = 0x228,
69 .reg = 0x2f4,
70 .shift = 16,
79 .reg = 0x228,
83 .reg = 0x2ec,
84 .shift = 0,
93 .reg = 0x228,
97 .reg = 0x2f8,
98 .shift = 0,
107 .reg = 0x228,
111 .reg = 0x2e0,
112 .shift = 0,
121 .reg = 0x228,
125 .reg = 0x2e4,
126 .shift = 0,
135 .reg = 0x228,
139 .reg = 0x2f0,
140 .shift = 0,
149 .reg = 0x228,
153 .reg = 0x2fc,
154 .shift = 0,
163 .reg = 0x228,
167 .reg = 0x318,
168 .shift = 0,
177 .reg = 0x228,
181 .reg = 0x310,
182 .shift = 0,
191 .reg = 0x228,
195 .reg = 0x310,
196 .shift = 16,
205 .reg = 0x228,
209 .reg = 0x328,
210 .shift = 0,
219 .reg = 0x228,
223 .reg = 0x344,
224 .shift = 0,
233 .reg = 0x228,
237 .reg = 0x344,
238 .shift = 16,
247 .reg = 0x228,
251 .reg = 0x350,
252 .shift = 0,
261 .reg = 0x22c,
265 .reg = 0x354,
266 .shift = 0,
275 .reg = 0x22c,
279 .reg = 0x354,
280 .shift = 16,
289 .reg = 0x22c,
293 .reg = 0x358,
294 .shift = 0,
303 .reg = 0x22c,
307 .reg = 0x358,
308 .shift = 16,
317 .reg = 0x324,
318 .shift = 0,
327 .reg = 0x320,
328 .shift = 0,
337 .reg = 0x22c,
341 .reg = 0x328,
342 .shift = 16,
351 .reg = 0x22c,
355 .reg = 0x2e0,
356 .shift = 16,
365 .reg = 0x22c,
369 .reg = 0x2e4,
370 .shift = 16,
379 .reg = 0x22c,
383 .reg = 0x318,
384 .shift = 16,
393 .reg = 0x22c,
397 .reg = 0x314,
398 .shift = 0,
407 .reg = 0x324,
408 .shift = 16,
417 .reg = 0x320,
418 .shift = 16,
427 .reg = 0x22c,
431 .reg = 0x348,
432 .shift = 0,
441 .reg = 0x22c,
445 .reg = 0x348,
446 .shift = 16,
455 .reg = 0x22c,
459 .reg = 0x350,
460 .shift = 16,
469 .reg = 0x22c,
473 .reg = 0x35c,
474 .shift = 0,
483 .reg = 0x22c,
487 .reg = 0x35c,
488 .shift = 16,
497 .reg = 0x230,
501 .reg = 0x360,
502 .shift = 0,
511 .reg = 0x230,
515 .reg = 0x360,
516 .shift = 16,
525 .reg = 0x230,
529 .reg = 0x370,
530 .shift = 0,
539 .reg = 0x230,
543 .reg = 0x374,
544 .shift = 0,
553 .reg = 0x230,
557 .reg = 0x374,
558 .shift = 16,
567 .reg = 0x230,
571 .reg = 0x37c,
572 .shift = 0,
581 .reg = 0x230,
585 .reg = 0x37c,
586 .shift = 16,
595 .reg = 0x230,
599 .reg = 0x380,
600 .shift = 0,
609 .reg = 0x230,
613 .reg = 0x380,
614 .shift = 16,
623 .reg = 0x230,
627 .reg = 0x384,
628 .shift = 0,
637 .reg = 0x230,
641 .reg = 0x388,
642 .shift = 0,
651 .reg = 0x230,
655 .reg = 0x388,
656 .shift = 16,
665 .reg = 0x230,
669 .reg = 0x390,
670 .shift = 0,
679 .reg = 0x230,
683 .reg = 0x390,
684 .shift = 16,
693 .reg = 0x230,
697 .reg = 0x3a4,
698 .shift = 0,
707 .reg = 0x230,
711 .reg = 0x3a4,
712 .shift = 16,
721 /* read-only */
722 .reg = 0x230,
726 .reg = 0x3c8,
727 .shift = 0,
736 /* read-only */
737 .reg = 0x230,
741 .reg = 0x3c8,
742 .shift = 16,
751 .reg = 0x230,
755 .reg = 0x2f0,
756 .shift = 16,
765 .reg = 0x234,
769 .reg = 0x3b8,
770 .shift = 0,
779 .reg = 0x234,
783 .reg = 0x3bc,
784 .shift = 0,
793 .reg = 0x234,
797 .reg = 0x3c0,
798 .shift = 0,
807 .reg = 0x234,
811 .reg = 0x3c4,
812 .shift = 0,
821 .reg = 0x234,
825 .reg = 0x3b8,
826 .shift = 16,
835 .reg = 0x234,
839 .reg = 0x3bc,
840 .shift = 16,
849 .reg = 0x234,
853 .reg = 0x3c0,
854 .shift = 16,
863 .reg = 0x234,
867 .reg = 0x3c4,
868 .shift = 16,
877 .reg = 0x234,
881 .reg = 0x394,
882 .shift = 0,
891 .reg = 0x234,
895 .reg = 0x394,
896 .shift = 16,
905 .reg = 0x234,
909 .reg = 0x398,
910 .shift = 0,
919 .reg = 0x234,
923 .reg = 0x3c8,
924 .shift = 0,
932 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
933 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
934 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
935 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
936 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
937 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
938 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
939 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
940 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
941 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
942 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
943 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
944 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
945 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
946 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
947 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
948 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
949 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
950 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
951 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
952 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
953 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
954 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },