Lines Matching +full:0 +full:x200
15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0xc2,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
43 .mask = 0xff,
44 .def = 0xc6,
47 .id = 0x03,
51 .reg = 0x228,
55 .reg = 0x2e8,
57 .mask = 0xff,
58 .def = 0x50,
61 .id = 0x04,
65 .reg = 0x228,
69 .reg = 0x2f4,
71 .mask = 0xff,
72 .def = 0x50,
75 .id = 0x05,
79 .reg = 0x228,
83 .reg = 0x2ec,
84 .shift = 0,
85 .mask = 0xff,
86 .def = 0x50,
89 .id = 0x06,
93 .reg = 0x228,
97 .reg = 0x2f8,
98 .shift = 0,
99 .mask = 0xff,
100 .def = 0x50,
103 .id = 0x0e,
107 .reg = 0x228,
111 .reg = 0x2e0,
112 .shift = 0,
113 .mask = 0xff,
114 .def = 0x13,
117 .id = 0x0f,
121 .reg = 0x228,
125 .reg = 0x2e4,
126 .shift = 0,
127 .mask = 0xff,
128 .def = 0x04,
131 .id = 0x10,
135 .reg = 0x228,
139 .reg = 0x2f0,
140 .shift = 0,
141 .mask = 0xff,
142 .def = 0x50,
145 .id = 0x11,
149 .reg = 0x228,
153 .reg = 0x2fc,
154 .shift = 0,
155 .mask = 0xff,
156 .def = 0x50,
159 .id = 0x15,
163 .reg = 0x228,
167 .reg = 0x318,
168 .shift = 0,
169 .mask = 0xff,
170 .def = 0x24,
173 .id = 0x16,
177 .reg = 0x228,
181 .reg = 0x310,
182 .shift = 0,
183 .mask = 0xff,
184 .def = 0x1e,
187 .id = 0x17,
191 .reg = 0x228,
195 .reg = 0x310,
197 .mask = 0xff,
198 .def = 0x50,
201 .id = 0x1c,
205 .reg = 0x228,
209 .reg = 0x328,
210 .shift = 0,
211 .mask = 0xff,
212 .def = 0x23,
215 .id = 0x1d,
219 .reg = 0x228,
223 .reg = 0x344,
224 .shift = 0,
225 .mask = 0xff,
226 .def = 0x49,
229 .id = 0x1e,
233 .reg = 0x228,
237 .reg = 0x344,
239 .mask = 0xff,
240 .def = 0x1a,
243 .id = 0x1f,
247 .reg = 0x228,
251 .reg = 0x350,
252 .shift = 0,
253 .mask = 0xff,
254 .def = 0x65,
257 .id = 0x22,
261 .reg = 0x22c,
265 .reg = 0x354,
266 .shift = 0,
267 .mask = 0xff,
268 .def = 0x4f,
271 .id = 0x23,
275 .reg = 0x22c,
279 .reg = 0x354,
281 .mask = 0xff,
282 .def = 0x3d,
285 .id = 0x24,
289 .reg = 0x22c,
293 .reg = 0x358,
294 .shift = 0,
295 .mask = 0xff,
296 .def = 0x66,
299 .id = 0x25,
303 .reg = 0x22c,
307 .reg = 0x358,
309 .mask = 0xff,
310 .def = 0xa5,
313 .id = 0x26,
317 .reg = 0x324,
318 .shift = 0,
319 .mask = 0xff,
320 .def = 0x04,
323 .id = 0x27,
327 .reg = 0x320,
328 .shift = 0,
329 .mask = 0xff,
330 .def = 0x04,
333 .id = 0x2b,
337 .reg = 0x22c,
341 .reg = 0x328,
343 .mask = 0xff,
344 .def = 0x80,
347 .id = 0x31,
351 .reg = 0x22c,
355 .reg = 0x2e0,
357 .mask = 0xff,
358 .def = 0x80,
361 .id = 0x32,
365 .reg = 0x22c,
369 .reg = 0x2e4,
371 .mask = 0xff,
372 .def = 0x80,
375 .id = 0x35,
379 .reg = 0x22c,
383 .reg = 0x318,
385 .mask = 0xff,
386 .def = 0x80,
389 .id = 0x36,
393 .reg = 0x22c,
397 .reg = 0x314,
398 .shift = 0,
399 .mask = 0xff,
400 .def = 0x80,
403 .id = 0x38,
407 .reg = 0x324,
409 .mask = 0xff,
410 .def = 0x80,
413 .id = 0x39,
417 .reg = 0x320,
419 .mask = 0xff,
420 .def = 0x80,
423 .id = 0x3b,
427 .reg = 0x22c,
431 .reg = 0x348,
432 .shift = 0,
433 .mask = 0xff,
434 .def = 0x80,
437 .id = 0x3c,
441 .reg = 0x22c,
445 .reg = 0x348,
447 .mask = 0xff,
448 .def = 0x80,
451 .id = 0x3d,
455 .reg = 0x22c,
459 .reg = 0x350,
461 .mask = 0xff,
462 .def = 0x65,
465 .id = 0x3e,
469 .reg = 0x22c,
473 .reg = 0x35c,
474 .shift = 0,
475 .mask = 0xff,
476 .def = 0x80,
479 .id = 0x3f,
483 .reg = 0x22c,
487 .reg = 0x35c,
489 .mask = 0xff,
490 .def = 0x80,
493 .id = 0x40,
497 .reg = 0x230,
498 .bit = 0,
501 .reg = 0x360,
502 .shift = 0,
503 .mask = 0xff,
504 .def = 0x80,
507 .id = 0x41,
511 .reg = 0x230,
515 .reg = 0x360,
517 .mask = 0xff,
518 .def = 0x80,
521 .id = 0x44,
525 .reg = 0x230,
529 .reg = 0x370,
530 .shift = 0,
531 .mask = 0xff,
532 .def = 0x18,
535 .id = 0x46,
539 .reg = 0x230,
543 .reg = 0x374,
544 .shift = 0,
545 .mask = 0xff,
546 .def = 0x80,
549 .id = 0x47,
553 .reg = 0x230,
557 .reg = 0x374,
559 .mask = 0xff,
560 .def = 0x80,
563 .id = 0x4a,
567 .reg = 0x230,
571 .reg = 0x37c,
572 .shift = 0,
573 .mask = 0xff,
574 .def = 0x39,
577 .id = 0x4b,
581 .reg = 0x230,
585 .reg = 0x37c,
587 .mask = 0xff,
588 .def = 0x80,
591 .id = 0x4c,
595 .reg = 0x230,
599 .reg = 0x380,
600 .shift = 0,
601 .mask = 0xff,
602 .def = 0x39,
605 .id = 0x4d,
609 .reg = 0x230,
613 .reg = 0x380,
615 .mask = 0xff,
616 .def = 0x80,
619 .id = 0x4e,
623 .reg = 0x230,
627 .reg = 0x384,
628 .shift = 0,
629 .mask = 0xff,
630 .def = 0x18,
633 .id = 0x50,
637 .reg = 0x230,
641 .reg = 0x388,
642 .shift = 0,
643 .mask = 0xff,
644 .def = 0x80,
647 .id = 0x51,
651 .reg = 0x230,
655 .reg = 0x388,
657 .mask = 0xff,
658 .def = 0x80,
661 .id = 0x54,
665 .reg = 0x230,
669 .reg = 0x390,
670 .shift = 0,
671 .mask = 0xff,
672 .def = 0x9b,
675 .id = 0x55,
679 .reg = 0x230,
683 .reg = 0x390,
685 .mask = 0xff,
686 .def = 0x80,
689 .id = 0x56,
693 .reg = 0x230,
697 .reg = 0x3a4,
698 .shift = 0,
699 .mask = 0xff,
700 .def = 0x04,
703 .id = 0x57,
707 .reg = 0x230,
711 .reg = 0x3a4,
713 .mask = 0xff,
714 .def = 0x80,
717 .id = 0x58,
722 .reg = 0x230,
726 .reg = 0x3c8,
727 .shift = 0,
728 .mask = 0xff,
729 .def = 0x1a,
732 .id = 0x59,
737 .reg = 0x230,
741 .reg = 0x3c8,
743 .mask = 0xff,
744 .def = 0x80,
747 .id = 0x5a,
751 .reg = 0x230,
755 .reg = 0x2f0,
757 .mask = 0xff,
758 .def = 0x50,
761 .id = 0x60,
765 .reg = 0x234,
766 .bit = 0,
769 .reg = 0x3b8,
770 .shift = 0,
771 .mask = 0xff,
772 .def = 0x49,
775 .id = 0x61,
779 .reg = 0x234,
783 .reg = 0x3bc,
784 .shift = 0,
785 .mask = 0xff,
786 .def = 0x49,
789 .id = 0x62,
793 .reg = 0x234,
797 .reg = 0x3c0,
798 .shift = 0,
799 .mask = 0xff,
800 .def = 0x49,
803 .id = 0x63,
807 .reg = 0x234,
811 .reg = 0x3c4,
812 .shift = 0,
813 .mask = 0xff,
814 .def = 0x49,
817 .id = 0x64,
821 .reg = 0x234,
825 .reg = 0x3b8,
827 .mask = 0xff,
828 .def = 0x80,
831 .id = 0x65,
835 .reg = 0x234,
839 .reg = 0x3bc,
841 .mask = 0xff,
842 .def = 0x80,
845 .id = 0x66,
849 .reg = 0x234,
853 .reg = 0x3c0,
855 .mask = 0xff,
856 .def = 0x80,
859 .id = 0x67,
863 .reg = 0x234,
867 .reg = 0x3c4,
869 .mask = 0xff,
870 .def = 0x80,
873 .id = 0x6c,
877 .reg = 0x234,
881 .reg = 0x394,
882 .shift = 0,
883 .mask = 0xff,
884 .def = 0x1a,
887 .id = 0x6d,
891 .reg = 0x234,
895 .reg = 0x394,
897 .mask = 0xff,
898 .def = 0x80,
901 .id = 0x72,
905 .reg = 0x234,
909 .reg = 0x398,
910 .shift = 0,
911 .mask = 0xff,
912 .def = 0x80,
915 .id = 0x73,
919 .reg = 0x234,
923 .reg = 0x3c8,
924 .shift = 0,
925 .mask = 0xff,
926 .def = 0x50,
932 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
933 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
934 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
935 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
936 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
937 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
938 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
939 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
940 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
941 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
942 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
943 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
944 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
945 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
946 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
947 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
948 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
949 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
950 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
951 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
952 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
953 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
954 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
981 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
982 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
983 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
984 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
985 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
986 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
987 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
988 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
989 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
990 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
991 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
992 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
993 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
994 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
995 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
996 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
997 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
998 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
999 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1000 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1001 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1002 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1003 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1004 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1048 .client_id_mask = 0x7f,
1080 .client_id_mask = 0x7f,