Lines Matching +full:timing +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
25 #define EMC_FBIO_CFG5 0x104
26 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
27 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
29 #define EMC_INTSTATUS 0x0
32 #define EMC_CFG 0xc
37 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
40 #define EMC_REFCTRL 0x20
41 #define EMC_REFCTRL_DEV_SEL_SHIFT 0
44 #define EMC_TIMING_CONTROL 0x28
45 #define EMC_RC 0x2c
46 #define EMC_RFC 0x30
47 #define EMC_RAS 0x34
48 #define EMC_RP 0x38
49 #define EMC_R2W 0x3c
50 #define EMC_W2R 0x40
51 #define EMC_R2P 0x44
52 #define EMC_W2P 0x48
53 #define EMC_RD_RCD 0x4c
54 #define EMC_WR_RCD 0x50
55 #define EMC_RRD 0x54
56 #define EMC_REXT 0x58
57 #define EMC_WDV 0x5c
58 #define EMC_QUSE 0x60
59 #define EMC_QRST 0x64
60 #define EMC_QSAFE 0x68
61 #define EMC_RDV 0x6c
62 #define EMC_REFRESH 0x70
63 #define EMC_BURST_REFRESH_NUM 0x74
64 #define EMC_PDEX2WR 0x78
65 #define EMC_PDEX2RD 0x7c
66 #define EMC_PCHG2PDEN 0x80
67 #define EMC_ACT2PDEN 0x84
68 #define EMC_AR2PDEN 0x88
69 #define EMC_RW2PDEN 0x8c
70 #define EMC_TXSR 0x90
71 #define EMC_TCKE 0x94
72 #define EMC_TFAW 0x98
73 #define EMC_TRPAB 0x9c
74 #define EMC_TCLKSTABLE 0xa0
75 #define EMC_TCLKSTOP 0xa4
76 #define EMC_TREFBW 0xa8
77 #define EMC_ODT_WRITE 0xb0
78 #define EMC_ODT_READ 0xb4
79 #define EMC_WEXT 0xb8
80 #define EMC_CTT 0xbc
81 #define EMC_RFC_SLR 0xc0
82 #define EMC_MRS_WAIT_CNT2 0xc4
84 #define EMC_MRS_WAIT_CNT 0xc8
85 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
87 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
90 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
92 #define EMC_MRS 0xcc
95 #define EMC_EMRS 0xd0
96 #define EMC_REF 0xd4
97 #define EMC_PRE 0xd8
99 #define EMC_SELF_REF 0xe0
100 #define EMC_SELF_REF_CMD_ENABLED BIT(0)
103 #define EMC_MRW 0xe8
105 #define EMC_MRR 0xec
107 #define LPDDR2_MR4_TEMP_SHIFT 0
109 #define EMC_XM2DQSPADCTRL3 0xf8
110 #define EMC_FBIO_SPARE 0x100
112 #define EMC_FBIO_CFG6 0x114
113 #define EMC_EMRS2 0x12c
114 #define EMC_MRW2 0x134
115 #define EMC_MRW4 0x13c
116 #define EMC_EINPUT 0x14c
117 #define EMC_EINPUT_DURATION 0x150
118 #define EMC_PUTERM_EXTRA 0x154
119 #define EMC_TCKESR 0x158
120 #define EMC_TPD 0x15c
122 #define EMC_AUTO_CAL_CONFIG 0x2a4
124 #define EMC_AUTO_CAL_INTERVAL 0x2a8
125 #define EMC_AUTO_CAL_STATUS 0x2ac
127 #define EMC_STATUS 0x2b4
130 #define EMC_CFG_2 0x2b8
131 #define EMC_CFG_2_MODE_SHIFT 0
134 #define EMC_CFG_DIG_DLL 0x2bc
135 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
136 #define EMC_RDV_MASK 0x2cc
137 #define EMC_WDV_MASK 0x2d0
138 #define EMC_CTT_DURATION 0x2d8
139 #define EMC_CTT_TERM_CTRL 0x2dc
140 #define EMC_ZCAL_INTERVAL 0x2e0
141 #define EMC_ZCAL_WAIT_CNT 0x2e4
143 #define EMC_ZQ_CAL 0x2ec
144 #define EMC_ZQ_CAL_CMD BIT(0)
151 #define EMC_XM2CMDPADCTRL 0x2f0
152 #define EMC_XM2DQSPADCTRL 0x2f8
153 #define EMC_XM2DQSPADCTRL2 0x2fc
154 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0)
156 #define EMC_XM2DQPADCTRL 0x300
157 #define EMC_XM2DQPADCTRL2 0x304
158 #define EMC_XM2CLKPADCTRL 0x308
159 #define EMC_XM2COMPPADCTRL 0x30c
160 #define EMC_XM2VTTGENPADCTRL 0x310
161 #define EMC_XM2VTTGENPADCTRL2 0x314
162 #define EMC_XM2VTTGENPADCTRL3 0x318
163 #define EMC_XM2DQSPADCTRL4 0x320
164 #define EMC_DLL_XFORM_DQS0 0x328
165 #define EMC_DLL_XFORM_DQS1 0x32c
166 #define EMC_DLL_XFORM_DQS2 0x330
167 #define EMC_DLL_XFORM_DQS3 0x334
168 #define EMC_DLL_XFORM_DQS4 0x338
169 #define EMC_DLL_XFORM_DQS5 0x33c
170 #define EMC_DLL_XFORM_DQS6 0x340
171 #define EMC_DLL_XFORM_DQS7 0x344
172 #define EMC_DLL_XFORM_QUSE0 0x348
173 #define EMC_DLL_XFORM_QUSE1 0x34c
174 #define EMC_DLL_XFORM_QUSE2 0x350
175 #define EMC_DLL_XFORM_QUSE3 0x354
176 #define EMC_DLL_XFORM_QUSE4 0x358
177 #define EMC_DLL_XFORM_QUSE5 0x35c
178 #define EMC_DLL_XFORM_QUSE6 0x360
179 #define EMC_DLL_XFORM_QUSE7 0x364
180 #define EMC_DLL_XFORM_DQ0 0x368
181 #define EMC_DLL_XFORM_DQ1 0x36c
182 #define EMC_DLL_XFORM_DQ2 0x370
183 #define EMC_DLL_XFORM_DQ3 0x374
184 #define EMC_DLI_TRIM_TXDQS0 0x3a8
185 #define EMC_DLI_TRIM_TXDQS1 0x3ac
186 #define EMC_DLI_TRIM_TXDQS2 0x3b0
187 #define EMC_DLI_TRIM_TXDQS3 0x3b4
188 #define EMC_DLI_TRIM_TXDQS4 0x3b8
189 #define EMC_DLI_TRIM_TXDQS5 0x3bc
190 #define EMC_DLI_TRIM_TXDQS6 0x3c0
191 #define EMC_DLI_TRIM_TXDQS7 0x3c4
192 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
193 #define EMC_SEL_DPD_CTRL 0x3d8
200 ((0xf << 2) | BIT(8))
202 ((0x3 << 2) | BIT(5) | BIT(8))
203 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
204 #define EMC_DYN_SELF_REF_CONTROL 0x3e0
205 #define EMC_TXSRDLL 0x3e4
206 #define EMC_CCFIFO_ADDR 0x3e8
207 #define EMC_CCFIFO_DATA 0x3ec
208 #define EMC_CCFIFO_STATUS 0x3f0
209 #define EMC_CDB_CNTL_1 0x3f4
210 #define EMC_CDB_CNTL_2 0x3f8
211 #define EMC_XM2CLKPADCTRL2 0x3fc
212 #define EMC_AUTO_CAL_CONFIG2 0x458
213 #define EMC_AUTO_CAL_CONFIG3 0x45c
214 #define EMC_IBDLY 0x468
215 #define EMC_DLL_XFORM_ADDR0 0x46c
216 #define EMC_DLL_XFORM_ADDR1 0x470
217 #define EMC_DLL_XFORM_ADDR2 0x474
218 #define EMC_DSR_VTTGEN_DRV 0x47c
219 #define EMC_TXDSRVTTGEN 0x480
220 #define EMC_XM2CMDPADCTRL4 0x484
221 #define EMC_XM2CMDPADCTRL5 0x488
222 #define EMC_DLL_XFORM_DQS8 0x4a0
223 #define EMC_DLL_XFORM_DQS9 0x4a4
224 #define EMC_DLL_XFORM_DQS10 0x4a8
225 #define EMC_DLL_XFORM_DQS11 0x4ac
226 #define EMC_DLL_XFORM_DQS12 0x4b0
227 #define EMC_DLL_XFORM_DQS13 0x4b4
228 #define EMC_DLL_XFORM_DQS14 0x4b8
229 #define EMC_DLL_XFORM_DQS15 0x4bc
230 #define EMC_DLL_XFORM_QUSE8 0x4c0
231 #define EMC_DLL_XFORM_QUSE9 0x4c4
232 #define EMC_DLL_XFORM_QUSE10 0x4c8
233 #define EMC_DLL_XFORM_QUSE11 0x4cc
234 #define EMC_DLL_XFORM_QUSE12 0x4d0
235 #define EMC_DLL_XFORM_QUSE13 0x4d4
236 #define EMC_DLL_XFORM_QUSE14 0x4d8
237 #define EMC_DLL_XFORM_QUSE15 0x4dc
238 #define EMC_DLL_XFORM_DQ4 0x4e0
239 #define EMC_DLL_XFORM_DQ5 0x4e4
240 #define EMC_DLL_XFORM_DQ6 0x4e8
241 #define EMC_DLL_XFORM_DQ7 0x4ec
242 #define EMC_DLI_TRIM_TXDQS8 0x520
243 #define EMC_DLI_TRIM_TXDQS9 0x524
244 #define EMC_DLI_TRIM_TXDQS10 0x528
245 #define EMC_DLI_TRIM_TXDQS11 0x52c
246 #define EMC_DLI_TRIM_TXDQS12 0x530
247 #define EMC_DLI_TRIM_TXDQS13 0x534
248 #define EMC_DLI_TRIM_TXDQS14 0x538
249 #define EMC_DLI_TRIM_TXDQS15 0x53c
250 #define EMC_CDB_CNTL_3 0x540
251 #define EMC_XM2DQSPADCTRL5 0x544
252 #define EMC_XM2DQSPADCTRL6 0x548
253 #define EMC_XM2DQPADCTRL3 0x54c
254 #define EMC_DLL_XFORM_ADDR3 0x550
255 #define EMC_DLL_XFORM_ADDR4 0x554
256 #define EMC_DLL_XFORM_ADDR5 0x558
257 #define EMC_CFG_PIPE 0x560
258 #define EMC_QPOP 0x564
259 #define EMC_QUSE_WIDTH 0x568
260 #define EMC_PUTERM_WIDTH 0x56c
261 #define EMC_BGBIAS_CTL0 0x570
265 #define EMC_PUTERM_ADJ 0x574
267 #define DRAM_DEV_SEL_ALL 0
274 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
281 DRAM_TYPE_DDR3 = 0,
486 /* Timing change sequence functions */
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
502 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
504 if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0) in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
517 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
519 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { in emc_seq_disable_auto_cal()
520 value = readl(emc->regs + EMC_AUTO_CAL_STATUS); in emc_seq_disable_auto_cal()
521 if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0) in emc_seq_disable_auto_cal()
526 dev_err(emc->dev, "auto cal disable timed out\n"); in emc_seq_disable_auto_cal()
534 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { in emc_seq_wait_clkchange()
535 value = readl(emc->regs + EMC_INTSTATUS); in emc_seq_wait_clkchange()
541 dev_err(emc->dev, "clock change timed out\n"); in emc_seq_wait_clkchange()
547 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
550 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
551 if (emc->timings[i].rate == rate) { in tegra_emc_find_timing()
552 timing = &emc->timings[i]; in tegra_emc_find_timing()
557 if (!timing) { in tegra_emc_find_timing()
558 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
562 return timing; in tegra_emc_find_timing()
568 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change() local
569 struct emc_timing *last = &emc->last_timing; in tegra_emc_prepare_timing_change()
571 unsigned int pre_wait = 0; in tegra_emc_prepare_timing_change()
576 if (!timing) in tegra_emc_prepare_timing_change()
577 return -ENOENT; in tegra_emc_prepare_timing_change()
579 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
581 else if (timing->emc_mode_1 & 0x1) in tegra_emc_prepare_timing_change()
587 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
589 /* Disable dynamic self-refresh */ in tegra_emc_prepare_timing_change()
590 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
593 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
599 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
604 val = readl(emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
607 writel(val, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
611 val = readl(emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_prepare_timing_change()
612 val2 = last->emc_bgbias_ctl0; in tegra_emc_prepare_timing_change()
613 if (!(timing->emc_bgbias_ctl0 & in tegra_emc_prepare_timing_change()
626 writel(val2, emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_prepare_timing_change()
632 val = readl(emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
633 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && in tegra_emc_prepare_timing_change()
639 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && in tegra_emc_prepare_timing_change()
646 writel(val, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
658 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { in tegra_emc_prepare_timing_change()
660 writel(timing->emc_ctt_term_ctrl, in tegra_emc_prepare_timing_change()
661 emc->regs + EMC_CTT_TERM_CTRL); in tegra_emc_prepare_timing_change()
666 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) in tegra_emc_prepare_timing_change()
667 writel(timing->emc_burst_data[i], in tegra_emc_prepare_timing_change()
668 emc->regs + emc_burst_regs[i]); in tegra_emc_prepare_timing_change()
670 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
671 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
673 tegra_mc_write_emem_configuration(emc->mc, timing->rate); in tegra_emc_prepare_timing_change()
675 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
679 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) in tegra_emc_prepare_timing_change()
680 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, in tegra_emc_prepare_timing_change()
683 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) in tegra_emc_prepare_timing_change()
684 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, in tegra_emc_prepare_timing_change()
687 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { in tegra_emc_prepare_timing_change()
688 val = timing->emc_auto_cal_config; in tegra_emc_prepare_timing_change()
694 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_prepare_timing_change()
698 if (timing->emc_zcal_interval != 0 && in tegra_emc_prepare_timing_change()
699 last->emc_zcal_interval == 0) in tegra_emc_prepare_timing_change()
700 cnt -= emc->dram_num * 256; in tegra_emc_prepare_timing_change()
702 val = (timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
708 val = timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
713 writel(val, emc->regs + EMC_MRS_WAIT_CNT); in tegra_emc_prepare_timing_change()
716 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
720 /* DDR3: Turn off DLL and enter self-refresh */ in tegra_emc_prepare_timing_change()
721 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) in tegra_emc_prepare_timing_change()
722 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
725 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num), in tegra_emc_prepare_timing_change()
727 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
728 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) | in tegra_emc_prepare_timing_change()
735 /* DDR3: Exit self-refresh */ in tegra_emc_prepare_timing_change()
736 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
737 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num), in tegra_emc_prepare_timing_change()
739 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) | in tegra_emc_prepare_timing_change()
744 if (emc->dram_type == DRAM_TYPE_DDR3) { in tegra_emc_prepare_timing_change()
745 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
746 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
747 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
748 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); in tegra_emc_prepare_timing_change()
750 if ((timing->emc_mode_reset != last->emc_mode_reset) || in tegra_emc_prepare_timing_change()
752 val = timing->emc_mode_reset; in tegra_emc_prepare_timing_change()
762 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
763 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); in tegra_emc_prepare_timing_change()
764 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
765 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
766 if (timing->emc_mode_4 != last->emc_mode_4) in tegra_emc_prepare_timing_change()
767 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
771 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { in tegra_emc_prepare_timing_change()
773 if (emc->dram_num > 1) in tegra_emc_prepare_timing_change()
779 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS); in tegra_emc_prepare_timing_change()
781 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) in tegra_emc_prepare_timing_change()
782 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
788 readl(emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
790 return 0; in tegra_emc_prepare_timing_change()
796 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_complete_timing_change() local
797 struct emc_timing *last = &emc->last_timing; in tegra_emc_complete_timing_change()
800 if (!timing) in tegra_emc_complete_timing_change()
807 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) in tegra_emc_complete_timing_change()
808 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
809 emc->regs + EMC_AUTO_CAL_INTERVAL); in tegra_emc_complete_timing_change()
811 /* Restore dynamic self-refresh */ in tegra_emc_complete_timing_change()
812 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
813 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
816 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); in tegra_emc_complete_timing_change()
819 if (emc->dram_type == DRAM_TYPE_LPDDR3 && in tegra_emc_complete_timing_change()
820 timing->emc_bgbias_ctl0 & in tegra_emc_complete_timing_change()
822 val = timing->emc_bgbias_ctl0; in tegra_emc_complete_timing_change()
825 writel(val, emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_complete_timing_change()
827 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_complete_timing_change()
828 readl(emc->regs + EMC_BGBIAS_CTL0) != in tegra_emc_complete_timing_change()
829 timing->emc_bgbias_ctl0) { in tegra_emc_complete_timing_change()
830 writel(timing->emc_bgbias_ctl0, in tegra_emc_complete_timing_change()
831 emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_complete_timing_change()
834 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
835 emc->regs + EMC_AUTO_CAL_INTERVAL); in tegra_emc_complete_timing_change()
838 /* Wait for timing to settle */ in tegra_emc_complete_timing_change()
842 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
845 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
851 struct emc_timing *timing) in emc_read_current_timing() argument
855 for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i) in emc_read_current_timing()
856 timing->emc_burst_data[i] = in emc_read_current_timing()
857 readl(emc->regs + emc_burst_regs[i]); in emc_read_current_timing()
859 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
861 timing->emc_auto_cal_interval = 0; in emc_read_current_timing()
862 timing->emc_zcal_cnt_long = 0; in emc_read_current_timing()
863 timing->emc_mode_1 = 0; in emc_read_current_timing()
864 timing->emc_mode_2 = 0; in emc_read_current_timing()
865 timing->emc_mode_4 = 0; in emc_read_current_timing()
866 timing->emc_mode_reset = 0; in emc_read_current_timing()
871 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()
872 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_init()
873 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; in emc_init()
875 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_init()
877 emc_read_current_timing(emc, &emc->last_timing); in emc_init()
879 return 0; in emc_init()
883 struct emc_timing *timing, in load_one_timing_from_dt() argument
889 err = of_property_read_u32(node, "clock-frequency", &value); in load_one_timing_from_dt()
891 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n", in load_one_timing_from_dt()
896 timing->rate = value; in load_one_timing_from_dt()
898 err = of_property_read_u32_array(node, "nvidia,emc-configuration", in load_one_timing_from_dt()
899 timing->emc_burst_data, in load_one_timing_from_dt()
900 ARRAY_SIZE(timing->emc_burst_data)); in load_one_timing_from_dt()
902 dev_err(emc->dev, in load_one_timing_from_dt()
903 "timing %pOFn: failed to read emc burst data: %d\n", in load_one_timing_from_dt()
909 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
911 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \ in load_one_timing_from_dt()
917 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config") in load_one_timing_from_dt()
918 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2") in load_one_timing_from_dt()
919 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3") in load_one_timing_from_dt()
920 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") in load_one_timing_from_dt()
921 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0") in load_one_timing_from_dt()
922 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") in load_one_timing_from_dt()
923 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") in load_one_timing_from_dt()
924 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") in load_one_timing_from_dt()
925 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1") in load_one_timing_from_dt()
926 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2") in load_one_timing_from_dt()
927 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4") in load_one_timing_from_dt()
928 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset") in load_one_timing_from_dt()
929 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt") in load_one_timing_from_dt()
930 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") in load_one_timing_from_dt()
931 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2") in load_one_timing_from_dt()
932 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") in load_one_timing_from_dt()
933 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval") in load_one_timing_from_dt()
937 return 0; in load_one_timing_from_dt()
945 if (a->rate < b->rate) in cmp_timings()
946 return -1; in cmp_timings()
947 else if (a->rate == b->rate) in cmp_timings()
948 return 0; in cmp_timings()
958 struct emc_timing *timing; in tegra_emc_load_timings_from_dt() local
959 unsigned int i = 0; in tegra_emc_load_timings_from_dt()
962 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
964 if (!emc->timings) in tegra_emc_load_timings_from_dt()
965 return -ENOMEM; in tegra_emc_load_timings_from_dt()
967 emc->num_timings = child_count; in tegra_emc_load_timings_from_dt()
970 timing = &emc->timings[i++]; in tegra_emc_load_timings_from_dt()
972 err = load_one_timing_from_dt(emc, timing, child); in tegra_emc_load_timings_from_dt()
979 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
982 return 0; in tegra_emc_load_timings_from_dt()
986 { .compatible = "nvidia,tegra124-emc" },
987 { .compatible = "nvidia,tegra132-emc" },
1000 err = of_property_read_u32(np, "nvidia,ram-code", &value); in tegra_emc_find_node_by_ram_code()
1014 * to control the EMC frequency. The top-level directory can be found here:
1020 * - available_rates: This file contains a list of valid, space-separated
1023 * - min_rate: Writing a value to this file sets the given frequency as the
1028 * - max_rate: Similarily to the min_rate file, writing a value to this file
1039 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1040 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1049 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show()
1053 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1054 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1060 return 0; in tegra_emc_debug_available_rates_show()
1069 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1071 return 0; in tegra_emc_debug_min_rate_get()
1080 return -EINVAL; in tegra_emc_debug_min_rate_set()
1082 err = clk_set_min_rate(emc->clk, rate); in tegra_emc_debug_min_rate_set()
1083 if (err < 0) in tegra_emc_debug_min_rate_set()
1086 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1088 return 0; in tegra_emc_debug_min_rate_set()
1099 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1101 return 0; in tegra_emc_debug_max_rate_get()
1110 return -EINVAL; in tegra_emc_debug_max_rate_set()
1112 err = clk_set_max_rate(emc->clk, rate); in tegra_emc_debug_max_rate_set()
1113 if (err < 0) in tegra_emc_debug_max_rate_set()
1116 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1118 return 0; in tegra_emc_debug_max_rate_set()
1130 emc->clk = devm_clk_get(dev, "emc"); in emc_debugfs_init()
1131 if (IS_ERR(emc->clk)) { in emc_debugfs_init()
1132 if (PTR_ERR(emc->clk) != -ENODEV) { in emc_debugfs_init()
1134 PTR_ERR(emc->clk)); in emc_debugfs_init()
1139 emc->debugfs.min_rate = ULONG_MAX; in emc_debugfs_init()
1140 emc->debugfs.max_rate = 0; in emc_debugfs_init()
1142 for (i = 0; i < emc->num_timings; i++) { in emc_debugfs_init()
1143 if (emc->timings[i].rate < emc->debugfs.min_rate) in emc_debugfs_init()
1144 emc->debugfs.min_rate = emc->timings[i].rate; in emc_debugfs_init()
1146 if (emc->timings[i].rate > emc->debugfs.max_rate) in emc_debugfs_init()
1147 emc->debugfs.max_rate = emc->timings[i].rate; in emc_debugfs_init()
1150 if (!emc->num_timings) { in emc_debugfs_init()
1151 emc->debugfs.min_rate = clk_get_rate(emc->clk); in emc_debugfs_init()
1152 emc->debugfs.max_rate = emc->debugfs.min_rate; in emc_debugfs_init()
1155 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in emc_debugfs_init()
1156 emc->debugfs.max_rate); in emc_debugfs_init()
1157 if (err < 0) { in emc_debugfs_init()
1158 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in emc_debugfs_init()
1159 emc->debugfs.min_rate, emc->debugfs.max_rate, in emc_debugfs_init()
1160 emc->clk); in emc_debugfs_init()
1164 emc->debugfs.root = debugfs_create_dir("emc", NULL); in emc_debugfs_init()
1165 if (!emc->debugfs.root) { in emc_debugfs_init()
1170 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, in emc_debugfs_init()
1172 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in emc_debugfs_init()
1174 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in emc_debugfs_init()
1187 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1189 return -ENOMEM; in tegra_emc_probe()
1191 emc->dev = &pdev->dev; in tegra_emc_probe()
1193 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in tegra_emc_probe()
1194 emc->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_emc_probe()
1195 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1196 return PTR_ERR(emc->regs); in tegra_emc_probe()
1198 np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); in tegra_emc_probe()
1200 dev_err(&pdev->dev, "could not get memory controller\n"); in tegra_emc_probe()
1201 return -ENOENT; in tegra_emc_probe()
1207 return -ENOENT; in tegra_emc_probe()
1209 emc->mc = platform_get_drvdata(mc); in tegra_emc_probe()
1210 if (!emc->mc) in tegra_emc_probe()
1211 return -EPROBE_DEFER; in tegra_emc_probe()
1215 np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code); in tegra_emc_probe()
1217 dev_err(&pdev->dev, in tegra_emc_probe()
1220 return -ENOENT; in tegra_emc_probe()
1228 if (emc->num_timings == 0) { in tegra_emc_probe()
1229 dev_err(&pdev->dev, in tegra_emc_probe()
1232 return -ENOENT; in tegra_emc_probe()
1237 dev_err(&pdev->dev, "EMC initialization failed: %d\n", err); in tegra_emc_probe()
1244 emc_debugfs_init(&pdev->dev, emc); in tegra_emc_probe()
1246 return 0; in tegra_emc_probe()
1252 .name = "tegra-emc",